ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/kernel/smpboot.c @ 6002:565cec5b9cc2

merge?
author cl349@firebug.cl.cam.ac.uk
date Tue Aug 02 23:13:50 2005 +0000 (2005-08-02)
parents 1032271a0abf c8279f7c14e2
children d4fd332df775 04dfb5158f3a f294acb25858
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
41 #include <linux/mm.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/irq.h>
46 #include <linux/bootmem.h>
47 #include <linux/notifier.h>
48 #include <linux/cpu.h>
49 #include <linux/percpu.h>
51 #include <linux/delay.h>
52 #include <linux/mc146818rtc.h>
53 #include <asm/tlbflush.h>
54 #include <asm/desc.h>
55 #include <asm/arch_hooks.h>
57 #include <asm/smp_alt.h>
59 #ifndef CONFIG_X86_IO_APIC
60 #define Dprintk(args...)
61 #endif
62 #include <mach_wakecpu.h>
63 #include <smpboot_hooks.h>
65 /* Set if we find a B stepping CPU */
66 static int __initdata smp_b_stepping;
68 /* Number of siblings per CPU package */
69 int smp_num_siblings = 1;
70 int phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */
71 EXPORT_SYMBOL(phys_proc_id);
72 int cpu_core_id[NR_CPUS]; /* Core ID of each logical CPU */
73 EXPORT_SYMBOL(cpu_core_id);
75 /* bitmap of online cpus */
76 cpumask_t cpu_online_map;
78 cpumask_t cpu_callin_map;
79 cpumask_t cpu_callout_map;
80 static cpumask_t smp_commenced_mask;
82 /* Per CPU bogomips and other parameters */
83 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
85 u8 x86_cpu_to_apicid[NR_CPUS] =
86 { [0 ... NR_CPUS-1] = 0xff };
87 EXPORT_SYMBOL(x86_cpu_to_apicid);
89 #if 0
90 /*
91 * Trampoline 80x86 program as an array.
92 */
94 extern unsigned char trampoline_data [];
95 extern unsigned char trampoline_end [];
96 static unsigned char *trampoline_base;
97 static int trampoline_exec;
98 #endif
100 #ifdef CONFIG_HOTPLUG_CPU
101 /* State of each CPU. */
102 DEFINE_PER_CPU(int, cpu_state) = { 0 };
103 #endif
105 static DEFINE_PER_CPU(int, resched_irq);
106 static DEFINE_PER_CPU(int, callfunc_irq);
107 static char resched_name[NR_CPUS][15];
108 static char callfunc_name[NR_CPUS][15];
110 #if 0
111 /*
112 * Currently trivial. Write the real->protected mode
113 * bootstrap into the page concerned. The caller
114 * has made sure it's suitably aligned.
115 */
117 static unsigned long __init setup_trampoline(void)
118 {
119 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
120 return virt_to_phys(trampoline_base);
121 }
122 #endif
124 static void map_cpu_to_logical_apicid(void);
126 /*
127 * We are called very early to get the low memory for the
128 * SMP bootup trampoline page.
129 */
130 void __init smp_alloc_memory(void)
131 {
132 #if 1
133 int cpu;
135 for (cpu = 1; cpu < NR_CPUS; cpu++) {
136 cpu_gdt_descr[cpu].address = (unsigned long)
137 alloc_bootmem_low_pages(PAGE_SIZE);
138 /* XXX free unused pages later */
139 }
140 #else
141 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
142 /*
143 * Has to be in very low memory so we can execute
144 * real-mode AP code.
145 */
146 if (__pa(trampoline_base) >= 0x9F000)
147 BUG();
148 /*
149 * Make the SMP trampoline executable:
150 */
151 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
152 #endif
153 }
155 /*
156 * The bootstrap kernel entry code has set these up. Save them for
157 * a given CPU
158 */
160 static void __init smp_store_cpu_info(int id)
161 {
162 struct cpuinfo_x86 *c = cpu_data + id;
164 *c = boot_cpu_data;
165 if (id!=0)
166 identify_cpu(c);
167 /*
168 * Mask B, Pentium, but not Pentium MMX
169 */
170 if (c->x86_vendor == X86_VENDOR_INTEL &&
171 c->x86 == 5 &&
172 c->x86_mask >= 1 && c->x86_mask <= 4 &&
173 c->x86_model <= 3)
174 /*
175 * Remember we have B step Pentia with bugs
176 */
177 smp_b_stepping = 1;
179 /*
180 * Certain Athlons might work (for various values of 'work') in SMP
181 * but they are not certified as MP capable.
182 */
183 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
185 /* Athlon 660/661 is valid. */
186 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
187 goto valid_k7;
189 /* Duron 670 is valid */
190 if ((c->x86_model==7) && (c->x86_mask==0))
191 goto valid_k7;
193 /*
194 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
195 * It's worth noting that the A5 stepping (662) of some Athlon XP's
196 * have the MP bit set.
197 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
198 */
199 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
200 ((c->x86_model==7) && (c->x86_mask>=1)) ||
201 (c->x86_model> 7))
202 if (cpu_has_mp)
203 goto valid_k7;
205 /* If we get here, it's not a certified SMP capable AMD system. */
206 tainted |= TAINT_UNSAFE_SMP;
207 }
209 valid_k7:
210 ;
211 }
213 #if 0
214 /*
215 * TSC synchronization.
216 *
217 * We first check whether all CPUs have their TSC's synchronized,
218 * then we print a warning if not, and always resync.
219 */
221 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
222 static atomic_t tsc_count_start = ATOMIC_INIT(0);
223 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
224 static unsigned long long tsc_values[NR_CPUS];
226 #define NR_LOOPS 5
228 static void __init synchronize_tsc_bp (void)
229 {
230 int i;
231 unsigned long long t0;
232 unsigned long long sum, avg;
233 long long delta;
234 unsigned long one_usec;
235 int buggy = 0;
237 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
239 /* convert from kcyc/sec to cyc/usec */
240 one_usec = cpu_khz / 1000;
242 atomic_set(&tsc_start_flag, 1);
243 wmb();
245 /*
246 * We loop a few times to get a primed instruction cache,
247 * then the last pass is more or less synchronized and
248 * the BP and APs set their cycle counters to zero all at
249 * once. This reduces the chance of having random offsets
250 * between the processors, and guarantees that the maximum
251 * delay between the cycle counters is never bigger than
252 * the latency of information-passing (cachelines) between
253 * two CPUs.
254 */
255 for (i = 0; i < NR_LOOPS; i++) {
256 /*
257 * all APs synchronize but they loop on '== num_cpus'
258 */
259 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
260 mb();
261 atomic_set(&tsc_count_stop, 0);
262 wmb();
263 /*
264 * this lets the APs save their current TSC:
265 */
266 atomic_inc(&tsc_count_start);
268 rdtscll(tsc_values[smp_processor_id()]);
269 /*
270 * We clear the TSC in the last loop:
271 */
272 if (i == NR_LOOPS-1)
273 write_tsc(0, 0);
275 /*
276 * Wait for all APs to leave the synchronization point:
277 */
278 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
279 mb();
280 atomic_set(&tsc_count_start, 0);
281 wmb();
282 atomic_inc(&tsc_count_stop);
283 }
285 sum = 0;
286 for (i = 0; i < NR_CPUS; i++) {
287 if (cpu_isset(i, cpu_callout_map)) {
288 t0 = tsc_values[i];
289 sum += t0;
290 }
291 }
292 avg = sum;
293 do_div(avg, num_booting_cpus());
295 sum = 0;
296 for (i = 0; i < NR_CPUS; i++) {
297 if (!cpu_isset(i, cpu_callout_map))
298 continue;
299 delta = tsc_values[i] - avg;
300 if (delta < 0)
301 delta = -delta;
302 /*
303 * We report bigger than 2 microseconds clock differences.
304 */
305 if (delta > 2*one_usec) {
306 long realdelta;
307 if (!buggy) {
308 buggy = 1;
309 printk("\n");
310 }
311 realdelta = delta;
312 do_div(realdelta, one_usec);
313 if (tsc_values[i] < avg)
314 realdelta = -realdelta;
316 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
317 }
319 sum += delta;
320 }
321 if (!buggy)
322 printk("passed.\n");
323 }
325 static void __init synchronize_tsc_ap (void)
326 {
327 int i;
329 /*
330 * Not every cpu is online at the time
331 * this gets called, so we first wait for the BP to
332 * finish SMP initialization:
333 */
334 while (!atomic_read(&tsc_start_flag)) mb();
336 for (i = 0; i < NR_LOOPS; i++) {
337 atomic_inc(&tsc_count_start);
338 while (atomic_read(&tsc_count_start) != num_booting_cpus())
339 mb();
341 rdtscll(tsc_values[smp_processor_id()]);
342 if (i == NR_LOOPS-1)
343 write_tsc(0, 0);
345 atomic_inc(&tsc_count_stop);
346 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
347 }
348 }
349 #undef NR_LOOPS
350 #endif
352 extern void calibrate_delay(void);
354 static atomic_t init_deasserted;
356 static void __init smp_callin(void)
357 {
358 int cpuid, phys_id;
359 unsigned long timeout;
361 #if 0
362 /*
363 * If waken up by an INIT in an 82489DX configuration
364 * we may get here before an INIT-deassert IPI reaches
365 * our local APIC. We have to wait for the IPI or we'll
366 * lock up on an APIC access.
367 */
368 wait_for_init_deassert(&init_deasserted);
369 #endif
371 /*
372 * (This works even if the APIC is not enabled.)
373 */
374 phys_id = smp_processor_id();
375 cpuid = smp_processor_id();
376 if (cpu_isset(cpuid, cpu_callin_map)) {
377 printk("huh, phys CPU#%d, CPU#%d already present??\n",
378 phys_id, cpuid);
379 BUG();
380 }
381 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
383 /*
384 * STARTUP IPIs are fragile beasts as they might sometimes
385 * trigger some glue motherboard logic. Complete APIC bus
386 * silence for 1 second, this overestimates the time the
387 * boot CPU is spending to send the up to 2 STARTUP IPIs
388 * by a factor of two. This should be enough.
389 */
391 /*
392 * Waiting 2s total for startup (udelay is not yet working)
393 */
394 timeout = jiffies + 2*HZ;
395 while (time_before(jiffies, timeout)) {
396 /*
397 * Has the boot CPU finished it's STARTUP sequence?
398 */
399 if (cpu_isset(cpuid, cpu_callout_map))
400 break;
401 rep_nop();
402 }
404 if (!time_before(jiffies, timeout)) {
405 printk("BUG: CPU%d started up but did not get a callout!\n",
406 cpuid);
407 BUG();
408 }
410 #if 0
411 /*
412 * the boot CPU has finished the init stage and is spinning
413 * on callin_map until we finish. We are free to set up this
414 * CPU, first the APIC. (this is probably redundant on most
415 * boards)
416 */
418 Dprintk("CALLIN, before setup_local_APIC().\n");
419 smp_callin_clear_local_apic();
420 setup_local_APIC();
421 #endif
422 map_cpu_to_logical_apicid();
424 /*
425 * Get our bogomips.
426 */
427 calibrate_delay();
428 Dprintk("Stack at about %p\n",&cpuid);
430 /*
431 * Save our processor parameters
432 */
433 smp_store_cpu_info(cpuid);
435 #if 0
436 disable_APIC_timer();
437 #endif
439 /*
440 * Allow the master to continue.
441 */
442 cpu_set(cpuid, cpu_callin_map);
444 #if 0
445 /*
446 * Synchronize the TSC with the BP
447 */
448 if (cpu_has_tsc && cpu_khz)
449 synchronize_tsc_ap();
450 #endif
451 }
453 static int cpucount;
456 static irqreturn_t ldebug_interrupt(
457 int irq, void *dev_id, struct pt_regs *regs)
458 {
459 return IRQ_HANDLED;
460 }
462 static DEFINE_PER_CPU(int, ldebug_irq);
463 static char ldebug_name[NR_CPUS][15];
465 void ldebug_setup(void)
466 {
467 int cpu = smp_processor_id();
469 per_cpu(ldebug_irq, cpu) = bind_virq_to_irq(VIRQ_DEBUG);
470 sprintf(ldebug_name[cpu], "ldebug%d", cpu);
471 BUG_ON(request_irq(per_cpu(ldebug_irq, cpu), ldebug_interrupt,
472 SA_INTERRUPT, ldebug_name[cpu], NULL));
473 }
476 extern void local_setup_timer(void);
478 /*
479 * Activate a secondary processor.
480 */
481 static void __init start_secondary(void *unused)
482 {
483 /*
484 * Dont put anything before smp_callin(), SMP
485 * booting is too fragile that we want to limit the
486 * things done here to the most necessary things.
487 */
488 cpu_init();
489 smp_callin();
490 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
491 rep_nop();
492 local_setup_timer();
493 ldebug_setup();
494 smp_intr_init();
495 local_irq_enable();
496 /*
497 * low-memory mappings have been cleared, flush them from
498 * the local TLBs too.
499 */
500 local_flush_tlb();
501 cpu_set(smp_processor_id(), cpu_online_map);
503 /* We can take interrupts now: we're officially "up". */
504 local_irq_enable();
506 wmb();
507 cpu_idle();
508 }
510 /*
511 * Everything has been set up for the secondary
512 * CPUs - they just need to reload everything
513 * from the task structure
514 * This function must not return.
515 */
516 void __init initialize_secondary(void)
517 {
518 /*
519 * We don't actually need to load the full TSS,
520 * basically just the stack pointer and the eip.
521 */
523 asm volatile(
524 "movl %0,%%esp\n\t"
525 "jmp *%1"
526 :
527 :"r" (current->thread.esp),"r" (current->thread.eip));
528 }
530 extern struct {
531 void * esp;
532 unsigned short ss;
533 } stack_start;
535 #ifdef CONFIG_NUMA
537 /* which logical CPUs are on which nodes */
538 cpumask_t node_2_cpu_mask[MAX_NUMNODES] =
539 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
540 /* which node each logical CPU is on */
541 int cpu_2_node[NR_CPUS] = { [0 ... NR_CPUS-1] = 0 };
542 EXPORT_SYMBOL(cpu_2_node);
544 /* set up a mapping between cpu and node. */
545 static inline void map_cpu_to_node(int cpu, int node)
546 {
547 printk("Mapping cpu %d to node %d\n", cpu, node);
548 cpu_set(cpu, node_2_cpu_mask[node]);
549 cpu_2_node[cpu] = node;
550 }
552 /* undo a mapping between cpu and node. */
553 static inline void unmap_cpu_to_node(int cpu)
554 {
555 int node;
557 printk("Unmapping cpu %d from all nodes\n", cpu);
558 for (node = 0; node < MAX_NUMNODES; node ++)
559 cpu_clear(cpu, node_2_cpu_mask[node]);
560 cpu_2_node[cpu] = 0;
561 }
562 #else /* !CONFIG_NUMA */
564 #define map_cpu_to_node(cpu, node) ({})
565 #define unmap_cpu_to_node(cpu) ({})
567 #endif /* CONFIG_NUMA */
569 u8 cpu_2_logical_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
571 static void map_cpu_to_logical_apicid(void)
572 {
573 int cpu = smp_processor_id();
574 int apicid = smp_processor_id();
576 cpu_2_logical_apicid[cpu] = apicid;
577 map_cpu_to_node(cpu, apicid_to_node(apicid));
578 }
580 static void unmap_cpu_to_logical_apicid(int cpu)
581 {
582 cpu_2_logical_apicid[cpu] = BAD_APICID;
583 unmap_cpu_to_node(cpu);
584 }
586 #if APIC_DEBUG
587 static inline void __inquire_remote_apic(int apicid)
588 {
589 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
590 char *names[] = { "ID", "VERSION", "SPIV" };
591 int timeout, status;
593 printk("Inquiring remote APIC #%d...\n", apicid);
595 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
596 printk("... APIC #%d %s: ", apicid, names[i]);
598 /*
599 * Wait for idle.
600 */
601 apic_wait_icr_idle();
603 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
604 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
606 timeout = 0;
607 do {
608 udelay(100);
609 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
610 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
612 switch (status) {
613 case APIC_ICR_RR_VALID:
614 status = apic_read(APIC_RRR);
615 printk("%08x\n", status);
616 break;
617 default:
618 printk("failed\n");
619 }
620 }
621 }
622 #endif
624 #if 0
625 #ifdef WAKE_SECONDARY_VIA_NMI
626 /*
627 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
628 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
629 * won't ... remember to clear down the APIC, etc later.
630 */
631 static int __init
632 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
633 {
634 unsigned long send_status = 0, accept_status = 0;
635 int timeout, maxlvt;
637 /* Target chip */
638 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
640 /* Boot on the stack */
641 /* Kick the second */
642 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
644 Dprintk("Waiting for send to finish...\n");
645 timeout = 0;
646 do {
647 Dprintk("+");
648 udelay(100);
649 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
650 } while (send_status && (timeout++ < 1000));
652 /*
653 * Give the other CPU some time to accept the IPI.
654 */
655 udelay(200);
656 /*
657 * Due to the Pentium erratum 3AP.
658 */
659 maxlvt = get_maxlvt();
660 if (maxlvt > 3) {
661 apic_read_around(APIC_SPIV);
662 apic_write(APIC_ESR, 0);
663 }
664 accept_status = (apic_read(APIC_ESR) & 0xEF);
665 Dprintk("NMI sent.\n");
667 if (send_status)
668 printk("APIC never delivered???\n");
669 if (accept_status)
670 printk("APIC delivery error (%lx).\n", accept_status);
672 return (send_status | accept_status);
673 }
674 #endif /* WAKE_SECONDARY_VIA_NMI */
676 #ifdef WAKE_SECONDARY_VIA_INIT
677 static int __init
678 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
679 {
680 unsigned long send_status = 0, accept_status = 0;
681 int maxlvt, timeout, num_starts, j;
683 /*
684 * Be paranoid about clearing APIC errors.
685 */
686 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
687 apic_read_around(APIC_SPIV);
688 apic_write(APIC_ESR, 0);
689 apic_read(APIC_ESR);
690 }
692 Dprintk("Asserting INIT.\n");
694 /*
695 * Turn INIT on target chip
696 */
697 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
699 /*
700 * Send IPI
701 */
702 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
703 | APIC_DM_INIT);
705 Dprintk("Waiting for send to finish...\n");
706 timeout = 0;
707 do {
708 Dprintk("+");
709 udelay(100);
710 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
711 } while (send_status && (timeout++ < 1000));
713 mdelay(10);
715 Dprintk("Deasserting INIT.\n");
717 /* Target chip */
718 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
720 /* Send IPI */
721 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
723 Dprintk("Waiting for send to finish...\n");
724 timeout = 0;
725 do {
726 Dprintk("+");
727 udelay(100);
728 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
729 } while (send_status && (timeout++ < 1000));
731 atomic_set(&init_deasserted, 1);
733 /*
734 * Should we send STARTUP IPIs ?
735 *
736 * Determine this based on the APIC version.
737 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
738 */
739 if (APIC_INTEGRATED(apic_version[phys_apicid]))
740 num_starts = 2;
741 else
742 num_starts = 0;
744 /*
745 * Run STARTUP IPI loop.
746 */
747 Dprintk("#startup loops: %d.\n", num_starts);
749 maxlvt = get_maxlvt();
751 for (j = 1; j <= num_starts; j++) {
752 Dprintk("Sending STARTUP #%d.\n",j);
753 apic_read_around(APIC_SPIV);
754 apic_write(APIC_ESR, 0);
755 apic_read(APIC_ESR);
756 Dprintk("After apic_write.\n");
758 /*
759 * STARTUP IPI
760 */
762 /* Target chip */
763 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
765 /* Boot on the stack */
766 /* Kick the second */
767 apic_write_around(APIC_ICR, APIC_DM_STARTUP
768 | (start_eip >> 12));
770 /*
771 * Give the other CPU some time to accept the IPI.
772 */
773 udelay(300);
775 Dprintk("Startup point 1.\n");
777 Dprintk("Waiting for send to finish...\n");
778 timeout = 0;
779 do {
780 Dprintk("+");
781 udelay(100);
782 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
783 } while (send_status && (timeout++ < 1000));
785 /*
786 * Give the other CPU some time to accept the IPI.
787 */
788 udelay(200);
789 /*
790 * Due to the Pentium erratum 3AP.
791 */
792 if (maxlvt > 3) {
793 apic_read_around(APIC_SPIV);
794 apic_write(APIC_ESR, 0);
795 }
796 accept_status = (apic_read(APIC_ESR) & 0xEF);
797 if (send_status || accept_status)
798 break;
799 }
800 Dprintk("After Startup.\n");
802 if (send_status)
803 printk("APIC never delivered???\n");
804 if (accept_status)
805 printk("APIC delivery error (%lx).\n", accept_status);
807 return (send_status | accept_status);
808 }
809 #endif /* WAKE_SECONDARY_VIA_INIT */
810 #endif
812 extern cpumask_t cpu_initialized;
814 static int __init do_boot_cpu(int apicid)
815 /*
816 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
817 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
818 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
819 */
820 {
821 struct task_struct *idle;
822 unsigned long boot_error;
823 int timeout, cpu;
824 unsigned long start_eip;
825 #if 0
826 unsigned short nmi_high = 0, nmi_low = 0;
827 #endif
828 vcpu_guest_context_t ctxt;
829 extern void startup_32_smp(void);
830 extern void hypervisor_callback(void);
831 extern void failsafe_callback(void);
832 extern void smp_trap_init(trap_info_t *);
833 int i;
835 cpu = ++cpucount;
836 /*
837 * We can't use kernel_thread since we must avoid to
838 * reschedule the child.
839 */
840 idle = fork_idle(cpu);
841 if (IS_ERR(idle))
842 panic("failed fork for CPU %d", cpu);
843 idle->thread.eip = (unsigned long) start_secondary;
844 /* start_eip had better be page-aligned! */
845 start_eip = (unsigned long)startup_32_smp;
847 /* So we see what's up */
848 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
849 /* Stack for startup_32 can be just as for start_secondary onwards */
850 stack_start.esp = (void *) idle->thread.esp;
852 irq_ctx_init(cpu);
854 /*
855 * This grunge runs the startup process for
856 * the targeted processor.
857 */
859 atomic_set(&init_deasserted, 0);
861 #if 1
862 if (cpu_gdt_descr[0].size > PAGE_SIZE)
863 BUG();
864 cpu_gdt_descr[cpu].size = cpu_gdt_descr[0].size;
865 printk("GDT: copying %d bytes from %lx to %lx\n",
866 cpu_gdt_descr[0].size, cpu_gdt_descr[0].address,
867 cpu_gdt_descr[cpu].address);
868 memcpy((void *)cpu_gdt_descr[cpu].address,
869 (void *)cpu_gdt_descr[0].address, cpu_gdt_descr[0].size);
871 memset(&ctxt, 0, sizeof(ctxt));
873 ctxt.user_regs.ds = __USER_DS;
874 ctxt.user_regs.es = __USER_DS;
875 ctxt.user_regs.fs = 0;
876 ctxt.user_regs.gs = 0;
877 ctxt.user_regs.ss = __KERNEL_DS;
878 ctxt.user_regs.cs = __KERNEL_CS;
879 ctxt.user_regs.eip = start_eip;
880 ctxt.user_regs.esp = idle->thread.esp;
881 ctxt.user_regs.eflags = (1<<9) | (1<<2) | (idle->thread.io_pl<<12);
883 /* FPU is set up to default initial state. */
884 memset(&ctxt.fpu_ctxt, 0, sizeof(ctxt.fpu_ctxt));
886 /* Virtual IDT is empty at start-of-day. */
887 for ( i = 0; i < 256; i++ )
888 {
889 ctxt.trap_ctxt[i].vector = i;
890 ctxt.trap_ctxt[i].cs = FLAT_KERNEL_CS;
891 }
892 smp_trap_init(ctxt.trap_ctxt);
894 /* No LDT. */
895 ctxt.ldt_ents = 0;
897 {
898 unsigned long va;
899 int f;
901 for (va = cpu_gdt_descr[cpu].address, f = 0;
902 va < cpu_gdt_descr[cpu].address + cpu_gdt_descr[cpu].size;
903 va += PAGE_SIZE, f++) {
904 ctxt.gdt_frames[f] = virt_to_machine(va) >> PAGE_SHIFT;
905 make_page_readonly((void *)va);
906 }
907 ctxt.gdt_ents = cpu_gdt_descr[cpu].size / 8;
908 }
910 /* Ring 1 stack is the initial stack. */
911 ctxt.kernel_ss = __KERNEL_DS;
912 ctxt.kernel_sp = idle->thread.esp;
914 /* Callback handlers. */
915 ctxt.event_callback_cs = __KERNEL_CS;
916 ctxt.event_callback_eip = (unsigned long)hypervisor_callback;
917 ctxt.failsafe_callback_cs = __KERNEL_CS;
918 ctxt.failsafe_callback_eip = (unsigned long)failsafe_callback;
920 ctxt.ctrlreg[3] = (unsigned long)virt_to_machine(swapper_pg_dir);
922 boot_error = HYPERVISOR_boot_vcpu(cpu, &ctxt);
923 printk("boot error: %ld\n", boot_error);
925 if (!boot_error) {
926 /*
927 * allow APs to start initializing.
928 */
929 Dprintk("Before Callout %d.\n", cpu);
930 cpu_set(cpu, cpu_callout_map);
931 Dprintk("After Callout %d.\n", cpu);
933 /*
934 * Wait 5s total for a response
935 */
936 for (timeout = 0; timeout < 50000; timeout++) {
937 if (cpu_isset(cpu, cpu_callin_map))
938 break; /* It has booted */
939 udelay(100);
940 }
942 if (cpu_isset(cpu, cpu_callin_map)) {
943 /* number CPUs logically, starting from 1 (BSP is 0) */
944 Dprintk("OK.\n");
945 printk("CPU%d: ", cpu);
946 print_cpu_info(&cpu_data[cpu]);
947 Dprintk("CPU has booted.\n");
948 } else {
949 boot_error= 1;
950 }
951 }
952 x86_cpu_to_apicid[cpu] = apicid;
953 if (boot_error) {
954 /* Try to put things back the way they were before ... */
955 unmap_cpu_to_logical_apicid(cpu);
956 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
957 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
958 cpucount--;
959 }
961 #else
962 Dprintk("Setting warm reset code and vector.\n");
964 store_NMI_vector(&nmi_high, &nmi_low);
966 smpboot_setup_warm_reset_vector(start_eip);
968 /*
969 * Starting actual IPI sequence...
970 */
971 boot_error = wakeup_secondary_cpu(apicid, start_eip);
973 if (!boot_error) {
974 /*
975 * allow APs to start initializing.
976 */
977 Dprintk("Before Callout %d.\n", cpu);
978 cpu_set(cpu, cpu_callout_map);
979 Dprintk("After Callout %d.\n", cpu);
981 /*
982 * Wait 5s total for a response
983 */
984 for (timeout = 0; timeout < 50000; timeout++) {
985 if (cpu_isset(cpu, cpu_callin_map))
986 break; /* It has booted */
987 udelay(100);
988 }
990 if (cpu_isset(cpu, cpu_callin_map)) {
991 /* number CPUs logically, starting from 1 (BSP is 0) */
992 Dprintk("OK.\n");
993 printk("CPU%d: ", cpu);
994 print_cpu_info(&cpu_data[cpu]);
995 Dprintk("CPU has booted.\n");
996 } else {
997 boot_error= 1;
998 if (*((volatile unsigned char *)trampoline_base)
999 == 0xA5)
1000 /* trampoline started but...? */
1001 printk("Stuck ??\n");
1002 else
1003 /* trampoline code not run */
1004 printk("Not responding.\n");
1005 inquire_remote_apic(apicid);
1008 x86_cpu_to_apicid[cpu] = apicid;
1009 if (boot_error) {
1010 /* Try to put things back the way they were before ... */
1011 unmap_cpu_to_logical_apicid(cpu);
1012 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
1013 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
1014 cpucount--;
1017 /* mark "stuck" area as not stuck */
1018 *((volatile unsigned long *)trampoline_base) = 0;
1019 #endif
1021 return boot_error;
1024 static void smp_tune_scheduling (void)
1026 unsigned long cachesize; /* kB */
1027 unsigned long bandwidth = 350; /* MB/s */
1028 /*
1029 * Rough estimation for SMP scheduling, this is the number of
1030 * cycles it takes for a fully memory-limited process to flush
1031 * the SMP-local cache.
1033 * (For a P5 this pretty much means we will choose another idle
1034 * CPU almost always at wakeup time (this is due to the small
1035 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1036 * the cache size)
1037 */
1039 if (!cpu_khz) {
1040 /*
1041 * this basically disables processor-affinity
1042 * scheduling on SMP without a TSC.
1043 */
1044 return;
1045 } else {
1046 cachesize = boot_cpu_data.x86_cache_size;
1047 if (cachesize == -1) {
1048 cachesize = 16; /* Pentiums, 2x8kB cache */
1049 bandwidth = 100;
1054 /*
1055 * Cycle through the processors sending APIC IPIs to boot each.
1056 */
1058 #if 0
1059 static int boot_cpu_logical_apicid;
1060 #endif
1061 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1062 void *xquad_portio;
1064 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
1065 cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
1066 EXPORT_SYMBOL(cpu_core_map);
1068 static void __init smp_boot_cpus(unsigned int max_cpus)
1070 int cpu, kicked;
1071 unsigned long bogosum = 0;
1072 #if 0
1073 int apicid, bit;
1074 #endif
1076 /*
1077 * Setup boot CPU information
1078 */
1079 smp_store_cpu_info(0); /* Final full version of the data */
1080 printk("CPU%d: ", 0);
1081 print_cpu_info(&cpu_data[0]);
1083 #if 0
1084 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1085 boot_cpu_logical_apicid = logical_smp_processor_id();
1086 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1087 #else
1088 // boot_cpu_physical_apicid = 0;
1089 // boot_cpu_logical_apicid = 0;
1090 x86_cpu_to_apicid[0] = 0;
1091 #endif
1093 current_thread_info()->cpu = 0;
1094 smp_tune_scheduling();
1095 cpus_clear(cpu_sibling_map[0]);
1096 cpu_set(0, cpu_sibling_map[0]);
1098 cpus_clear(cpu_core_map[0]);
1099 cpu_set(0, cpu_core_map[0]);
1101 #ifdef CONFIG_X86_IO_APIC
1102 /*
1103 * If we couldn't find an SMP configuration at boot time,
1104 * get out of here now!
1105 */
1106 if (!smp_found_config && !acpi_lapic) {
1107 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1108 smpboot_clear_io_apic_irqs();
1109 #if 0
1110 phys_cpu_present_map = physid_mask_of_physid(0);
1111 #endif
1112 #ifdef CONFIG_X86_LOCAL_APIC
1113 if (APIC_init_uniprocessor())
1114 printk(KERN_NOTICE "Local APIC not detected."
1115 " Using dummy APIC emulation.\n");
1116 #endif
1117 map_cpu_to_logical_apicid();
1118 cpu_set(0, cpu_sibling_map[0]);
1119 cpu_set(0, cpu_core_map[0]);
1120 return;
1122 #endif
1124 #if 0
1125 /*
1126 * Should not be necessary because the MP table should list the boot
1127 * CPU too, but we do it for the sake of robustness anyway.
1128 * Makes no sense to do this check in clustered apic mode, so skip it
1129 */
1130 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1131 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1132 boot_cpu_physical_apicid);
1133 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1136 /*
1137 * If we couldn't find a local APIC, then get out of here now!
1138 */
1139 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1140 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1141 boot_cpu_physical_apicid);
1142 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1143 smpboot_clear_io_apic_irqs();
1144 phys_cpu_present_map = physid_mask_of_physid(0);
1145 cpu_set(0, cpu_sibling_map[0]);
1146 cpu_set(0, cpu_core_map[0]);
1147 cpu_set(0, cpu_sibling_map[0]);
1148 cpu_set(0, cpu_core_map[0]);
1149 return;
1152 verify_local_APIC();
1153 #endif
1155 /*
1156 * If SMP should be disabled, then really disable it!
1157 */
1158 if (!max_cpus) {
1159 HYPERVISOR_shared_info->n_vcpu = 1;
1160 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1161 smpboot_clear_io_apic_irqs();
1162 #if 0
1163 phys_cpu_present_map = physid_mask_of_physid(0);
1164 #endif
1165 return;
1168 smp_intr_init();
1170 #if 0
1171 connect_bsp_APIC();
1172 setup_local_APIC();
1173 #endif
1174 map_cpu_to_logical_apicid();
1175 #if 0
1178 setup_portio_remap();
1180 /*
1181 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1183 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1184 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1185 * clustered apic ID.
1186 */
1187 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1188 #endif
1189 Dprintk("CPU present map: %lx\n",
1190 (1UL << HYPERVISOR_shared_info->n_vcpu) - 1);
1192 kicked = 1;
1193 for (cpu = 1; kicked < NR_CPUS &&
1194 cpu < HYPERVISOR_shared_info->n_vcpu; cpu++) {
1195 if (max_cpus <= cpucount+1)
1196 continue;
1198 #ifdef CONFIG_SMP_ALTERNATIVES
1199 if (kicked == 1)
1200 prepare_for_smp();
1201 #endif
1202 if (do_boot_cpu(cpu))
1203 printk("CPU #%d not responding - cannot use it.\n",
1204 cpu);
1205 else
1206 ++kicked;
1209 #if 0
1210 /*
1211 * Cleanup possible dangling ends...
1212 */
1213 smpboot_restore_warm_reset_vector();
1214 #endif
1216 /*
1217 * Allow the user to impress friends.
1218 */
1219 Dprintk("Before bogomips.\n");
1220 for (cpu = 0; cpu < NR_CPUS; cpu++)
1221 if (cpu_isset(cpu, cpu_callout_map))
1222 bogosum += cpu_data[cpu].loops_per_jiffy;
1223 printk(KERN_INFO
1224 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1225 cpucount+1,
1226 bogosum/(500000/HZ),
1227 (bogosum/(5000/HZ))%100);
1229 Dprintk("Before bogocount - setting activated=1.\n");
1231 if (smp_b_stepping)
1232 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1234 /*
1235 * Don't taint if we are running SMP kernel on a single non-MP
1236 * approved Athlon
1237 */
1238 if (tainted & TAINT_UNSAFE_SMP) {
1239 if (cpucount)
1240 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1241 else
1242 tainted &= ~TAINT_UNSAFE_SMP;
1245 Dprintk("Boot done.\n");
1247 /*
1248 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1249 * efficiently.
1250 */
1251 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1252 cpus_clear(cpu_sibling_map[cpu]);
1253 cpus_clear(cpu_core_map[cpu]);
1256 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1257 struct cpuinfo_x86 *c = cpu_data + cpu;
1258 int siblings = 0;
1259 int i;
1260 if (!cpu_isset(cpu, cpu_callout_map))
1261 continue;
1263 if (smp_num_siblings > 1) {
1264 for (i = 0; i < NR_CPUS; i++) {
1265 if (!cpu_isset(i, cpu_callout_map))
1266 continue;
1267 if (cpu_core_id[cpu] == cpu_core_id[i]) {
1268 siblings++;
1269 cpu_set(i, cpu_sibling_map[cpu]);
1272 } else {
1273 siblings++;
1274 cpu_set(cpu, cpu_sibling_map[cpu]);
1277 if (siblings != smp_num_siblings) {
1278 printk(KERN_WARNING "WARNING: %d siblings found for CPU%d, should be %d\n", siblings, cpu, smp_num_siblings);
1279 smp_num_siblings = siblings;
1281 if (c->x86_num_cores > 1) {
1282 for (i = 0; i < NR_CPUS; i++) {
1283 if (!cpu_isset(i, cpu_callout_map))
1284 continue;
1285 if (phys_proc_id[cpu] == phys_proc_id[i]) {
1286 cpu_set(i, cpu_core_map[cpu]);
1289 } else {
1290 cpu_core_map[cpu] = cpu_sibling_map[cpu];
1294 smpboot_setup_io_apic();
1296 #if 0
1297 setup_boot_APIC_clock();
1299 /*
1300 * Synchronize the TSC with the AP
1301 */
1302 if (cpu_has_tsc && cpucount && cpu_khz)
1303 synchronize_tsc_bp();
1304 #endif
1307 /* These are wrappers to interface to the new boot process. Someone
1308 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1309 void __init smp_prepare_cpus(unsigned int max_cpus)
1311 smp_commenced_mask = cpumask_of_cpu(0);
1312 cpu_callin_map = cpumask_of_cpu(0);
1313 mb();
1314 smp_boot_cpus(max_cpus);
1317 void __devinit smp_prepare_boot_cpu(void)
1319 cpu_set(smp_processor_id(), cpu_online_map);
1320 cpu_set(smp_processor_id(), cpu_callout_map);
1323 #ifdef CONFIG_HOTPLUG_CPU
1324 #include <asm-xen/ctrl_if.h>
1326 /* hotplug down/up funtion pointer and target vcpu */
1327 struct vcpu_hotplug_handler_t {
1328 void (*fn)(int vcpu);
1329 u32 vcpu;
1330 };
1331 static struct vcpu_hotplug_handler_t vcpu_hotplug_handler;
1333 /* must be called with the cpucontrol mutex held */
1334 static int __devinit cpu_enable(unsigned int cpu)
1336 #ifdef CONFIG_SMP_ALTERNATIVES
1337 if (num_online_cpus() == 1)
1338 prepare_for_smp();
1339 #endif
1341 /* get the target out of its holding state */
1342 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1343 wmb();
1345 /* wait for the processor to ack it. timeout? */
1346 while (!cpu_online(cpu))
1347 cpu_relax();
1349 fixup_irqs(cpu_online_map);
1351 /* counter the disable in fixup_irqs() */
1352 local_irq_enable();
1353 return 0;
1356 int __cpu_disable(void)
1358 cpumask_t map = cpu_online_map;
1359 int cpu = smp_processor_id();
1361 /*
1362 * Perhaps use cpufreq to drop frequency, but that could go
1363 * into generic code.
1365 * We won't take down the boot processor on i386 due to some
1366 * interrupts only being able to be serviced by the BSP.
1367 * Especially so if we're not using an IOAPIC -zwane
1368 */
1369 if (cpu == 0)
1370 return -EBUSY;
1372 cpu_clear(cpu, map);
1373 fixup_irqs(map);
1375 /* It's now safe to remove this processor from the online map */
1376 cpu_clear(cpu, cpu_online_map);
1378 #ifdef CONFIG_SMP_ALTERNATIVES
1379 if (num_online_cpus() == 1)
1380 unprepare_for_smp();
1381 #endif
1383 return 0;
1386 void __cpu_die(unsigned int cpu)
1388 /* We don't do anything here: idle task is faking death itself. */
1389 unsigned int i;
1391 for (i = 0; i < 10; i++) {
1392 /* They ack this in play_dead by setting CPU_DEAD */
1393 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
1394 return;
1395 current->state = TASK_UNINTERRUPTIBLE;
1396 schedule_timeout(HZ/10);
1398 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1401 static int vcpu_hotplug_cpu_process(void *unused)
1403 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1405 if (handler->fn) {
1406 (*(handler->fn))(handler->vcpu);
1407 handler->fn = NULL;
1409 return 0;
1412 static void __vcpu_hotplug_handler(void *unused)
1414 int err;
1416 err = kernel_thread(vcpu_hotplug_cpu_process,
1417 NULL, CLONE_FS | CLONE_FILES);
1418 if (err < 0)
1419 printk(KERN_ALERT "Error creating hotplug_cpu process!\n");
1423 static void vcpu_hotplug_event_handler(ctrl_msg_t *msg, unsigned long id)
1425 static DECLARE_WORK(vcpu_hotplug_work, __vcpu_hotplug_handler, NULL);
1426 vcpu_hotplug_t *req = (vcpu_hotplug_t *)&msg->msg[0];
1427 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1428 ssize_t ret;
1430 if (msg->length != sizeof(vcpu_hotplug_t))
1431 goto parse_error;
1433 /* grab target vcpu from msg */
1434 handler->vcpu = req->vcpu;
1436 /* determine which function to call based on msg subtype */
1437 switch (msg->subtype) {
1438 case CMSG_VCPU_HOTPLUG_OFF:
1439 handler->fn = (void *)&cpu_down;
1440 ret = schedule_work(&vcpu_hotplug_work);
1441 req->status = (u32) ret;
1442 break;
1443 case CMSG_VCPU_HOTPLUG_ON:
1444 handler->fn = (void *)&cpu_up;
1445 ret = schedule_work(&vcpu_hotplug_work);
1446 req->status = (u32) ret;
1447 break;
1448 default:
1449 goto parse_error;
1452 ctrl_if_send_response(msg);
1453 return;
1454 parse_error:
1455 msg->length = 0;
1456 ctrl_if_send_response(msg);
1459 static int __init setup_vcpu_hotplug_event(void)
1461 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1463 handler->fn = NULL;
1464 ctrl_if_register_receiver(CMSG_VCPU_HOTPLUG,
1465 vcpu_hotplug_event_handler, 0);
1467 return 0;
1470 __initcall(setup_vcpu_hotplug_event);
1472 #else /* ... !CONFIG_HOTPLUG_CPU */
1473 int __cpu_disable(void)
1475 return -ENOSYS;
1478 void __cpu_die(unsigned int cpu)
1480 /* We said "no" in __cpu_disable */
1481 BUG();
1483 #endif /* CONFIG_HOTPLUG_CPU */
1485 int __devinit __cpu_up(unsigned int cpu)
1487 /* In case one didn't come up */
1488 if (!cpu_isset(cpu, cpu_callin_map)) {
1489 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1490 local_irq_enable();
1491 return -EIO;
1494 #ifdef CONFIG_HOTPLUG_CPU
1495 #ifdef CONFIG_XEN
1496 /* Tell hypervisor to bring vcpu up. */
1497 HYPERVISOR_vcpu_up(cpu);
1498 #endif
1499 /* Already up, and in cpu_quiescent now? */
1500 if (cpu_isset(cpu, smp_commenced_mask)) {
1501 cpu_enable(cpu);
1502 return 0;
1504 #endif
1506 local_irq_enable();
1507 /* Unleash the CPU! */
1508 cpu_set(cpu, smp_commenced_mask);
1509 while (!cpu_isset(cpu, cpu_online_map))
1510 mb();
1511 return 0;
1514 void __init smp_cpus_done(unsigned int max_cpus)
1516 #if 1
1517 #else
1518 #ifdef CONFIG_X86_IO_APIC
1519 setup_ioapic_dest();
1520 #endif
1521 zap_low_mappings();
1522 /*
1523 * Disable executability of the SMP trampoline:
1524 */
1525 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1526 #endif
1529 extern irqreturn_t smp_reschedule_interrupt(int, void *, struct pt_regs *);
1530 extern irqreturn_t smp_call_function_interrupt(int, void *, struct pt_regs *);
1532 void smp_intr_init(void)
1534 int cpu = smp_processor_id();
1536 per_cpu(resched_irq, cpu) =
1537 bind_ipi_on_cpu_to_irq(RESCHEDULE_VECTOR);
1538 sprintf(resched_name[cpu], "resched%d", cpu);
1539 BUG_ON(request_irq(per_cpu(resched_irq, cpu), smp_reschedule_interrupt,
1540 SA_INTERRUPT, resched_name[cpu], NULL));
1542 per_cpu(callfunc_irq, cpu) =
1543 bind_ipi_on_cpu_to_irq(CALL_FUNCTION_VECTOR);
1544 sprintf(callfunc_name[cpu], "callfunc%d", cpu);
1545 BUG_ON(request_irq(per_cpu(callfunc_irq, cpu),
1546 smp_call_function_interrupt,
1547 SA_INTERRUPT, callfunc_name[cpu], NULL));
1550 static void smp_intr_exit(void)
1552 int cpu = smp_processor_id();
1554 free_irq(per_cpu(resched_irq, cpu), NULL);
1555 unbind_ipi_from_irq(RESCHEDULE_VECTOR);
1557 free_irq(per_cpu(callfunc_irq, cpu), NULL);
1558 unbind_ipi_from_irq(CALL_FUNCTION_VECTOR);
1561 void smp_suspend(void)
1563 /* XXX todo: take down time and ipi's on all cpus */
1564 local_teardown_timer_irq();
1565 smp_intr_exit();
1568 void smp_resume(void)
1570 /* XXX todo: restore time and ipi's on all cpus */
1571 smp_intr_init();
1572 local_setup_timer_irq();