ia64/xen-unstable

view xen/arch/ia64/vmx/vmx_minstate.h @ 16749:54ed70d1dd11

[IA64] vti fault handler clean up: vmx_minstate.h white space

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Fri Dec 14 13:04:27 2007 -0700 (2007-12-14)
parents c7e16caf4e63
children d0f0ed665d1a
line source
1 /*
2 * vmx_minstate.h:
3 * Copyright (c) 2005, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
19 */
21 #include <linux/config.h>
23 #include <asm/asmmacro.h>
24 #include <asm/fpu.h>
25 #include <asm/mmu_context.h>
26 #include <asm/offsets.h>
27 #include <asm/pal.h>
28 #include <asm/pgtable.h>
29 #include <asm/processor.h>
30 #include <asm/ptrace.h>
31 #include <asm/system.h>
32 #include <asm/vmx_pal_vsa.h>
33 #include <asm/vmx_vpd.h>
34 #include <asm/cache.h>
35 #include "entry.h"
37 #define VMX_MINSTATE_START_SAVE_MIN \
38 mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
39 ;; \
40 mov.m r28=ar.rnat; \
41 addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
42 ;; \
43 lfetch.fault.excl.nt1 [r22]; \
44 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
45 mov r23=ar.bspstore; /* save ar.bspstore */ \
46 ;; \
47 mov ar.bspstore=r22; /* switch to kernel RBS */ \
48 ;; \
49 mov r18=ar.bsp; \
50 mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
52 #define VMX_MINSTATE_END_SAVE_MIN \
53 bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
54 ;;
56 #define PAL_VSA_SYNC_READ \
57 /* begin to call pal vps sync_read */ \
58 add r25=IA64_VPD_BASE_OFFSET, r21; \
59 movl r20=__vsa_base; \
60 ;; \
61 ld8 r25=[r25]; /* read vpd base */ \
62 ld8 r20=[r20]; /* read entry point */ \
63 ;; \
64 add r20=PAL_VPS_SYNC_READ,r20; \
65 ;; \
66 { .mii; \
67 nop 0x0; \
68 mov r24=ip; \
69 mov b0=r20; \
70 ;; \
71 }; \
72 { .mmb; \
73 add r24 = 0x20, r24; \
74 nop 0x0; \
75 br.cond.sptk b0; /* call the service */ \
76 ;; \
77 };
79 #define IA64_CURRENT_REG IA64_KR(CURRENT) /* r21 is reserved for current pointer */
80 //#define VMX_MINSTATE_GET_CURRENT(reg) mov reg=IA64_CURRENT_REG
81 #define VMX_MINSTATE_GET_CURRENT(reg) mov reg=r21
83 /*
84 * VMX_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
85 * the minimum state necessary that allows us to turn psr.ic back
86 * on.
87 *
88 * Assumed state upon entry:
89 * psr.ic: off
90 * r31: contains saved predicates (pr)
91 *
92 * Upon exit, the state is as follows:
93 * psr.ic: off
94 * r2 = points to &pt_regs.r16
95 * r8 = contents of ar.ccv
96 * r9 = contents of ar.csd
97 * r10 = contents of ar.ssd
98 * r11 = FPSR_DEFAULT
99 * r12 = kernel sp (kernel virtual address)
100 * r13 = points to current task_struct (kernel virtual address)
101 * p15 = TRUE if psr.i is set in cr.ipsr
102 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
103 * preserved
104 *
105 * Note that psr.ic is NOT turned on by this macro. This is so that
106 * we can pass interruption state as arguments to a handler.
107 */
109 #define VMX_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
110 VMX_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
111 mov r27=ar.rsc; /* M */ \
112 mov r20=r1; /* A */ \
113 mov r25=ar.unat; /* M */ \
114 mov r29=cr.ipsr; /* M */ \
115 mov r26=ar.pfs; /* I */ \
116 mov r18=cr.isr; \
117 COVER; /* B;; (or nothing) */ \
118 ;; \
119 tbit.z p6,p0=r29,IA64_PSR_VM_BIT; \
120 ;; \
121 tbit.nz.or p6,p0 = r18,IA64_ISR_NI_BIT; \
122 ;; \
123 (p6)br.spnt.few vmx_panic; \
124 tbit.z p0,p15=r29,IA64_PSR_I_BIT; \
125 mov r1=r16; \
126 /* mov r21=r16; */ \
127 /* switch from user to kernel RBS: */ \
128 ;; \
129 invala; /* M */ \
130 SAVE_IFS; \
131 ;; \
132 VMX_MINSTATE_START_SAVE_MIN \
133 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
134 adds r16=PT(CR_IPSR),r1; \
135 ;; \
136 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
137 st8 [r16]=r29; /* save cr.ipsr */ \
138 ;; \
139 lfetch.fault.excl.nt1 [r17]; \
140 tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \
141 mov r29=b0 \
142 ;; \
143 adds r16=PT(R8),r1; /* initialize first base pointer */ \
144 adds r17=PT(R9),r1; /* initialize second base pointer */ \
145 ;; \
146 .mem.offset 0,0; st8.spill [r16]=r8,16; \
147 .mem.offset 8,0; st8.spill [r17]=r9,16; \
148 ;; \
149 .mem.offset 0,0; st8.spill [r16]=r10,24; \
150 .mem.offset 8,0; st8.spill [r17]=r11,24; \
151 ;; \
152 mov r9=cr.iip; /* M */ \
153 mov r10=ar.fpsr; /* M */ \
154 ;; \
155 st8 [r16]=r9,16; /* save cr.iip */ \
156 st8 [r17]=r30,16; /* save cr.ifs */ \
157 sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
158 ;; \
159 st8 [r16]=r25,16; /* save ar.unat */ \
160 st8 [r17]=r26,16; /* save ar.pfs */ \
161 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
162 ;; \
163 st8 [r16]=r27,16; /* save ar.rsc */ \
164 st8 [r17]=r28,16; /* save ar.rnat */ \
165 ;; /* avoid RAW on r16 & r17 */ \
166 st8 [r16]=r23,16; /* save ar.bspstore */ \
167 st8 [r17]=r31,16; /* save predicates */ \
168 ;; \
169 st8 [r16]=r29,16; /* save b0 */ \
170 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
171 cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \
172 ;; \
173 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
174 .mem.offset 8,0; st8.spill [r17]=r12,16; \
175 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
176 ;; \
177 .mem.offset 0,0; st8.spill [r16]=r13,16; \
178 .mem.offset 8,0; st8.spill [r17]=r10,16; /* save ar.fpsr */ \
179 mov r13=r21; /* establish `current' */ \
180 ;; \
181 .mem.offset 0,0; st8.spill [r16]=r15,16; \
182 .mem.offset 8,0; st8.spill [r17]=r14,16; \
183 ;; \
184 .mem.offset 0,0; st8.spill [r16]=r2,16; \
185 .mem.offset 8,0; st8.spill [r17]=r3,16; \
186 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
187 ;; \
188 adds r16=IA64_VCPU_IIPA_OFFSET,r13; \
189 adds r17=IA64_VCPU_ISR_OFFSET,r13; \
190 mov r26=cr.iipa; \
191 mov r27=cr.isr; \
192 ;; \
193 st8 [r16]=r26; \
194 st8 [r17]=r27; \
195 ;; \
196 EXTRA; \
197 mov r8=ar.ccv; \
198 mov r9=ar.csd; \
199 mov r10=ar.ssd; \
200 movl r11=FPSR_DEFAULT; /* L-unit */ \
201 movl r1=__gp; /* establish kernel global pointer */ \
202 ;; \
203 PAL_VSA_SYNC_READ \
204 VMX_MINSTATE_END_SAVE_MIN
206 /*
207 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
208 *
209 * Assumed state upon entry:
210 * psr.ic: on
211 * r2: points to &pt_regs.f6
212 * r3: points to &pt_regs.f7
213 * r8: contents of ar.ccv
214 * r9: contents of ar.csd
215 * r10: contents of ar.ssd
216 * r11: FPSR_DEFAULT
217 *
218 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
219 */
220 #define VMX_SAVE_REST \
221 .mem.offset 0,0; st8.spill [r2]=r16,16; \
222 .mem.offset 8,0; st8.spill [r3]=r17,16; \
223 ;; \
224 .mem.offset 0,0; st8.spill [r2]=r18,16; \
225 .mem.offset 8,0; st8.spill [r3]=r19,16; \
226 ;; \
227 .mem.offset 0,0; st8.spill [r2]=r20,16; \
228 .mem.offset 8,0; st8.spill [r3]=r21,16; \
229 mov r18=b6; \
230 ;; \
231 .mem.offset 0,0; st8.spill [r2]=r22,16; \
232 .mem.offset 8,0; st8.spill [r3]=r23,16; \
233 mov r19=b7; \
234 ;; \
235 .mem.offset 0,0; st8.spill [r2]=r24,16; \
236 .mem.offset 8,0; st8.spill [r3]=r25,16; \
237 ;; \
238 .mem.offset 0,0; st8.spill [r2]=r26,16; \
239 .mem.offset 8,0; st8.spill [r3]=r27,16; \
240 ;; \
241 .mem.offset 0,0; st8.spill [r2]=r28,16; \
242 .mem.offset 8,0; st8.spill [r3]=r29,16; \
243 ;; \
244 .mem.offset 0,0; st8.spill [r2]=r30,16; \
245 .mem.offset 8,0; st8.spill [r3]=r31,32; \
246 ;; \
247 mov ar.fpsr=r11; \
248 st8 [r2]=r8,8; \
249 adds r24=PT(B6)-PT(F7),r3; \
250 ;; \
251 stf.spill [r2]=f6,32; \
252 stf.spill [r3]=f7,32; \
253 ;; \
254 stf.spill [r2]=f8,32; \
255 stf.spill [r3]=f9,32; \
256 ;; \
257 stf.spill [r2]=f10,32; \
258 stf.spill [r3]=f11; \
259 adds r25=PT(B7)-PT(F11),r3; \
260 ;; \
261 st8 [r24]=r18,16; /* b6 */ \
262 st8 [r25]=r19,16; /* b7 */ \
263 adds r3=PT(R5)-PT(F11),r3; \
264 ;; \
265 st8 [r24]=r9; /* ar.csd */ \
266 st8 [r25]=r10; /* ar.ssd */ \
267 ;; \
268 mov r18=ar.unat; \
269 adds r19=PT(EML_UNAT)-PT(R4),r2; \
270 ;; \
271 st8 [r19]=r18; /* eml_unat */
273 #define VMX_SAVE_EXTRA \
274 .mem.offset 0,0; st8.spill [r2]=r4,16; \
275 .mem.offset 8,0; st8.spill [r3]=r5,16; \
276 ;; \
277 .mem.offset 0,0; st8.spill [r2]=r6,16; \
278 .mem.offset 8,0; st8.spill [r3]=r7; \
279 ;; \
280 mov r26=ar.unat; \
281 ;; \
282 st8 [r2]=r26; /* eml_unat */
284 #define VMX_SAVE_MIN_WITH_COVER VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,)
285 #define VMX_SAVE_MIN_WITH_COVER_R19 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19)
286 #define VMX_SAVE_MIN VMX_DO_SAVE_MIN( , mov r30=r0, )
288 /*
289 * Local variables:
290 * mode: C
291 * c-set-style: "BSD"
292 * c-basic-offset: 4
293 * tab-width: 4
294 * indent-tabs-mode: nil
295 * End:
296 */