ia64/xen-unstable

view xen/arch/ia64/linux-xen/unaligned.c @ 10888:5379548bfc79

[NET] Enable TCPv4 segmentation offload in front/back drivers.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Tue Aug 01 11:54:45 2006 +0100 (2006-08-01)
parents cd1df13fb1c4
children 997bd5fcf307
line source
1 /*
2 * Architecture-specific unaligned trap handling.
3 *
4 * Copyright (C) 1999-2002, 2004 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 2002/12/09 Fix rotating register handling (off-by-1 error, missing fr-rotation). Fix
9 * get_rse_reg() to not leak kernel bits to user-level (reading an out-of-frame
10 * stacked register returns an undefined value; it does NOT trigger a
11 * "rsvd register fault").
12 * 2001/10/11 Fix unaligned access to rotating registers in s/w pipelined loops.
13 * 2001/08/13 Correct size of extended floats (float_fsz) from 16 to 10 bytes.
14 * 2001/01/17 Add support emulation of unaligned kernel accesses.
15 */
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/smp_lock.h>
19 #include <linux/tty.h>
21 #include <asm/intrinsics.h>
22 #include <asm/processor.h>
23 #include <asm/rse.h>
24 #include <asm/uaccess.h>
25 #include <asm/unaligned.h>
27 extern void die_if_kernel(char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
29 #undef DEBUG_UNALIGNED_TRAP
31 #ifdef DEBUG_UNALIGNED_TRAP
32 # define DPRINT(a...) do { printk("%s %u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
33 # define DDUMP(str,vp,len) dump(str, vp, len)
35 static void
36 dump (const char *str, void *vp, size_t len)
37 {
38 unsigned char *cp = vp;
39 int i;
41 printk("%s", str);
42 for (i = 0; i < len; ++i)
43 printk (" %02x", *cp++);
44 printk("\n");
45 }
46 #else
47 # define DPRINT(a...)
48 # define DDUMP(str,vp,len)
49 #endif
51 #define IA64_FIRST_STACKED_GR 32
52 #define IA64_FIRST_ROTATING_FR 32
53 #define SIGN_EXT9 0xffffffffffffff00ul
55 /*
56 * For M-unit:
57 *
58 * opcode | m | x6 |
59 * --------|------|---------|
60 * [40-37] | [36] | [35:30] |
61 * --------|------|---------|
62 * 4 | 1 | 6 | = 11 bits
63 * --------------------------
64 * However bits [31:30] are not directly useful to distinguish between
65 * load/store so we can use [35:32] instead, which gives the following
66 * mask ([40:32]) using 9 bits. The 'e' comes from the fact that we defer
67 * checking the m-bit until later in the load/store emulation.
68 */
69 #define IA64_OPCODE_MASK 0x1ef
70 #define IA64_OPCODE_SHIFT 32
72 /*
73 * Table C-28 Integer Load/Store
74 *
75 * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
76 *
77 * ld8.fill, st8.fill MUST be aligned because the RNATs are based on
78 * the address (bits [8:3]), so we must failed.
79 */
80 #define LD_OP 0x080
81 #define LDS_OP 0x081
82 #define LDA_OP 0x082
83 #define LDSA_OP 0x083
84 #define LDBIAS_OP 0x084
85 #define LDACQ_OP 0x085
86 /* 0x086, 0x087 are not relevant */
87 #define LDCCLR_OP 0x088
88 #define LDCNC_OP 0x089
89 #define LDCCLRACQ_OP 0x08a
90 #define ST_OP 0x08c
91 #define STREL_OP 0x08d
92 /* 0x08e,0x8f are not relevant */
94 /*
95 * Table C-29 Integer Load +Reg
96 *
97 * we use the ld->m (bit [36:36]) field to determine whether or not we have
98 * a load/store of this form.
99 */
101 /*
102 * Table C-30 Integer Load/Store +Imm
103 *
104 * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
105 *
106 * ld8.fill, st8.fill must be aligned because the Nat register are based on
107 * the address, so we must fail and the program must be fixed.
108 */
109 #define LD_IMM_OP 0x0a0
110 #define LDS_IMM_OP 0x0a1
111 #define LDA_IMM_OP 0x0a2
112 #define LDSA_IMM_OP 0x0a3
113 #define LDBIAS_IMM_OP 0x0a4
114 #define LDACQ_IMM_OP 0x0a5
115 /* 0x0a6, 0xa7 are not relevant */
116 #define LDCCLR_IMM_OP 0x0a8
117 #define LDCNC_IMM_OP 0x0a9
118 #define LDCCLRACQ_IMM_OP 0x0aa
119 #define ST_IMM_OP 0x0ac
120 #define STREL_IMM_OP 0x0ad
121 /* 0x0ae,0xaf are not relevant */
123 /*
124 * Table C-32 Floating-point Load/Store
125 */
126 #define LDF_OP 0x0c0
127 #define LDFS_OP 0x0c1
128 #define LDFA_OP 0x0c2
129 #define LDFSA_OP 0x0c3
130 /* 0x0c6 is irrelevant */
131 #define LDFCCLR_OP 0x0c8
132 #define LDFCNC_OP 0x0c9
133 /* 0x0cb is irrelevant */
134 #define STF_OP 0x0cc
136 /*
137 * Table C-33 Floating-point Load +Reg
138 *
139 * we use the ld->m (bit [36:36]) field to determine whether or not we have
140 * a load/store of this form.
141 */
143 /*
144 * Table C-34 Floating-point Load/Store +Imm
145 */
146 #define LDF_IMM_OP 0x0e0
147 #define LDFS_IMM_OP 0x0e1
148 #define LDFA_IMM_OP 0x0e2
149 #define LDFSA_IMM_OP 0x0e3
150 /* 0x0e6 is irrelevant */
151 #define LDFCCLR_IMM_OP 0x0e8
152 #define LDFCNC_IMM_OP 0x0e9
153 #define STF_IMM_OP 0x0ec
155 typedef struct {
156 unsigned long qp:6; /* [0:5] */
157 unsigned long r1:7; /* [6:12] */
158 unsigned long imm:7; /* [13:19] */
159 unsigned long r3:7; /* [20:26] */
160 unsigned long x:1; /* [27:27] */
161 unsigned long hint:2; /* [28:29] */
162 unsigned long x6_sz:2; /* [30:31] */
163 unsigned long x6_op:4; /* [32:35], x6 = x6_sz|x6_op */
164 unsigned long m:1; /* [36:36] */
165 unsigned long op:4; /* [37:40] */
166 unsigned long pad:23; /* [41:63] */
167 } load_store_t;
170 typedef enum {
171 UPD_IMMEDIATE, /* ldXZ r1=[r3],imm(9) */
172 UPD_REG /* ldXZ r1=[r3],r2 */
173 } update_t;
175 /*
176 * We use tables to keep track of the offsets of registers in the saved state.
177 * This way we save having big switch/case statements.
178 *
179 * We use bit 0 to indicate switch_stack or pt_regs.
180 * The offset is simply shifted by 1 bit.
181 * A 2-byte value should be enough to hold any kind of offset
182 *
183 * In case the calling convention changes (and thus pt_regs/switch_stack)
184 * simply use RSW instead of RPT or vice-versa.
185 */
187 #define RPO(x) ((size_t) &((struct pt_regs *)0)->x)
188 #define RSO(x) ((size_t) &((struct switch_stack *)0)->x)
190 #define RPT(x) (RPO(x) << 1)
191 #define RSW(x) (1| RSO(x)<<1)
193 #define GR_OFFS(x) (gr_info[x]>>1)
194 #define GR_IN_SW(x) (gr_info[x] & 0x1)
196 #define FR_OFFS(x) (fr_info[x]>>1)
197 #define FR_IN_SW(x) (fr_info[x] & 0x1)
199 static u16 gr_info[32]={
200 0, /* r0 is read-only : WE SHOULD NEVER GET THIS */
202 RPT(r1), RPT(r2), RPT(r3),
204 #if defined(XEN)
205 RPT(r4), RPT(r5), RPT(r6), RPT(r7),
206 #else
207 RSW(r4), RSW(r5), RSW(r6), RSW(r7),
208 #endif
210 RPT(r8), RPT(r9), RPT(r10), RPT(r11),
211 RPT(r12), RPT(r13), RPT(r14), RPT(r15),
213 RPT(r16), RPT(r17), RPT(r18), RPT(r19),
214 RPT(r20), RPT(r21), RPT(r22), RPT(r23),
215 RPT(r24), RPT(r25), RPT(r26), RPT(r27),
216 RPT(r28), RPT(r29), RPT(r30), RPT(r31)
217 };
219 #ifndef XEN
220 static u16 fr_info[32]={
221 0, /* constant : WE SHOULD NEVER GET THIS */
222 0, /* constant : WE SHOULD NEVER GET THIS */
224 RSW(f2), RSW(f3), RSW(f4), RSW(f5),
226 RPT(f6), RPT(f7), RPT(f8), RPT(f9),
227 RPT(f10), RPT(f11),
229 RSW(f12), RSW(f13), RSW(f14),
230 RSW(f15), RSW(f16), RSW(f17), RSW(f18), RSW(f19),
231 RSW(f20), RSW(f21), RSW(f22), RSW(f23), RSW(f24),
232 RSW(f25), RSW(f26), RSW(f27), RSW(f28), RSW(f29),
233 RSW(f30), RSW(f31)
234 };
236 /* Invalidate ALAT entry for integer register REGNO. */
237 static void
238 invala_gr (int regno)
239 {
240 # define F(reg) case reg: ia64_invala_gr(reg); break
242 switch (regno) {
243 F( 0); F( 1); F( 2); F( 3); F( 4); F( 5); F( 6); F( 7);
244 F( 8); F( 9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
245 F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
246 F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
247 F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
248 F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
249 F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
250 F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
251 F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
252 F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
253 F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
254 F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
255 F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
256 F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
257 F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
258 F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
259 }
260 # undef F
261 }
263 /* Invalidate ALAT entry for floating-point register REGNO. */
264 static void
265 invala_fr (int regno)
266 {
267 # define F(reg) case reg: ia64_invala_fr(reg); break
269 switch (regno) {
270 F( 0); F( 1); F( 2); F( 3); F( 4); F( 5); F( 6); F( 7);
271 F( 8); F( 9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
272 F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
273 F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
274 F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
275 F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
276 F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
277 F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
278 F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
279 F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
280 F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
281 F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
282 F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
283 F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
284 F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
285 F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
286 }
287 # undef F
288 }
289 #endif /* XEN */
291 static inline unsigned long
292 rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg)
293 {
294 reg += rrb;
295 if (reg >= sor)
296 reg -= sor;
297 return reg;
298 }
300 #if defined(XEN)
301 void
302 set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, unsigned long nat)
303 {
304 unsigned long *bsp, *bspstore, *addr, *rnat_addr;
305 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
306 unsigned long nat_mask;
307 unsigned long old_rsc,new_rsc;
308 unsigned long rnat;
309 long sof = (regs->cr_ifs) & 0x7f;
310 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
311 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
312 long ridx = r1 - 32;
314 if (ridx >= sof) {
315 /* this should never happen, as the "rsvd register fault" has higher priority */
316 DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
317 return;
318 }
320 if (ridx < sor)
321 ridx = rotate_reg(sor, rrb_gr, ridx);
323 old_rsc=ia64_get_rsc();
324 new_rsc=old_rsc&(~0x3);
325 ia64_set_rsc(new_rsc);
327 bspstore = (unsigned long*)ia64_get_bspstore();
328 bsp =kbs + (regs->loadrs >> 19);//16+3
330 addr = ia64_rse_skip_regs(bsp, -sof + ridx);
331 nat_mask = 1UL << ia64_rse_slot_num(addr);
332 rnat_addr = ia64_rse_rnat_addr(addr);
334 if(addr >= bspstore){
336 ia64_flushrs ();
337 ia64_mf ();
338 *addr = val;
339 bspstore = (unsigned long*)ia64_get_bspstore();
340 rnat = ia64_get_rnat ();
341 if(bspstore < rnat_addr){
342 rnat=rnat&(~nat_mask);
343 }else{
344 *rnat_addr = (*rnat_addr)&(~nat_mask);
345 }
346 ia64_mf();
347 ia64_loadrs();
348 ia64_set_rnat(rnat);
349 }else{
351 rnat = ia64_get_rnat ();
352 *addr = val;
353 if(bspstore < rnat_addr){
354 rnat=rnat&(~nat_mask);
355 }else{
356 *rnat_addr = (*rnat_addr)&(~nat_mask);
357 }
358 ia64_set_bspstore (bspstore);
359 ia64_set_rnat(rnat);
360 }
361 ia64_set_rsc(old_rsc);
362 }
365 static void
366 get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int*nat)
367 {
368 unsigned long *bsp, *addr, *rnat_addr, *bspstore;
369 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
370 unsigned long nat_mask;
371 unsigned long old_rsc, new_rsc;
372 long sof = (regs->cr_ifs) & 0x7f;
373 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
374 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
375 long ridx = r1 - 32;
377 if (ridx >= sof) {
378 /* read of out-of-frame register returns an undefined value; 0 in our case. */
379 DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
380 panic("wrong stack register number (iip=%lx)\n", regs->cr_iip);
381 }
383 if (ridx < sor)
384 ridx = rotate_reg(sor, rrb_gr, ridx);
386 old_rsc=ia64_get_rsc();
387 new_rsc=old_rsc&(~(0x3));
388 ia64_set_rsc(new_rsc);
390 bspstore = (unsigned long*)ia64_get_bspstore();
391 bsp =kbs + (regs->loadrs >> 19); //16+3;
393 addr = ia64_rse_skip_regs(bsp, -sof + ridx);
394 nat_mask = 1UL << ia64_rse_slot_num(addr);
395 rnat_addr = ia64_rse_rnat_addr(addr);
397 if(addr >= bspstore){
399 ia64_flushrs ();
400 ia64_mf ();
401 bspstore = (unsigned long*)ia64_get_bspstore();
402 }
403 *val=*addr;
404 if(nat){
405 if(bspstore < rnat_addr){
406 *nat=(int)!!(ia64_get_rnat()&nat_mask);
407 }else{
408 *nat = (int)!!((*rnat_addr)&nat_mask);
409 }
410 ia64_set_rsc(old_rsc);
411 }
412 }
414 #else
415 static void
416 set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat)
417 {
418 struct switch_stack *sw = (struct switch_stack *) regs - 1;
419 unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end;
420 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
421 unsigned long rnats, nat_mask;
422 unsigned long on_kbs;
423 long sof = (regs->cr_ifs) & 0x7f;
424 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
425 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
426 long ridx = r1 - 32;
428 if (ridx >= sof) {
429 /* this should never happen, as the "rsvd register fault" has higher priority */
430 DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
431 return;
432 }
434 if (ridx < sor)
435 ridx = rotate_reg(sor, rrb_gr, ridx);
437 DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
438 r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
440 on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
441 addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
442 if (addr >= kbs) {
443 /* the register is on the kernel backing store: easy... */
444 rnat_addr = ia64_rse_rnat_addr(addr);
445 if ((unsigned long) rnat_addr >= sw->ar_bspstore)
446 rnat_addr = &sw->ar_rnat;
447 nat_mask = 1UL << ia64_rse_slot_num(addr);
449 *addr = val;
450 if (nat)
451 *rnat_addr |= nat_mask;
452 else
453 *rnat_addr &= ~nat_mask;
454 return;
455 }
457 if (!user_stack(current, regs)) {
458 DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);
459 return;
460 }
462 bspstore = (unsigned long *)regs->ar_bspstore;
463 ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
464 bsp = ia64_rse_skip_regs(ubs_end, -sof);
465 addr = ia64_rse_skip_regs(bsp, ridx);
467 DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
469 ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
471 rnat_addr = ia64_rse_rnat_addr(addr);
473 ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
474 DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",
475 (void *) rnat_addr, rnats, nat, (rnats >> ia64_rse_slot_num(addr)) & 1);
477 nat_mask = 1UL << ia64_rse_slot_num(addr);
478 if (nat)
479 rnats |= nat_mask;
480 else
481 rnats &= ~nat_mask;
482 ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, rnats);
484 DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats);
485 }
488 static void
489 get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat)
490 {
491 struct switch_stack *sw = (struct switch_stack *) regs - 1;
492 unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore;
493 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
494 unsigned long rnats, nat_mask;
495 unsigned long on_kbs;
496 long sof = (regs->cr_ifs) & 0x7f;
497 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
498 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
499 long ridx = r1 - 32;
501 if (ridx >= sof) {
502 /* read of out-of-frame register returns an undefined value; 0 in our case. */
503 DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
504 goto fail;
505 }
507 if (ridx < sor)
508 ridx = rotate_reg(sor, rrb_gr, ridx);
510 DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
511 r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
513 on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
514 addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
515 if (addr >= kbs) {
516 /* the register is on the kernel backing store: easy... */
517 *val = *addr;
518 if (nat) {
519 rnat_addr = ia64_rse_rnat_addr(addr);
520 if ((unsigned long) rnat_addr >= sw->ar_bspstore)
521 rnat_addr = &sw->ar_rnat;
522 nat_mask = 1UL << ia64_rse_slot_num(addr);
523 *nat = (*rnat_addr & nat_mask) != 0;
524 }
525 return;
526 }
528 if (!user_stack(current, regs)) {
529 DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1);
530 goto fail;
531 }
533 bspstore = (unsigned long *)regs->ar_bspstore;
534 ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
535 bsp = ia64_rse_skip_regs(ubs_end, -sof);
536 addr = ia64_rse_skip_regs(bsp, ridx);
538 DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
540 ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
542 if (nat) {
543 rnat_addr = ia64_rse_rnat_addr(addr);
544 nat_mask = 1UL << ia64_rse_slot_num(addr);
546 DPRINT("rnat @%p = 0x%lx\n", (void *) rnat_addr, rnats);
548 ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
549 *nat = (rnats & nat_mask) != 0;
550 }
551 return;
553 fail:
554 *val = 0;
555 if (nat)
556 *nat = 0;
557 return;
558 }
559 #endif
562 #ifdef XEN
563 void
564 #else
565 static void
566 #endif
567 setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs)
568 {
569 struct switch_stack *sw = (struct switch_stack *) regs - 1;
570 unsigned long addr;
571 unsigned long bitmask;
572 unsigned long *unat;
574 /*
575 * First takes care of stacked registers
576 */
577 if (regnum >= IA64_FIRST_STACKED_GR) {
578 set_rse_reg(regs, regnum, val, nat);
579 return;
580 }
582 /*
583 * Using r0 as a target raises a General Exception fault which has higher priority
584 * than the Unaligned Reference fault.
585 */
587 /*
588 * Now look at registers in [0-31] range and init correct UNAT
589 */
590 if (GR_IN_SW(regnum)) {
591 addr = (unsigned long)sw;
592 unat = &sw->ar_unat;
593 } else {
594 addr = (unsigned long)regs;
595 #if defined(XEN)
596 unat = &regs->eml_unat;
597 #else
598 unat = &sw->caller_unat;
599 #endif
600 }
601 DPRINT("tmp_base=%lx switch_stack=%s offset=%d\n",
602 addr, unat==&sw->ar_unat ? "yes":"no", GR_OFFS(regnum));
603 /*
604 * add offset from base of struct
605 * and do it !
606 */
607 addr += GR_OFFS(regnum);
609 *(unsigned long *)addr = val;
611 /*
612 * We need to clear the corresponding UNAT bit to fully emulate the load
613 * UNAT bit_pos = GR[r3]{8:3} form EAS-2.4
614 */
615 bitmask = 1UL << (addr >> 3 & 0x3f);
616 DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat);
617 if (nat) {
618 *unat |= bitmask;
619 } else {
620 *unat &= ~bitmask;
621 }
622 DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat);
623 }
625 /*
626 * Return the (rotated) index for floating point register REGNUM (REGNUM must be in the
627 * range from 32-127, result is in the range from 0-95.
628 */
629 static inline unsigned long
630 fph_index (struct pt_regs *regs, long regnum)
631 {
632 unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f;
633 return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR));
634 }
636 #ifndef XEN
637 static void
638 setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
639 {
640 struct switch_stack *sw = (struct switch_stack *)regs - 1;
641 unsigned long addr;
643 /*
644 * From EAS-2.5: FPDisableFault has higher priority than Unaligned
645 * Fault. Thus, when we get here, we know the partition is enabled.
646 * To update f32-f127, there are three choices:
647 *
648 * (1) save f32-f127 to thread.fph and update the values there
649 * (2) use a gigantic switch statement to directly access the registers
650 * (3) generate code on the fly to update the desired register
651 *
652 * For now, we are using approach (1).
653 */
654 if (regnum >= IA64_FIRST_ROTATING_FR) {
655 ia64_sync_fph(current);
656 #ifdef XEN
657 current->arch._thread.fph[fph_index(regs, regnum)] = *fpval;
658 #else
659 current->thread.fph[fph_index(regs, regnum)] = *fpval;
660 #endif
661 } else {
662 /*
663 * pt_regs or switch_stack ?
664 */
665 if (FR_IN_SW(regnum)) {
666 addr = (unsigned long)sw;
667 } else {
668 addr = (unsigned long)regs;
669 }
671 DPRINT("tmp_base=%lx offset=%d\n", addr, FR_OFFS(regnum));
673 addr += FR_OFFS(regnum);
674 *(struct ia64_fpreg *)addr = *fpval;
676 /*
677 * mark the low partition as being used now
678 *
679 * It is highly unlikely that this bit is not already set, but
680 * let's do it for safety.
681 */
682 regs->cr_ipsr |= IA64_PSR_MFL;
683 }
684 }
685 #endif /* XEN */
687 /*
688 * Those 2 inline functions generate the spilled versions of the constant floating point
689 * registers which can be used with stfX
690 */
691 static inline void
692 float_spill_f0 (struct ia64_fpreg *final)
693 {
694 ia64_stf_spill(final, 0);
695 }
697 static inline void
698 float_spill_f1 (struct ia64_fpreg *final)
699 {
700 ia64_stf_spill(final, 1);
701 }
703 #ifndef XEN
704 static void
705 getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
706 {
707 struct switch_stack *sw = (struct switch_stack *) regs - 1;
708 unsigned long addr;
710 /*
711 * From EAS-2.5: FPDisableFault has higher priority than
712 * Unaligned Fault. Thus, when we get here, we know the partition is
713 * enabled.
714 *
715 * When regnum > 31, the register is still live and we need to force a save
716 * to current->thread.fph to get access to it. See discussion in setfpreg()
717 * for reasons and other ways of doing this.
718 */
719 if (regnum >= IA64_FIRST_ROTATING_FR) {
720 ia64_flush_fph(current);
721 #ifdef XEN
722 *fpval = current->arch._thread.fph[fph_index(regs, regnum)];
723 #else
724 *fpval = current->thread.fph[fph_index(regs, regnum)];
725 #endif
726 } else {
727 /*
728 * f0 = 0.0, f1= 1.0. Those registers are constant and are thus
729 * not saved, we must generate their spilled form on the fly
730 */
731 switch(regnum) {
732 case 0:
733 float_spill_f0(fpval);
734 break;
735 case 1:
736 float_spill_f1(fpval);
737 break;
738 default:
739 /*
740 * pt_regs or switch_stack ?
741 */
742 addr = FR_IN_SW(regnum) ? (unsigned long)sw
743 : (unsigned long)regs;
745 DPRINT("is_sw=%d tmp_base=%lx offset=0x%x\n",
746 FR_IN_SW(regnum), addr, FR_OFFS(regnum));
748 addr += FR_OFFS(regnum);
749 *fpval = *(struct ia64_fpreg *)addr;
750 }
751 }
752 }
753 #else
754 void
755 getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
756 {
757 // Take floating register rotation into consideration
758 if(regnum >= IA64_FIRST_ROTATING_FR)
759 regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum);
760 #define CASE_FIXED_FP(reg) \
761 case reg: \
762 ia64_stf_spill(fpval,reg); \
763 break
764 #define CASE_SAVED_FP(reg) \
765 case reg: \
766 fpval->u.bits[0] = regs->f##reg.u.bits[0]; \
767 fpval->u.bits[1] = regs->f##reg.u.bits[1]; \
768 break
769 switch(regnum) {
770 CASE_FIXED_FP(0);
771 CASE_FIXED_FP(1);
772 CASE_FIXED_FP(2);
773 CASE_FIXED_FP(3);
774 CASE_FIXED_FP(4);
775 CASE_FIXED_FP(5);
777 CASE_SAVED_FP(6);
778 CASE_SAVED_FP(7);
779 CASE_SAVED_FP(8);
780 CASE_SAVED_FP(9);
781 CASE_SAVED_FP(10);
782 CASE_SAVED_FP(11);
784 CASE_FIXED_FP(12);
785 CASE_FIXED_FP(13);
786 CASE_FIXED_FP(14);
787 CASE_FIXED_FP(15);
788 CASE_FIXED_FP(16);
789 CASE_FIXED_FP(17);
790 CASE_FIXED_FP(18);
791 CASE_FIXED_FP(19);
792 CASE_FIXED_FP(20);
793 CASE_FIXED_FP(21);
794 CASE_FIXED_FP(22);
795 CASE_FIXED_FP(23);
796 CASE_FIXED_FP(24);
797 CASE_FIXED_FP(25);
798 CASE_FIXED_FP(26);
799 CASE_FIXED_FP(27);
800 CASE_FIXED_FP(28);
801 CASE_FIXED_FP(29);
802 CASE_FIXED_FP(30);
803 CASE_FIXED_FP(31);
804 CASE_FIXED_FP(32);
805 CASE_FIXED_FP(33);
806 CASE_FIXED_FP(34);
807 CASE_FIXED_FP(35);
808 CASE_FIXED_FP(36);
809 CASE_FIXED_FP(37);
810 CASE_FIXED_FP(38);
811 CASE_FIXED_FP(39);
812 CASE_FIXED_FP(40);
813 CASE_FIXED_FP(41);
814 CASE_FIXED_FP(42);
815 CASE_FIXED_FP(43);
816 CASE_FIXED_FP(44);
817 CASE_FIXED_FP(45);
818 CASE_FIXED_FP(46);
819 CASE_FIXED_FP(47);
820 CASE_FIXED_FP(48);
821 CASE_FIXED_FP(49);
822 CASE_FIXED_FP(50);
823 CASE_FIXED_FP(51);
824 CASE_FIXED_FP(52);
825 CASE_FIXED_FP(53);
826 CASE_FIXED_FP(54);
827 CASE_FIXED_FP(55);
828 CASE_FIXED_FP(56);
829 CASE_FIXED_FP(57);
830 CASE_FIXED_FP(58);
831 CASE_FIXED_FP(59);
832 CASE_FIXED_FP(60);
833 CASE_FIXED_FP(61);
834 CASE_FIXED_FP(62);
835 CASE_FIXED_FP(63);
836 CASE_FIXED_FP(64);
837 CASE_FIXED_FP(65);
838 CASE_FIXED_FP(66);
839 CASE_FIXED_FP(67);
840 CASE_FIXED_FP(68);
841 CASE_FIXED_FP(69);
842 CASE_FIXED_FP(70);
843 CASE_FIXED_FP(71);
844 CASE_FIXED_FP(72);
845 CASE_FIXED_FP(73);
846 CASE_FIXED_FP(74);
847 CASE_FIXED_FP(75);
848 CASE_FIXED_FP(76);
849 CASE_FIXED_FP(77);
850 CASE_FIXED_FP(78);
851 CASE_FIXED_FP(79);
852 CASE_FIXED_FP(80);
853 CASE_FIXED_FP(81);
854 CASE_FIXED_FP(82);
855 CASE_FIXED_FP(83);
856 CASE_FIXED_FP(84);
857 CASE_FIXED_FP(85);
858 CASE_FIXED_FP(86);
859 CASE_FIXED_FP(87);
860 CASE_FIXED_FP(88);
861 CASE_FIXED_FP(89);
862 CASE_FIXED_FP(90);
863 CASE_FIXED_FP(91);
864 CASE_FIXED_FP(92);
865 CASE_FIXED_FP(93);
866 CASE_FIXED_FP(94);
867 CASE_FIXED_FP(95);
868 CASE_FIXED_FP(96);
869 CASE_FIXED_FP(97);
870 CASE_FIXED_FP(98);
871 CASE_FIXED_FP(99);
872 CASE_FIXED_FP(100);
873 CASE_FIXED_FP(101);
874 CASE_FIXED_FP(102);
875 CASE_FIXED_FP(103);
876 CASE_FIXED_FP(104);
877 CASE_FIXED_FP(105);
878 CASE_FIXED_FP(106);
879 CASE_FIXED_FP(107);
880 CASE_FIXED_FP(108);
881 CASE_FIXED_FP(109);
882 CASE_FIXED_FP(110);
883 CASE_FIXED_FP(111);
884 CASE_FIXED_FP(112);
885 CASE_FIXED_FP(113);
886 CASE_FIXED_FP(114);
887 CASE_FIXED_FP(115);
888 CASE_FIXED_FP(116);
889 CASE_FIXED_FP(117);
890 CASE_FIXED_FP(118);
891 CASE_FIXED_FP(119);
892 CASE_FIXED_FP(120);
893 CASE_FIXED_FP(121);
894 CASE_FIXED_FP(122);
895 CASE_FIXED_FP(123);
896 CASE_FIXED_FP(124);
897 CASE_FIXED_FP(125);
898 CASE_FIXED_FP(126);
899 CASE_FIXED_FP(127);
900 }
901 #undef CASE_FIXED_FP
902 #undef CASE_SAVED_FP
903 }
906 void
907 setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
908 {
909 // Take floating register rotation into consideration
910 ia64_fph_enable();
911 if(regnum >= IA64_FIRST_ROTATING_FR)
912 regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum);
914 #define CASE_FIXED_FP(reg) \
915 case reg: \
916 ia64_ldf_fill(reg,fpval); \
917 break
918 #define CASE_RESTORED_FP(reg) \
919 case reg: \
920 regs->f##reg.u.bits[0] = fpval->u.bits[0]; \
921 regs->f##reg.u.bits[1] = fpval->u.bits[1] ; \
922 break
923 switch(regnum) {
924 CASE_FIXED_FP(2);
925 CASE_FIXED_FP(3);
926 CASE_FIXED_FP(4);
927 CASE_FIXED_FP(5);
929 CASE_RESTORED_FP(6);
930 CASE_RESTORED_FP(7);
931 CASE_RESTORED_FP(8);
932 CASE_RESTORED_FP(9);
933 CASE_RESTORED_FP(10);
934 CASE_RESTORED_FP(11);
936 CASE_FIXED_FP(12);
937 CASE_FIXED_FP(13);
938 CASE_FIXED_FP(14);
939 CASE_FIXED_FP(15);
940 CASE_FIXED_FP(16);
941 CASE_FIXED_FP(17);
942 CASE_FIXED_FP(18);
943 CASE_FIXED_FP(19);
944 CASE_FIXED_FP(20);
945 CASE_FIXED_FP(21);
946 CASE_FIXED_FP(22);
947 CASE_FIXED_FP(23);
948 CASE_FIXED_FP(24);
949 CASE_FIXED_FP(25);
950 CASE_FIXED_FP(26);
951 CASE_FIXED_FP(27);
952 CASE_FIXED_FP(28);
953 CASE_FIXED_FP(29);
954 CASE_FIXED_FP(30);
955 CASE_FIXED_FP(31);
956 CASE_FIXED_FP(32);
957 CASE_FIXED_FP(33);
958 CASE_FIXED_FP(34);
959 CASE_FIXED_FP(35);
960 CASE_FIXED_FP(36);
961 CASE_FIXED_FP(37);
962 CASE_FIXED_FP(38);
963 CASE_FIXED_FP(39);
964 CASE_FIXED_FP(40);
965 CASE_FIXED_FP(41);
966 CASE_FIXED_FP(42);
967 CASE_FIXED_FP(43);
968 CASE_FIXED_FP(44);
969 CASE_FIXED_FP(45);
970 CASE_FIXED_FP(46);
971 CASE_FIXED_FP(47);
972 CASE_FIXED_FP(48);
973 CASE_FIXED_FP(49);
974 CASE_FIXED_FP(50);
975 CASE_FIXED_FP(51);
976 CASE_FIXED_FP(52);
977 CASE_FIXED_FP(53);
978 CASE_FIXED_FP(54);
979 CASE_FIXED_FP(55);
980 CASE_FIXED_FP(56);
981 CASE_FIXED_FP(57);
982 CASE_FIXED_FP(58);
983 CASE_FIXED_FP(59);
984 CASE_FIXED_FP(60);
985 CASE_FIXED_FP(61);
986 CASE_FIXED_FP(62);
987 CASE_FIXED_FP(63);
988 CASE_FIXED_FP(64);
989 CASE_FIXED_FP(65);
990 CASE_FIXED_FP(66);
991 CASE_FIXED_FP(67);
992 CASE_FIXED_FP(68);
993 CASE_FIXED_FP(69);
994 CASE_FIXED_FP(70);
995 CASE_FIXED_FP(71);
996 CASE_FIXED_FP(72);
997 CASE_FIXED_FP(73);
998 CASE_FIXED_FP(74);
999 CASE_FIXED_FP(75);
1000 CASE_FIXED_FP(76);
1001 CASE_FIXED_FP(77);
1002 CASE_FIXED_FP(78);
1003 CASE_FIXED_FP(79);
1004 CASE_FIXED_FP(80);
1005 CASE_FIXED_FP(81);
1006 CASE_FIXED_FP(82);
1007 CASE_FIXED_FP(83);
1008 CASE_FIXED_FP(84);
1009 CASE_FIXED_FP(85);
1010 CASE_FIXED_FP(86);
1011 CASE_FIXED_FP(87);
1012 CASE_FIXED_FP(88);
1013 CASE_FIXED_FP(89);
1014 CASE_FIXED_FP(90);
1015 CASE_FIXED_FP(91);
1016 CASE_FIXED_FP(92);
1017 CASE_FIXED_FP(93);
1018 CASE_FIXED_FP(94);
1019 CASE_FIXED_FP(95);
1020 CASE_FIXED_FP(96);
1021 CASE_FIXED_FP(97);
1022 CASE_FIXED_FP(98);
1023 CASE_FIXED_FP(99);
1024 CASE_FIXED_FP(100);
1025 CASE_FIXED_FP(101);
1026 CASE_FIXED_FP(102);
1027 CASE_FIXED_FP(103);
1028 CASE_FIXED_FP(104);
1029 CASE_FIXED_FP(105);
1030 CASE_FIXED_FP(106);
1031 CASE_FIXED_FP(107);
1032 CASE_FIXED_FP(108);
1033 CASE_FIXED_FP(109);
1034 CASE_FIXED_FP(110);
1035 CASE_FIXED_FP(111);
1036 CASE_FIXED_FP(112);
1037 CASE_FIXED_FP(113);
1038 CASE_FIXED_FP(114);
1039 CASE_FIXED_FP(115);
1040 CASE_FIXED_FP(116);
1041 CASE_FIXED_FP(117);
1042 CASE_FIXED_FP(118);
1043 CASE_FIXED_FP(119);
1044 CASE_FIXED_FP(120);
1045 CASE_FIXED_FP(121);
1046 CASE_FIXED_FP(122);
1047 CASE_FIXED_FP(123);
1048 CASE_FIXED_FP(124);
1049 CASE_FIXED_FP(125);
1050 CASE_FIXED_FP(126);
1051 CASE_FIXED_FP(127);
1053 #undef CASE_FIXED_FP
1054 #undef CASE_RESTORED_FP
1057 #endif /* XEN */
1060 #ifdef XEN
1061 void
1062 #else
1063 static void
1064 #endif
1065 getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs)
1067 struct switch_stack *sw = (struct switch_stack *) regs - 1;
1068 unsigned long addr, *unat;
1070 if (regnum >= IA64_FIRST_STACKED_GR) {
1071 get_rse_reg(regs, regnum, val, nat);
1072 return;
1075 /*
1076 * take care of r0 (read-only always evaluate to 0)
1077 */
1078 if (regnum == 0) {
1079 *val = 0;
1080 if (nat)
1081 *nat = 0;
1082 return;
1085 /*
1086 * Now look at registers in [0-31] range and init correct UNAT
1087 */
1088 if (GR_IN_SW(regnum)) {
1089 addr = (unsigned long)sw;
1090 unat = &sw->ar_unat;
1091 } else {
1092 addr = (unsigned long)regs;
1093 #if defined(XEN)
1094 unat = &regs->eml_unat;;
1095 #else
1096 unat = &sw->caller_unat;
1097 #endif
1100 DPRINT("addr_base=%lx offset=0x%x\n", addr, GR_OFFS(regnum));
1102 addr += GR_OFFS(regnum);
1104 *val = *(unsigned long *)addr;
1106 /*
1107 * do it only when requested
1108 */
1109 if (nat)
1110 *nat = (*unat >> (addr >> 3 & 0x3f)) & 0x1UL;
1113 #ifndef XEN
1114 static void
1115 emulate_load_updates (update_t type, load_store_t ld, struct pt_regs *regs, unsigned long ifa)
1117 /*
1118 * IMPORTANT:
1119 * Given the way we handle unaligned speculative loads, we should
1120 * not get to this point in the code but we keep this sanity check,
1121 * just in case.
1122 */
1123 if (ld.x6_op == 1 || ld.x6_op == 3) {
1124 printk(KERN_ERR "%s: register update on speculative load, error\n", __FUNCTION__);
1125 die_if_kernel("unaligned reference on speculative load with register update\n",
1126 regs, 30);
1130 /*
1131 * at this point, we know that the base register to update is valid i.e.,
1132 * it's not r0
1133 */
1134 if (type == UPD_IMMEDIATE) {
1135 unsigned long imm;
1137 /*
1138 * Load +Imm: ldXZ r1=[r3],imm(9)
1141 * form imm9: [13:19] contain the first 7 bits
1142 */
1143 imm = ld.x << 7 | ld.imm;
1145 /*
1146 * sign extend (1+8bits) if m set
1147 */
1148 if (ld.m) imm |= SIGN_EXT9;
1150 /*
1151 * ifa == r3 and we know that the NaT bit on r3 was clear so
1152 * we can directly use ifa.
1153 */
1154 ifa += imm;
1156 setreg(ld.r3, ifa, 0, regs);
1158 DPRINT("ld.x=%d ld.m=%d imm=%ld r3=0x%lx\n", ld.x, ld.m, imm, ifa);
1160 } else if (ld.m) {
1161 unsigned long r2;
1162 int nat_r2;
1164 /*
1165 * Load +Reg Opcode: ldXZ r1=[r3],r2
1167 * Note: that we update r3 even in the case of ldfX.a
1168 * (where the load does not happen)
1170 * The way the load algorithm works, we know that r3 does not
1171 * have its NaT bit set (would have gotten NaT consumption
1172 * before getting the unaligned fault). So we can use ifa
1173 * which equals r3 at this point.
1175 * IMPORTANT:
1176 * The above statement holds ONLY because we know that we
1177 * never reach this code when trying to do a ldX.s.
1178 * If we ever make it to here on an ldfX.s then
1179 */
1180 getreg(ld.imm, &r2, &nat_r2, regs);
1182 ifa += r2;
1184 /*
1185 * propagate Nat r2 -> r3
1186 */
1187 setreg(ld.r3, ifa, nat_r2, regs);
1189 DPRINT("imm=%d r2=%ld r3=0x%lx nat_r2=%d\n",ld.imm, r2, ifa, nat_r2);
1194 static int
1195 emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1197 unsigned int len = 1 << ld.x6_sz;
1198 unsigned long val = 0;
1200 /*
1201 * r0, as target, doesn't need to be checked because Illegal Instruction
1202 * faults have higher priority than unaligned faults.
1204 * r0 cannot be found as the base as it would never generate an
1205 * unaligned reference.
1206 */
1208 /*
1209 * ldX.a we will emulate load and also invalidate the ALAT entry.
1210 * See comment below for explanation on how we handle ldX.a
1211 */
1213 if (len != 2 && len != 4 && len != 8) {
1214 DPRINT("unknown size: x6=%d\n", ld.x6_sz);
1215 return -1;
1217 /* this assumes little-endian byte-order: */
1218 if (copy_from_user(&val, (void __user *) ifa, len))
1219 return -1;
1220 setreg(ld.r1, val, 0, regs);
1222 /*
1223 * check for updates on any kind of loads
1224 */
1225 if (ld.op == 0x5 || ld.m)
1226 emulate_load_updates(ld.op == 0x5 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
1228 /*
1229 * handling of various loads (based on EAS2.4):
1231 * ldX.acq (ordered load):
1232 * - acquire semantics would have been used, so force fence instead.
1234 * ldX.c.clr (check load and clear):
1235 * - if we get to this handler, it's because the entry was not in the ALAT.
1236 * Therefore the operation reverts to a normal load
1238 * ldX.c.nc (check load no clear):
1239 * - same as previous one
1241 * ldX.c.clr.acq (ordered check load and clear):
1242 * - same as above for c.clr part. The load needs to have acquire semantics. So
1243 * we use the fence semantics which is stronger and thus ensures correctness.
1245 * ldX.a (advanced load):
1246 * - suppose ldX.a r1=[r3]. If we get to the unaligned trap it's because the
1247 * address doesn't match requested size alignment. This means that we would
1248 * possibly need more than one load to get the result.
1250 * The load part can be handled just like a normal load, however the difficult
1251 * part is to get the right thing into the ALAT. The critical piece of information
1252 * in the base address of the load & size. To do that, a ld.a must be executed,
1253 * clearly any address can be pushed into the table by using ld1.a r1=[r3]. Now
1254 * if we use the same target register, we will be okay for the check.a instruction.
1255 * If we look at the store, basically a stX [r3]=r1 checks the ALAT for any entry
1256 * which would overlap within [r3,r3+X] (the size of the load was store in the
1257 * ALAT). If such an entry is found the entry is invalidated. But this is not good
1258 * enough, take the following example:
1259 * r3=3
1260 * ld4.a r1=[r3]
1262 * Could be emulated by doing:
1263 * ld1.a r1=[r3],1
1264 * store to temporary;
1265 * ld1.a r1=[r3],1
1266 * store & shift to temporary;
1267 * ld1.a r1=[r3],1
1268 * store & shift to temporary;
1269 * ld1.a r1=[r3]
1270 * store & shift to temporary;
1271 * r1=temporary
1273 * So in this case, you would get the right value is r1 but the wrong info in
1274 * the ALAT. Notice that you could do it in reverse to finish with address 3
1275 * but you would still get the size wrong. To get the size right, one needs to
1276 * execute exactly the same kind of load. You could do it from a aligned
1277 * temporary location, but you would get the address wrong.
1279 * So no matter what, it is not possible to emulate an advanced load
1280 * correctly. But is that really critical ?
1282 * We will always convert ld.a into a normal load with ALAT invalidated. This
1283 * will enable compiler to do optimization where certain code path after ld.a
1284 * is not required to have ld.c/chk.a, e.g., code path with no intervening stores.
1286 * If there is a store after the advanced load, one must either do a ld.c.* or
1287 * chk.a.* to reuse the value stored in the ALAT. Both can "fail" (meaning no
1288 * entry found in ALAT), and that's perfectly ok because:
1290 * - ld.c.*, if the entry is not present a normal load is executed
1291 * - chk.a.*, if the entry is not present, execution jumps to recovery code
1293 * In either case, the load can be potentially retried in another form.
1295 * ALAT must be invalidated for the register (so that chk.a or ld.c don't pick
1296 * up a stale entry later). The register base update MUST also be performed.
1297 */
1299 /*
1300 * when the load has the .acq completer then
1301 * use ordering fence.
1302 */
1303 if (ld.x6_op == 0x5 || ld.x6_op == 0xa)
1304 mb();
1306 /*
1307 * invalidate ALAT entry in case of advanced load
1308 */
1309 if (ld.x6_op == 0x2)
1310 invala_gr(ld.r1);
1312 return 0;
1315 static int
1316 emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1318 unsigned long r2;
1319 unsigned int len = 1 << ld.x6_sz;
1321 /*
1322 * if we get to this handler, Nat bits on both r3 and r2 have already
1323 * been checked. so we don't need to do it
1325 * extract the value to be stored
1326 */
1327 getreg(ld.imm, &r2, NULL, regs);
1329 /*
1330 * we rely on the macros in unaligned.h for now i.e.,
1331 * we let the compiler figure out how to read memory gracefully.
1333 * We need this switch/case because the way the inline function
1334 * works. The code is optimized by the compiler and looks like
1335 * a single switch/case.
1336 */
1337 DPRINT("st%d [%lx]=%lx\n", len, ifa, r2);
1339 if (len != 2 && len != 4 && len != 8) {
1340 DPRINT("unknown size: x6=%d\n", ld.x6_sz);
1341 return -1;
1344 /* this assumes little-endian byte-order: */
1345 if (copy_to_user((void __user *) ifa, &r2, len))
1346 return -1;
1348 /*
1349 * stX [r3]=r2,imm(9)
1351 * NOTE:
1352 * ld.r3 can never be r0, because r0 would not generate an
1353 * unaligned access.
1354 */
1355 if (ld.op == 0x5) {
1356 unsigned long imm;
1358 /*
1359 * form imm9: [12:6] contain first 7bits
1360 */
1361 imm = ld.x << 7 | ld.r1;
1362 /*
1363 * sign extend (8bits) if m set
1364 */
1365 if (ld.m) imm |= SIGN_EXT9;
1366 /*
1367 * ifa == r3 (NaT is necessarily cleared)
1368 */
1369 ifa += imm;
1371 DPRINT("imm=%lx r3=%lx\n", imm, ifa);
1373 setreg(ld.r3, ifa, 0, regs);
1375 /*
1376 * we don't have alat_invalidate_multiple() so we need
1377 * to do the complete flush :-<<
1378 */
1379 ia64_invala();
1381 /*
1382 * stX.rel: use fence instead of release
1383 */
1384 if (ld.x6_op == 0xd)
1385 mb();
1387 return 0;
1389 #endif /* XEN */
1391 /*
1392 * floating point operations sizes in bytes
1393 */
1394 static const unsigned char float_fsz[4]={
1395 10, /* extended precision (e) */
1396 8, /* integer (8) */
1397 4, /* single precision (s) */
1398 8 /* double precision (d) */
1399 };
1401 static inline void
1402 mem2float_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
1404 ia64_ldfe(6, init);
1405 ia64_stop();
1406 ia64_stf_spill(final, 6);
1409 static inline void
1410 mem2float_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
1412 ia64_ldf8(6, init);
1413 ia64_stop();
1414 ia64_stf_spill(final, 6);
1417 static inline void
1418 mem2float_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
1420 ia64_ldfs(6, init);
1421 ia64_stop();
1422 ia64_stf_spill(final, 6);
1425 static inline void
1426 mem2float_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
1428 ia64_ldfd(6, init);
1429 ia64_stop();
1430 ia64_stf_spill(final, 6);
1433 static inline void
1434 float2mem_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
1436 ia64_ldf_fill(6, init);
1437 ia64_stop();
1438 ia64_stfe(final, 6);
1441 static inline void
1442 float2mem_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
1444 ia64_ldf_fill(6, init);
1445 ia64_stop();
1446 ia64_stf8(final, 6);
1449 static inline void
1450 float2mem_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
1452 ia64_ldf_fill(6, init);
1453 ia64_stop();
1454 ia64_stfs(final, 6);
1457 static inline void
1458 float2mem_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
1460 ia64_ldf_fill(6, init);
1461 ia64_stop();
1462 ia64_stfd(final, 6);
1465 #ifndef XEN
1466 static int
1467 emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1469 struct ia64_fpreg fpr_init[2];
1470 struct ia64_fpreg fpr_final[2];
1471 unsigned long len = float_fsz[ld.x6_sz];
1473 /*
1474 * fr0 & fr1 don't need to be checked because Illegal Instruction faults have
1475 * higher priority than unaligned faults.
1477 * r0 cannot be found as the base as it would never generate an unaligned
1478 * reference.
1479 */
1481 /*
1482 * make sure we get clean buffers
1483 */
1484 memset(&fpr_init, 0, sizeof(fpr_init));
1485 memset(&fpr_final, 0, sizeof(fpr_final));
1487 /*
1488 * ldfpX.a: we don't try to emulate anything but we must
1489 * invalidate the ALAT entry and execute updates, if any.
1490 */
1491 if (ld.x6_op != 0x2) {
1492 /*
1493 * This assumes little-endian byte-order. Note that there is no "ldfpe"
1494 * instruction:
1495 */
1496 if (copy_from_user(&fpr_init[0], (void __user *) ifa, len)
1497 || copy_from_user(&fpr_init[1], (void __user *) (ifa + len), len))
1498 return -1;
1500 DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz);
1501 DDUMP("frp_init =", &fpr_init, 2*len);
1502 /*
1503 * XXX fixme
1504 * Could optimize inlines by using ldfpX & 2 spills
1505 */
1506 switch( ld.x6_sz ) {
1507 case 0:
1508 mem2float_extended(&fpr_init[0], &fpr_final[0]);
1509 mem2float_extended(&fpr_init[1], &fpr_final[1]);
1510 break;
1511 case 1:
1512 mem2float_integer(&fpr_init[0], &fpr_final[0]);
1513 mem2float_integer(&fpr_init[1], &fpr_final[1]);
1514 break;
1515 case 2:
1516 mem2float_single(&fpr_init[0], &fpr_final[0]);
1517 mem2float_single(&fpr_init[1], &fpr_final[1]);
1518 break;
1519 case 3:
1520 mem2float_double(&fpr_init[0], &fpr_final[0]);
1521 mem2float_double(&fpr_init[1], &fpr_final[1]);
1522 break;
1524 DDUMP("fpr_final =", &fpr_final, 2*len);
1525 /*
1526 * XXX fixme
1528 * A possible optimization would be to drop fpr_final and directly
1529 * use the storage from the saved context i.e., the actual final
1530 * destination (pt_regs, switch_stack or thread structure).
1531 */
1532 setfpreg(ld.r1, &fpr_final[0], regs);
1533 setfpreg(ld.imm, &fpr_final[1], regs);
1536 /*
1537 * Check for updates: only immediate updates are available for this
1538 * instruction.
1539 */
1540 if (ld.m) {
1541 /*
1542 * the immediate is implicit given the ldsz of the operation:
1543 * single: 8 (2x4) and for all others it's 16 (2x8)
1544 */
1545 ifa += len<<1;
1547 /*
1548 * IMPORTANT:
1549 * the fact that we force the NaT of r3 to zero is ONLY valid
1550 * as long as we don't come here with a ldfpX.s.
1551 * For this reason we keep this sanity check
1552 */
1553 if (ld.x6_op == 1 || ld.x6_op == 3)
1554 printk(KERN_ERR "%s: register update on speculative load pair, error\n",
1555 __FUNCTION__);
1557 setreg(ld.r3, ifa, 0, regs);
1560 /*
1561 * Invalidate ALAT entries, if any, for both registers.
1562 */
1563 if (ld.x6_op == 0x2) {
1564 invala_fr(ld.r1);
1565 invala_fr(ld.imm);
1567 return 0;
1571 static int
1572 emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1574 struct ia64_fpreg fpr_init;
1575 struct ia64_fpreg fpr_final;
1576 unsigned long len = float_fsz[ld.x6_sz];
1578 /*
1579 * fr0 & fr1 don't need to be checked because Illegal Instruction
1580 * faults have higher priority than unaligned faults.
1582 * r0 cannot be found as the base as it would never generate an
1583 * unaligned reference.
1584 */
1586 /*
1587 * make sure we get clean buffers
1588 */
1589 memset(&fpr_init,0, sizeof(fpr_init));
1590 memset(&fpr_final,0, sizeof(fpr_final));
1592 /*
1593 * ldfX.a we don't try to emulate anything but we must
1594 * invalidate the ALAT entry.
1595 * See comments in ldX for descriptions on how the various loads are handled.
1596 */
1597 if (ld.x6_op != 0x2) {
1598 if (copy_from_user(&fpr_init, (void __user *) ifa, len))
1599 return -1;
1601 DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
1602 DDUMP("fpr_init =", &fpr_init, len);
1603 /*
1604 * we only do something for x6_op={0,8,9}
1605 */
1606 switch( ld.x6_sz ) {
1607 case 0:
1608 mem2float_extended(&fpr_init, &fpr_final);
1609 break;
1610 case 1:
1611 mem2float_integer(&fpr_init, &fpr_final);
1612 break;
1613 case 2:
1614 mem2float_single(&fpr_init, &fpr_final);
1615 break;
1616 case 3:
1617 mem2float_double(&fpr_init, &fpr_final);
1618 break;
1620 DDUMP("fpr_final =", &fpr_final, len);
1621 /*
1622 * XXX fixme
1624 * A possible optimization would be to drop fpr_final and directly
1625 * use the storage from the saved context i.e., the actual final
1626 * destination (pt_regs, switch_stack or thread structure).
1627 */
1628 setfpreg(ld.r1, &fpr_final, regs);
1631 /*
1632 * check for updates on any loads
1633 */
1634 if (ld.op == 0x7 || ld.m)
1635 emulate_load_updates(ld.op == 0x7 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
1637 /*
1638 * invalidate ALAT entry in case of advanced floating point loads
1639 */
1640 if (ld.x6_op == 0x2)
1641 invala_fr(ld.r1);
1643 return 0;
1647 static int
1648 emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1650 struct ia64_fpreg fpr_init;
1651 struct ia64_fpreg fpr_final;
1652 unsigned long len = float_fsz[ld.x6_sz];
1654 /*
1655 * make sure we get clean buffers
1656 */
1657 memset(&fpr_init,0, sizeof(fpr_init));
1658 memset(&fpr_final,0, sizeof(fpr_final));
1660 /*
1661 * if we get to this handler, Nat bits on both r3 and r2 have already
1662 * been checked. so we don't need to do it
1664 * extract the value to be stored
1665 */
1666 getfpreg(ld.imm, &fpr_init, regs);
1667 /*
1668 * during this step, we extract the spilled registers from the saved
1669 * context i.e., we refill. Then we store (no spill) to temporary
1670 * aligned location
1671 */
1672 switch( ld.x6_sz ) {
1673 case 0:
1674 float2mem_extended(&fpr_init, &fpr_final);
1675 break;
1676 case 1:
1677 float2mem_integer(&fpr_init, &fpr_final);
1678 break;
1679 case 2:
1680 float2mem_single(&fpr_init, &fpr_final);
1681 break;
1682 case 3:
1683 float2mem_double(&fpr_init, &fpr_final);
1684 break;
1686 DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
1687 DDUMP("fpr_init =", &fpr_init, len);
1688 DDUMP("fpr_final =", &fpr_final, len);
1690 if (copy_to_user((void __user *) ifa, &fpr_final, len))
1691 return -1;
1693 /*
1694 * stfX [r3]=r2,imm(9)
1696 * NOTE:
1697 * ld.r3 can never be r0, because r0 would not generate an
1698 * unaligned access.
1699 */
1700 if (ld.op == 0x7) {
1701 unsigned long imm;
1703 /*
1704 * form imm9: [12:6] contain first 7bits
1705 */
1706 imm = ld.x << 7 | ld.r1;
1707 /*
1708 * sign extend (8bits) if m set
1709 */
1710 if (ld.m)
1711 imm |= SIGN_EXT9;
1712 /*
1713 * ifa == r3 (NaT is necessarily cleared)
1714 */
1715 ifa += imm;
1717 DPRINT("imm=%lx r3=%lx\n", imm, ifa);
1719 setreg(ld.r3, ifa, 0, regs);
1721 /*
1722 * we don't have alat_invalidate_multiple() so we need
1723 * to do the complete flush :-<<
1724 */
1725 ia64_invala();
1727 return 0;
1730 /*
1731 * Make sure we log the unaligned access, so that user/sysadmin can notice it and
1732 * eventually fix the program. However, we don't want to do that for every access so we
1733 * pace it with jiffies. This isn't really MP-safe, but it doesn't really have to be
1734 * either...
1735 */
1736 static int
1737 within_logging_rate_limit (void)
1739 static unsigned long count, last_time;
1741 if (jiffies - last_time > 5*HZ)
1742 count = 0;
1743 if (++count < 5) {
1744 last_time = jiffies;
1745 return 1;
1747 return 0;
1750 #endif /* XEN */
1752 void
1753 ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
1755 #ifdef XEN
1756 printk("ia64_handle_unaligned: called, not working yet\n");
1757 #else
1758 struct ia64_psr *ipsr = ia64_psr(regs);
1759 mm_segment_t old_fs = get_fs();
1760 unsigned long bundle[2];
1761 unsigned long opcode;
1762 struct siginfo si;
1763 const struct exception_table_entry *eh = NULL;
1764 union {
1765 unsigned long l;
1766 load_store_t insn;
1767 } u;
1768 int ret = -1;
1770 if (ia64_psr(regs)->be) {
1771 /* we don't support big-endian accesses */
1772 die_if_kernel("big-endian unaligned accesses are not supported", regs, 0);
1773 goto force_sigbus;
1776 /*
1777 * Treat kernel accesses for which there is an exception handler entry the same as
1778 * user-level unaligned accesses. Otherwise, a clever program could trick this
1779 * handler into reading an arbitrary kernel addresses...
1780 */
1781 if (!user_mode(regs))
1782 eh = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
1783 if (user_mode(regs) || eh) {
1784 if ((current->thread.flags & IA64_THREAD_UAC_SIGBUS) != 0)
1785 goto force_sigbus;
1787 if (!(current->thread.flags & IA64_THREAD_UAC_NOPRINT)
1788 && within_logging_rate_limit())
1790 char buf[200]; /* comm[] is at most 16 bytes... */
1791 size_t len;
1793 len = sprintf(buf, "%s(%d): unaligned access to 0x%016lx, "
1794 "ip=0x%016lx\n\r", current->comm, current->pid,
1795 ifa, regs->cr_iip + ipsr->ri);
1796 /*
1797 * Don't call tty_write_message() if we're in the kernel; we might
1798 * be holding locks...
1799 */
1800 if (user_mode(regs))
1801 tty_write_message(current->signal->tty, buf);
1802 buf[len-1] = '\0'; /* drop '\r' */
1803 printk(KERN_WARNING "%s", buf); /* watch for command names containing %s */
1805 } else {
1806 if (within_logging_rate_limit())
1807 printk(KERN_WARNING "kernel unaligned access to 0x%016lx, ip=0x%016lx\n",
1808 ifa, regs->cr_iip + ipsr->ri);
1809 set_fs(KERNEL_DS);
1812 DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n",
1813 regs->cr_iip, ifa, regs->cr_ipsr, ipsr->ri, ipsr->it);
1815 if (__copy_from_user(bundle, (void __user *) regs->cr_iip, 16))
1816 goto failure;
1818 /*
1819 * extract the instruction from the bundle given the slot number
1820 */
1821 switch (ipsr->ri) {
1822 case 0: u.l = (bundle[0] >> 5); break;
1823 case 1: u.l = (bundle[0] >> 46) | (bundle[1] << 18); break;
1824 case 2: u.l = (bundle[1] >> 23); break;
1826 opcode = (u.l >> IA64_OPCODE_SHIFT) & IA64_OPCODE_MASK;
1828 DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d "
1829 "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm,
1830 u.insn.r3, u.insn.x, u.insn.hint, u.insn.x6_sz, u.insn.m, u.insn.op);
1832 /*
1833 * IMPORTANT:
1834 * Notice that the switch statement DOES not cover all possible instructions
1835 * that DO generate unaligned references. This is made on purpose because for some
1836 * instructions it DOES NOT make sense to try and emulate the access. Sometimes it
1837 * is WRONG to try and emulate. Here is a list of instruction we don't emulate i.e.,
1838 * the program will get a signal and die:
1840 * load/store:
1841 * - ldX.spill
1842 * - stX.spill
1843 * Reason: RNATs are based on addresses
1844 * - ld16
1845 * - st16
1846 * Reason: ld16 and st16 are supposed to occur in a single
1847 * memory op
1849 * synchronization:
1850 * - cmpxchg
1851 * - fetchadd
1852 * - xchg
1853 * Reason: ATOMIC operations cannot be emulated properly using multiple
1854 * instructions.
1856 * speculative loads:
1857 * - ldX.sZ
1858 * Reason: side effects, code must be ready to deal with failure so simpler
1859 * to let the load fail.
1860 * ---------------------------------------------------------------------------------
1861 * XXX fixme
1863 * I would like to get rid of this switch case and do something
1864 * more elegant.
1865 */
1866 switch (opcode) {
1867 case LDS_OP:
1868 case LDSA_OP:
1869 if (u.insn.x)
1870 /* oops, really a semaphore op (cmpxchg, etc) */
1871 goto failure;
1872 /* no break */
1873 case LDS_IMM_OP:
1874 case LDSA_IMM_OP:
1875 case LDFS_OP:
1876 case LDFSA_OP:
1877 case LDFS_IMM_OP:
1878 /*
1879 * The instruction will be retried with deferred exceptions turned on, and
1880 * we should get Nat bit installed
1882 * IMPORTANT: When PSR_ED is set, the register & immediate update forms
1883 * are actually executed even though the operation failed. So we don't
1884 * need to take care of this.
1885 */
1886 DPRINT("forcing PSR_ED\n");
1887 regs->cr_ipsr |= IA64_PSR_ED;
1888 goto done;
1890 case LD_OP:
1891 case LDA_OP:
1892 case LDBIAS_OP:
1893 case LDACQ_OP:
1894 case LDCCLR_OP:
1895 case LDCNC_OP:
1896 case LDCCLRACQ_OP:
1897 if (u.insn.x)
1898 /* oops, really a semaphore op (cmpxchg, etc) */
1899 goto failure;
1900 /* no break */
1901 case LD_IMM_OP:
1902 case LDA_IMM_OP:
1903 case LDBIAS_IMM_OP:
1904 case LDACQ_IMM_OP:
1905 case LDCCLR_IMM_OP:
1906 case LDCNC_IMM_OP:
1907 case LDCCLRACQ_IMM_OP:
1908 ret = emulate_load_int(ifa, u.insn, regs);
1909 break;
1911 case ST_OP:
1912 case STREL_OP:
1913 if (u.insn.x)
1914 /* oops, really a semaphore op (cmpxchg, etc) */
1915 goto failure;
1916 /* no break */
1917 case ST_IMM_OP:
1918 case STREL_IMM_OP:
1919 ret = emulate_store_int(ifa, u.insn, regs);
1920 break;
1922 case LDF_OP:
1923 case LDFA_OP:
1924 case LDFCCLR_OP:
1925 case LDFCNC_OP:
1926 case LDF_IMM_OP:
1927 case LDFA_IMM_OP:
1928 case LDFCCLR_IMM_OP:
1929 case LDFCNC_IMM_OP:
1930 if (u.insn.x)
1931 ret = emulate_load_floatpair(ifa, u.insn, regs);
1932 else
1933 ret = emulate_load_float(ifa, u.insn, regs);
1934 break;
1936 case STF_OP:
1937 case STF_IMM_OP:
1938 ret = emulate_store_float(ifa, u.insn, regs);
1939 break;
1941 default:
1942 goto failure;
1944 DPRINT("ret=%d\n", ret);
1945 if (ret)
1946 goto failure;
1948 if (ipsr->ri == 2)
1949 /*
1950 * given today's architecture this case is not likely to happen because a
1951 * memory access instruction (M) can never be in the last slot of a
1952 * bundle. But let's keep it for now.
1953 */
1954 regs->cr_iip += 16;
1955 ipsr->ri = (ipsr->ri + 1) & 0x3;
1957 DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip);
1958 done:
1959 set_fs(old_fs); /* restore original address limit */
1960 return;
1962 failure:
1963 /* something went wrong... */
1964 if (!user_mode(regs)) {
1965 if (eh) {
1966 ia64_handle_exception(regs, eh);
1967 goto done;
1969 die_if_kernel("error during unaligned kernel access\n", regs, ret);
1970 /* NOT_REACHED */
1972 force_sigbus:
1973 si.si_signo = SIGBUS;
1974 si.si_errno = 0;
1975 si.si_code = BUS_ADRALN;
1976 si.si_addr = (void __user *) ifa;
1977 si.si_flags = 0;
1978 si.si_isr = 0;
1979 si.si_imm = 0;
1980 force_sig_info(SIGBUS, &si, current);
1981 goto done;
1982 #endif