ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 10888:5379548bfc79

[NET] Enable TCPv4 segmentation offload in front/back drivers.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Tue Aug 01 11:54:45 2006 +0100 (2006-08-01)
parents 0a226de3fc37
children 16aa4b417c6b
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #ifndef XEN
45 #include <linux/platform.h>
46 #include <linux/pm.h>
47 #endif
49 #include <asm/ia32.h>
50 #include <asm/machvec.h>
51 #include <asm/mca.h>
52 #include <asm/meminit.h>
53 #include <asm/page.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
57 #include <asm/sal.h>
58 #include <asm/sections.h>
59 #include <asm/serial.h>
60 #include <asm/setup.h>
61 #include <asm/smp.h>
62 #include <asm/system.h>
63 #include <asm/unistd.h>
64 #ifdef XEN
65 #include <asm/vmx.h>
66 #include <asm/io.h>
67 #endif
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
79 #ifdef XEN
80 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
81 #endif
82 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
83 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
84 unsigned long ia64_cycles_per_usec;
85 struct ia64_boot_param *ia64_boot_param;
86 struct screen_info screen_info;
87 unsigned long vga_console_iobase;
88 unsigned long vga_console_membase;
90 unsigned long ia64_max_cacheline_size;
91 unsigned long ia64_iobase; /* virtual address for I/O accesses */
92 EXPORT_SYMBOL(ia64_iobase);
93 struct io_space io_space[MAX_IO_SPACES];
94 EXPORT_SYMBOL(io_space);
95 unsigned int num_io_spaces;
97 #ifdef XEN
98 extern void early_cmdline_parse(char **);
99 #endif
101 /*
102 * "flush_icache_range()" needs to know what processor dependent stride size to use
103 * when it makes i-cache(s) coherent with d-caches.
104 */
105 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
106 unsigned long ia64_i_cache_stride_shift = ~0;
108 #ifdef XEN
109 #define D_CACHE_STRIDE_SHIFT 5 /* Safest. */
110 unsigned long ia64_d_cache_stride_shift = ~0;
111 #endif
113 /*
114 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
115 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
116 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
117 * address of the second buffer must be aligned to (merge_mask+1) in order to be
118 * mergeable). By default, we assume there is no I/O MMU which can merge physically
119 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
120 * page-size of 2^64.
121 */
122 unsigned long ia64_max_iommu_merge_mask = ~0UL;
123 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
125 /*
126 * We use a special marker for the end of memory and it uses the extra (+1) slot
127 */
128 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
129 int num_rsvd_regions;
132 /*
133 * Filter incoming memory segments based on the primitive map created from the boot
134 * parameters. Segments contained in the map are removed from the memory ranges. A
135 * caller-specified function is called with the memory ranges that remain after filtering.
136 * This routine does not assume the incoming segments are sorted.
137 */
138 int
139 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
140 {
141 unsigned long range_start, range_end, prev_start;
142 void (*func)(unsigned long, unsigned long, int);
143 int i;
145 #if IGNORE_PFN0
146 if (start == PAGE_OFFSET) {
147 printk(KERN_WARNING "warning: skipping physical page 0\n");
148 start += PAGE_SIZE;
149 if (start >= end) return 0;
150 }
151 #endif
152 /*
153 * lowest possible address(walker uses virtual)
154 */
155 prev_start = PAGE_OFFSET;
156 func = arg;
158 for (i = 0; i < num_rsvd_regions; ++i) {
159 range_start = max(start, prev_start);
160 range_end = min(end, rsvd_region[i].start);
162 if (range_start < range_end)
163 #ifdef XEN
164 {
165 /* init_boot_pages requires "ps, pe" */
166 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
167 __pa(range_start), __pa(range_end));
168 (*func)(__pa(range_start), __pa(range_end), 0);
169 }
170 #else
171 call_pernode_memory(__pa(range_start), range_end - range_start, func);
172 #endif
174 /* nothing more available in this segment */
175 if (range_end == end) return 0;
177 prev_start = rsvd_region[i].end;
178 }
179 /* end of memory marker allows full processing inside loop body */
180 return 0;
181 }
183 static void
184 sort_regions (struct rsvd_region *rsvd_region, int max)
185 {
186 int j;
188 /* simple bubble sorting */
189 while (max--) {
190 for (j = 0; j < max; ++j) {
191 if (rsvd_region[j].start > rsvd_region[j+1].start) {
192 struct rsvd_region tmp;
193 tmp = rsvd_region[j];
194 rsvd_region[j] = rsvd_region[j + 1];
195 rsvd_region[j + 1] = tmp;
196 }
197 }
198 }
199 }
201 /**
202 * reserve_memory - setup reserved memory areas
203 *
204 * Setup the reserved memory areas set aside for the boot parameters,
205 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
206 * see include/asm-ia64/meminit.h if you need to define more.
207 */
208 void
209 reserve_memory (void)
210 {
211 int n = 0;
213 /*
214 * none of the entries in this table overlap
215 */
216 rsvd_region[n].start = (unsigned long) ia64_boot_param;
217 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
218 n++;
220 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
221 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
222 n++;
224 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
225 rsvd_region[n].end = (rsvd_region[n].start
226 + strlen(__va(ia64_boot_param->command_line)) + 1);
227 n++;
229 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
230 #ifdef XEN
231 /* Reserve xen image/bitmap/xen-heap */
232 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
233 #else
234 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
235 #endif
236 n++;
238 #ifdef XEN
239 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->domain_start);
240 rsvd_region[n].end = (rsvd_region[n].start + ia64_boot_param->domain_size);
241 n++;
242 #endif
244 #if defined(XEN)||defined(CONFIG_BLK_DEV_INITRD)
245 if (ia64_boot_param->initrd_start) {
246 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
247 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
248 n++;
249 }
250 #endif
252 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
253 n++;
255 /* end of memory marker */
256 rsvd_region[n].start = ~0UL;
257 rsvd_region[n].end = ~0UL;
258 n++;
260 num_rsvd_regions = n;
262 sort_regions(rsvd_region, num_rsvd_regions);
263 }
265 /**
266 * find_initrd - get initrd parameters from the boot parameter structure
267 *
268 * Grab the initrd start and end from the boot parameter struct given us by
269 * the boot loader.
270 */
271 void
272 find_initrd (void)
273 {
274 #ifdef CONFIG_BLK_DEV_INITRD
275 if (ia64_boot_param->initrd_start) {
276 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
277 initrd_end = initrd_start+ia64_boot_param->initrd_size;
279 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
280 initrd_start, ia64_boot_param->initrd_size);
281 }
282 #endif
283 }
285 static void __init
286 io_port_init (void)
287 {
288 extern unsigned long ia64_iobase;
289 unsigned long phys_iobase;
291 /*
292 * Set `iobase' to the appropriate address in region 6 (uncached access range).
293 *
294 * The EFI memory map is the "preferred" location to get the I/O port space base,
295 * rather the relying on AR.KR0. This should become more clear in future SAL
296 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
297 * found in the memory map.
298 */
299 phys_iobase = efi_get_iobase();
300 if (phys_iobase)
301 /* set AR.KR0 since this is all we use it for anyway */
302 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
303 else {
304 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
305 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
306 "to AR.KR0\n");
307 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
308 }
309 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
311 /* setup legacy IO port space */
312 io_space[0].mmio_base = ia64_iobase;
313 io_space[0].sparse = 1;
314 num_io_spaces = 1;
315 }
317 /**
318 * early_console_setup - setup debugging console
319 *
320 * Consoles started here require little enough setup that we can start using
321 * them very early in the boot process, either right after the machine
322 * vector initialization, or even before if the drivers can detect their hw.
323 *
324 * Returns non-zero if a console couldn't be setup.
325 */
326 static inline int __init
327 early_console_setup (char *cmdline)
328 {
329 int earlycons = 0;
331 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
332 {
333 extern int sn_serial_console_early_setup(void);
334 if (!sn_serial_console_early_setup())
335 earlycons++;
336 }
337 #endif
338 #ifdef CONFIG_EFI_PCDP
339 if (!efi_setup_pcdp_console(cmdline))
340 earlycons++;
341 #endif
342 #ifdef CONFIG_SERIAL_8250_CONSOLE
343 if (!early_serial_console_init(cmdline))
344 earlycons++;
345 #endif
347 return (earlycons) ? 0 : -1;
348 }
350 static inline void
351 mark_bsp_online (void)
352 {
353 #ifdef CONFIG_SMP
354 /* If we register an early console, allow CPU 0 to printk */
355 cpu_set(smp_processor_id(), cpu_online_map);
356 #endif
357 }
359 #ifdef CONFIG_SMP
360 static void
361 check_for_logical_procs (void)
362 {
363 pal_logical_to_physical_t info;
364 s64 status;
366 status = ia64_pal_logical_to_phys(0, &info);
367 if (status == -1) {
368 printk(KERN_INFO "No logical to physical processor mapping "
369 "available\n");
370 return;
371 }
372 if (status) {
373 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
374 status);
375 return;
376 }
377 /*
378 * Total number of siblings that BSP has. Though not all of them
379 * may have booted successfully. The correct number of siblings
380 * booted is in info.overview_num_log.
381 */
382 smp_num_siblings = info.overview_tpc;
383 smp_num_cpucores = info.overview_cpp;
384 }
385 #endif
387 void __init
388 #ifdef XEN
389 early_setup_arch (char **cmdline_p)
390 #else
391 setup_arch (char **cmdline_p)
392 #endif
393 {
394 unw_init();
396 #ifndef XEN
397 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
398 #endif
400 *cmdline_p = __va(ia64_boot_param->command_line);
401 #ifndef XEN
402 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
403 #else
404 early_cmdline_parse(cmdline_p);
405 cmdline_parse(*cmdline_p);
406 #endif
408 efi_init();
409 io_port_init();
411 #ifdef CONFIG_IA64_GENERIC
412 {
413 const char *mvec_name = strstr (*cmdline_p, "machvec=");
414 char str[64];
416 if (mvec_name) {
417 const char *end;
418 size_t len;
420 mvec_name += 8;
421 end = strchr (mvec_name, ' ');
422 if (end)
423 len = end - mvec_name;
424 else
425 len = strlen (mvec_name);
426 len = min(len, sizeof (str) - 1);
427 strncpy (str, mvec_name, len);
428 str[len] = '\0';
429 mvec_name = str;
430 } else
431 mvec_name = acpi_get_sysname();
432 machvec_init(mvec_name);
433 }
434 #endif
436 if (early_console_setup(*cmdline_p) == 0)
437 mark_bsp_online();
439 #ifdef XEN
440 }
442 void __init
443 late_setup_arch (char **cmdline_p)
444 {
445 #endif
446 #ifdef CONFIG_ACPI_BOOT
447 /* Initialize the ACPI boot-time table parser */
448 acpi_table_init();
449 # ifdef CONFIG_ACPI_NUMA
450 acpi_numa_init();
451 # endif
452 #else
453 # ifdef CONFIG_SMP
454 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
455 # endif
456 #endif /* CONFIG_APCI_BOOT */
458 #ifndef XEN
459 find_memory();
460 #endif
462 /* process SAL system table: */
463 ia64_sal_init(efi.sal_systab);
465 #ifdef CONFIG_SMP
466 #ifdef XEN
467 init_smp_config ();
468 #endif
470 cpu_physical_id(0) = hard_smp_processor_id();
472 cpu_set(0, cpu_sibling_map[0]);
473 cpu_set(0, cpu_core_map[0]);
475 check_for_logical_procs();
476 if (smp_num_cpucores > 1)
477 printk(KERN_INFO
478 "cpu package is Multi-Core capable: number of cores=%d\n",
479 smp_num_cpucores);
480 if (smp_num_siblings > 1)
481 printk(KERN_INFO
482 "cpu package is Multi-Threading capable: number of siblings=%d\n",
483 smp_num_siblings);
484 #endif
486 #ifdef XEN
487 identify_vmx_feature();
488 #endif
490 cpu_init(); /* initialize the bootstrap CPU */
492 #ifdef CONFIG_ACPI_BOOT
493 acpi_boot_init();
494 #endif
496 #ifdef CONFIG_VT
497 if (!conswitchp) {
498 # if defined(CONFIG_DUMMY_CONSOLE)
499 conswitchp = &dummy_con;
500 # endif
501 # if defined(CONFIG_VGA_CONSOLE)
502 /*
503 * Non-legacy systems may route legacy VGA MMIO range to system
504 * memory. vga_con probes the MMIO hole, so memory looks like
505 * a VGA device to it. The EFI memory map can tell us if it's
506 * memory so we can avoid this problem.
507 */
508 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
509 conswitchp = &vga_con;
510 # endif
511 }
512 #endif
514 /* enable IA-64 Machine Check Abort Handling unless disabled */
515 if (!strstr(saved_command_line, "nomca"))
516 ia64_mca_init();
518 platform_setup(cmdline_p);
519 paging_init();
520 }
522 #ifndef XEN
523 /*
524 * Display cpu info for all cpu's.
525 */
526 static int
527 show_cpuinfo (struct seq_file *m, void *v)
528 {
529 #ifdef CONFIG_SMP
530 # define lpj c->loops_per_jiffy
531 # define cpunum c->cpu
532 #else
533 # define lpj loops_per_jiffy
534 # define cpunum 0
535 #endif
536 static struct {
537 unsigned long mask;
538 const char *feature_name;
539 } feature_bits[] = {
540 { 1UL << 0, "branchlong" },
541 { 1UL << 1, "spontaneous deferral"},
542 { 1UL << 2, "16-byte atomic ops" }
543 };
544 char family[32], features[128], *cp, sep;
545 struct cpuinfo_ia64 *c = v;
546 unsigned long mask;
547 int i;
549 mask = c->features;
551 switch (c->family) {
552 case 0x07: memcpy(family, "Itanium", 8); break;
553 case 0x1f: memcpy(family, "Itanium 2", 10); break;
554 default: sprintf(family, "%u", c->family); break;
555 }
557 /* build the feature string: */
558 memcpy(features, " standard", 10);
559 cp = features;
560 sep = 0;
561 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
562 if (mask & feature_bits[i].mask) {
563 if (sep)
564 *cp++ = sep;
565 sep = ',';
566 *cp++ = ' ';
567 strcpy(cp, feature_bits[i].feature_name);
568 cp += strlen(feature_bits[i].feature_name);
569 mask &= ~feature_bits[i].mask;
570 }
571 }
572 if (mask) {
573 /* print unknown features as a hex value: */
574 if (sep)
575 *cp++ = sep;
576 sprintf(cp, " 0x%lx", mask);
577 }
579 seq_printf(m,
580 "processor : %d\n"
581 "vendor : %s\n"
582 "arch : IA-64\n"
583 "family : %s\n"
584 "model : %u\n"
585 "revision : %u\n"
586 "archrev : %u\n"
587 "features :%s\n" /* don't change this---it _is_ right! */
588 "cpu number : %lu\n"
589 "cpu regs : %u\n"
590 "cpu MHz : %lu.%06lu\n"
591 "itc MHz : %lu.%06lu\n"
592 "BogoMIPS : %lu.%02lu\n",
593 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
594 features, c->ppn, c->number,
595 c->proc_freq / 1000000, c->proc_freq % 1000000,
596 c->itc_freq / 1000000, c->itc_freq % 1000000,
597 lpj*HZ/500000, (lpj*HZ/5000) % 100);
598 #ifdef CONFIG_SMP
599 seq_printf(m, "siblings : %u\n", c->num_log);
600 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
601 seq_printf(m,
602 "physical id: %u\n"
603 "core id : %u\n"
604 "thread id : %u\n",
605 c->socket_id, c->core_id, c->thread_id);
606 #endif
607 seq_printf(m,"\n");
609 return 0;
610 }
612 static void *
613 c_start (struct seq_file *m, loff_t *pos)
614 {
615 #ifdef CONFIG_SMP
616 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
617 ++*pos;
618 #endif
619 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
620 }
622 static void *
623 c_next (struct seq_file *m, void *v, loff_t *pos)
624 {
625 ++*pos;
626 return c_start(m, pos);
627 }
629 static void
630 c_stop (struct seq_file *m, void *v)
631 {
632 }
634 struct seq_operations cpuinfo_op = {
635 .start = c_start,
636 .next = c_next,
637 .stop = c_stop,
638 .show = show_cpuinfo
639 };
640 #endif /* XEN */
642 void
643 identify_cpu (struct cpuinfo_ia64 *c)
644 {
645 union {
646 unsigned long bits[5];
647 struct {
648 /* id 0 & 1: */
649 char vendor[16];
651 /* id 2 */
652 u64 ppn; /* processor serial number */
654 /* id 3: */
655 unsigned number : 8;
656 unsigned revision : 8;
657 unsigned model : 8;
658 unsigned family : 8;
659 unsigned archrev : 8;
660 unsigned reserved : 24;
662 /* id 4: */
663 u64 features;
664 } field;
665 } cpuid;
666 pal_vm_info_1_u_t vm1;
667 pal_vm_info_2_u_t vm2;
668 pal_status_t status;
669 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
670 int i;
672 for (i = 0; i < 5; ++i)
673 cpuid.bits[i] = ia64_get_cpuid(i);
675 memcpy(c->vendor, cpuid.field.vendor, 16);
676 #ifdef CONFIG_SMP
677 c->cpu = smp_processor_id();
679 /* below default values will be overwritten by identify_siblings()
680 * for Multi-Threading/Multi-Core capable cpu's
681 */
682 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
683 c->socket_id = -1;
685 identify_siblings(c);
686 #endif
687 c->ppn = cpuid.field.ppn;
688 c->number = cpuid.field.number;
689 c->revision = cpuid.field.revision;
690 c->model = cpuid.field.model;
691 c->family = cpuid.field.family;
692 c->archrev = cpuid.field.archrev;
693 c->features = cpuid.field.features;
695 status = ia64_pal_vm_summary(&vm1, &vm2);
696 if (status == PAL_STATUS_SUCCESS) {
697 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
698 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
699 }
700 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
701 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
703 #ifdef XEN
704 /* If vmx feature is on, do necessary initialization for vmx */
705 if (vmx_enabled)
706 vmx_init_env();
707 #endif
708 }
710 void
711 setup_per_cpu_areas (void)
712 {
713 /* start_kernel() requires this... */
714 }
716 /*
717 * Calculate the max. cache line size.
718 *
719 * In addition, the minimum of the i-cache stride sizes is calculated for
720 * "flush_icache_range()".
721 */
722 static void
723 get_max_cacheline_size (void)
724 {
725 unsigned long line_size, max = 1;
726 u64 l, levels, unique_caches;
727 pal_cache_config_info_t cci;
728 s64 status;
730 status = ia64_pal_cache_summary(&levels, &unique_caches);
731 if (status != 0) {
732 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
733 __FUNCTION__, status);
734 max = SMP_CACHE_BYTES;
735 /* Safest setup for "flush_icache_range()" */
736 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
737 #ifdef XEN
738 ia64_d_cache_stride_shift = D_CACHE_STRIDE_SHIFT;
739 #endif
740 goto out;
741 }
743 for (l = 0; l < levels; ++l) {
744 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
745 &cci);
746 if (status != 0) {
747 printk(KERN_ERR
748 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
749 __FUNCTION__, l, status);
750 max = SMP_CACHE_BYTES;
751 /* The safest setup for "flush_icache_range()" */
752 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
753 cci.pcci_unified = 1;
754 }
755 #ifdef XEN
756 if (cci.pcci_stride < ia64_d_cache_stride_shift)
757 ia64_d_cache_stride_shift = cci.pcci_stride;
758 #endif
759 line_size = 1 << cci.pcci_line_size;
760 if (line_size > max)
761 max = line_size;
762 if (!cci.pcci_unified) {
763 status = ia64_pal_cache_config_info(l,
764 /* cache_type (instruction)= */ 1,
765 &cci);
766 if (status != 0) {
767 printk(KERN_ERR
768 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
769 __FUNCTION__, l, status);
770 /* The safest setup for "flush_icache_range()" */
771 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
772 }
773 }
774 if (cci.pcci_stride < ia64_i_cache_stride_shift)
775 ia64_i_cache_stride_shift = cci.pcci_stride;
776 }
777 out:
778 if (max > ia64_max_cacheline_size)
779 ia64_max_cacheline_size = max;
780 #ifdef XEN
781 if (ia64_d_cache_stride_shift > ia64_i_cache_stride_shift)
782 ia64_d_cache_stride_shift = ia64_i_cache_stride_shift;
783 #endif
785 }
787 /*
788 * cpu_init() initializes state that is per-CPU. This function acts
789 * as a 'CPU state barrier', nothing should get across.
790 */
791 void
792 cpu_init (void)
793 {
794 extern void __devinit ia64_mmu_init (void *);
795 unsigned long num_phys_stacked;
796 #ifndef XEN
797 pal_vm_info_2_u_t vmi;
798 unsigned int max_ctx;
799 #endif
800 struct cpuinfo_ia64 *cpu_info;
801 void *cpu_data;
803 cpu_data = per_cpu_init();
805 #ifdef XEN
806 printf ("cpu_init: current=%p\n", current);
807 #endif
809 /*
810 * We set ar.k3 so that assembly code in MCA handler can compute
811 * physical addresses of per cpu variables with a simple:
812 * phys = ar.k3 + &per_cpu_var
813 */
814 ia64_set_kr(IA64_KR_PER_CPU_DATA,
815 ia64_tpa(cpu_data) - (long) __per_cpu_start);
817 get_max_cacheline_size();
819 /*
820 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
821 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
822 * depends on the data returned by identify_cpu(). We break the dependency by
823 * accessing cpu_data() through the canonical per-CPU address.
824 */
825 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
826 identify_cpu(cpu_info);
828 #ifdef CONFIG_MCKINLEY
829 {
830 # define FEATURE_SET 16
831 struct ia64_pal_retval iprv;
833 if (cpu_info->family == 0x1f) {
834 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
835 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
836 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
837 (iprv.v1 | 0x80), FEATURE_SET, 0);
838 }
839 }
840 #endif
842 /* Clear the stack memory reserved for pt_regs: */
843 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
845 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
847 /*
848 * Initialize the page-table base register to a global
849 * directory with all zeroes. This ensure that we can handle
850 * TLB-misses to user address-space even before we created the
851 * first user address-space. This may happen, e.g., due to
852 * aggressive use of lfetch.fault.
853 */
854 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
856 /*
857 * Initialize default control register to defer speculative faults except
858 * for those arising from TLB misses, which are not deferred. The
859 * kernel MUST NOT depend on a particular setting of these bits (in other words,
860 * the kernel must have recovery code for all speculative accesses). Turn on
861 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
862 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
863 * be fine).
864 */
865 #ifdef XEN
866 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
867 | IA64_DCR_PP | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
868 #else
869 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
870 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
871 #endif
872 #ifndef XEN
873 atomic_inc(&init_mm.mm_count);
874 current->active_mm = &init_mm;
875 #endif
876 #ifndef XEN
877 if (current->mm)
878 BUG();
879 #endif
882 #ifdef XEN
883 ia64_fph_enable();
884 __ia64_init_fpu();
885 #endif
887 ia64_mmu_init(ia64_imva(cpu_data));
888 ia64_mca_cpu_init(ia64_imva(cpu_data));
890 #ifdef CONFIG_IA32_SUPPORT
891 ia32_cpu_init();
892 #endif
894 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
895 ia64_set_itc(0);
897 /* disable all local interrupt sources: */
898 ia64_set_itv(1 << 16);
899 ia64_set_lrr0(1 << 16);
900 ia64_set_lrr1(1 << 16);
901 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
902 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
904 /* clear TPR & XTP to enable all interrupt classes: */
905 ia64_setreg(_IA64_REG_CR_TPR, 0);
906 #ifdef CONFIG_SMP
907 normal_xtp();
908 #endif
910 #ifndef XEN
911 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
912 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
913 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
914 else {
915 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
916 max_ctx = (1U << 15) - 1; /* use architected minimum */
917 }
918 while (max_ctx < ia64_ctx.max_ctx) {
919 unsigned int old = ia64_ctx.max_ctx;
920 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
921 break;
922 }
923 #endif
925 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
926 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
927 "stacked regs\n");
928 num_phys_stacked = 96;
929 }
930 /* size of physical stacked register partition plus 8 bytes: */
931 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
932 platform_cpu_init();
933 #ifndef XEN
934 pm_idle = default_idle;
935 #endif
937 #ifdef XEN
938 /* surrender usage of kernel registers to domain, use percpu area instead */
939 __get_cpu_var(cpu_kr)._kr[IA64_KR_IO_BASE] = ia64_get_kr(IA64_KR_IO_BASE);
940 __get_cpu_var(cpu_kr)._kr[IA64_KR_PER_CPU_DATA] = ia64_get_kr(IA64_KR_PER_CPU_DATA);
941 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT_STACK] = ia64_get_kr(IA64_KR_CURRENT_STACK);
942 __get_cpu_var(cpu_kr)._kr[IA64_KR_FPU_OWNER] = ia64_get_kr(IA64_KR_FPU_OWNER);
943 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT] = ia64_get_kr(IA64_KR_CURRENT);
944 __get_cpu_var(cpu_kr)._kr[IA64_KR_PT_BASE] = ia64_get_kr(IA64_KR_PT_BASE);
945 #endif
946 }
948 #ifndef XEN
949 void
950 check_bugs (void)
951 {
952 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
953 (unsigned long) __end___mckinley_e9_bundles);
954 }
955 #endif