ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/pci/irq.c @ 5848:50fd1e053b1a

Remove extra definition of DBG in pci/irq.c in XenLinux.
author kaf24@firebug.cl.cam.ac.uk
date Mon Jul 25 20:41:31 2005 +0000 (2005-07-25)
parents 56a63f9f378f
children b53a65034532 1efe6f4163ee e173a853dc46 d4fd332df775 04dfb5158f3a f294acb25858
line source
1 /*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/dmi.h>
16 #include <asm/io.h>
17 #include <asm/smp.h>
18 #include <asm/io_apic.h>
19 #include <asm/hw_irq.h>
20 #include <linux/acpi.h>
22 #include "pci.h"
24 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25 #define PIRQ_VERSION 0x0100
27 static int broken_hp_bios_irq9;
28 static int acer_tm360_irqrouting;
30 static struct irq_routing_table *pirq_table;
32 static int pirq_enable_irq(struct pci_dev *dev);
34 /*
35 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
36 * Avoid using: 13, 14 and 15 (FP error and IDE).
37 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
38 */
39 unsigned int pcibios_irq_mask = 0xfff8;
41 static int pirq_penalty[16] = {
42 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
43 0, 0, 0, 0, 1000, 100000, 100000, 100000
44 };
46 struct irq_router {
47 char *name;
48 u16 vendor, device;
49 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
50 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
51 };
53 struct irq_router_handler {
54 u16 vendor;
55 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
56 };
58 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
60 /*
61 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
62 */
64 static struct irq_routing_table * __init pirq_find_routing_table(void)
65 {
66 u8 *addr;
67 struct irq_routing_table *rt;
68 int i;
69 u8 sum;
71 #ifdef CONFIG_XEN_PRIVILEGED_GUEST
72 for(addr = (u8 *) isa_bus_to_virt(0xf0000); addr < (u8 *) isa_bus_to_virt(0x100000); addr += 16) {
73 rt = (struct irq_routing_table *) addr;
74 if (rt->signature != PIRQ_SIGNATURE ||
75 rt->version != PIRQ_VERSION ||
76 rt->size % 16 ||
77 rt->size < sizeof(struct irq_routing_table))
78 continue;
79 sum = 0;
80 for(i=0; i<rt->size; i++)
81 sum += addr[i];
82 if (!sum) {
83 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
84 return rt;
85 }
86 }
87 #endif
89 return NULL;
90 }
92 /*
93 * If we have a IRQ routing table, use it to search for peer host
94 * bridges. It's a gross hack, but since there are no other known
95 * ways how to get a list of buses, we have to go this way.
96 */
98 static void __init pirq_peer_trick(void)
99 {
100 struct irq_routing_table *rt = pirq_table;
101 u8 busmap[256];
102 int i;
103 struct irq_info *e;
105 memset(busmap, 0, sizeof(busmap));
106 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
107 e = &rt->slots[i];
108 #ifdef DEBUG
109 {
110 int j;
111 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
112 for(j=0; j<4; j++)
113 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
114 DBG("\n");
115 }
116 #endif
117 busmap[e->bus] = 1;
118 }
119 for(i = 1; i < 256; i++) {
120 if (!busmap[i] || pci_find_bus(0, i))
121 continue;
122 if (pci_scan_bus(i, &pci_root_ops, NULL))
123 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
124 }
125 pcibios_last_bus = -1;
126 }
128 /*
129 * Code for querying and setting of IRQ routes on various interrupt routers.
130 */
132 void eisa_set_level_irq(unsigned int irq)
133 {
134 unsigned char mask = 1 << (irq & 7);
135 unsigned int port = 0x4d0 + (irq >> 3);
136 unsigned char val;
137 static u16 eisa_irq_mask;
139 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
140 return;
142 eisa_irq_mask |= (1 << irq);
143 printk("PCI: setting IRQ %u as level-triggered\n", irq);
144 val = inb(port);
145 if (!(val & mask)) {
146 DBG(" -> edge");
147 outb(val | mask, port);
148 }
149 }
151 /*
152 * Common IRQ routing practice: nybbles in config space,
153 * offset by some magic constant.
154 */
155 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
156 {
157 u8 x;
158 unsigned reg = offset + (nr >> 1);
160 pci_read_config_byte(router, reg, &x);
161 return (nr & 1) ? (x >> 4) : (x & 0xf);
162 }
164 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
165 {
166 u8 x;
167 unsigned reg = offset + (nr >> 1);
169 pci_read_config_byte(router, reg, &x);
170 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
171 pci_write_config_byte(router, reg, x);
172 }
174 /*
175 * ALI pirq entries are damn ugly, and completely undocumented.
176 * This has been figured out from pirq tables, and it's not a pretty
177 * picture.
178 */
179 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
180 {
181 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
183 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
184 }
186 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
187 {
188 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
189 unsigned int val = irqmap[irq];
191 if (val) {
192 write_config_nybble(router, 0x48, pirq-1, val);
193 return 1;
194 }
195 return 0;
196 }
198 /*
199 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
200 * just a pointer to the config space.
201 */
202 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
203 {
204 u8 x;
206 pci_read_config_byte(router, pirq, &x);
207 return (x < 16) ? x : 0;
208 }
210 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
211 {
212 pci_write_config_byte(router, pirq, irq);
213 return 1;
214 }
216 /*
217 * The VIA pirq rules are nibble-based, like ALI,
218 * but without the ugly irq number munging.
219 * However, PIRQD is in the upper instead of lower 4 bits.
220 */
221 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
222 {
223 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
224 }
226 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
227 {
228 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
229 return 1;
230 }
232 /*
233 * ITE 8330G pirq rules are nibble-based
234 * FIXME: pirqmap may be { 1, 0, 3, 2 },
235 * 2+3 are both mapped to irq 9 on my system
236 */
237 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
238 {
239 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
240 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
241 }
243 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
244 {
245 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
246 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
247 return 1;
248 }
250 /*
251 * OPTI: high four bits are nibble pointer..
252 * I wonder what the low bits do?
253 */
254 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
255 {
256 return read_config_nybble(router, 0xb8, pirq >> 4);
257 }
259 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
260 {
261 write_config_nybble(router, 0xb8, pirq >> 4, irq);
262 return 1;
263 }
265 /*
266 * Cyrix: nibble offset 0x5C
267 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
268 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
269 */
270 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
271 {
272 return read_config_nybble(router, 0x5C, (pirq-1)^1);
273 }
275 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
276 {
277 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
278 return 1;
279 }
281 /*
282 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
283 * We have to deal with the following issues here:
284 * - vendors have different ideas about the meaning of link values
285 * - some onboard devices (integrated in the chipset) have special
286 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
287 * - different revision of the router have a different layout for
288 * the routing registers, particularly for the onchip devices
289 *
290 * For all routing registers the common thing is we have one byte
291 * per routeable link which is defined as:
292 * bit 7 IRQ mapping enabled (0) or disabled (1)
293 * bits [6:4] reserved (sometimes used for onchip devices)
294 * bits [3:0] IRQ to map to
295 * allowed: 3-7, 9-12, 14-15
296 * reserved: 0, 1, 2, 8, 13
297 *
298 * The config-space registers located at 0x41/0x42/0x43/0x44 are
299 * always used to route the normal PCI INT A/B/C/D respectively.
300 * Apparently there are systems implementing PCI routing table using
301 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
302 * We try our best to handle both link mappings.
303 *
304 * Currently (2003-05-21) it appears most SiS chipsets follow the
305 * definition of routing registers from the SiS-5595 southbridge.
306 * According to the SiS 5595 datasheets the revision id's of the
307 * router (ISA-bridge) should be 0x01 or 0xb0.
308 *
309 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
310 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
311 * They seem to work with the current routing code. However there is
312 * some concern because of the two USB-OHCI HCs (original SiS 5595
313 * had only one). YMMV.
314 *
315 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
316 *
317 * 0x61: IDEIRQ:
318 * bits [6:5] must be written 01
319 * bit 4 channel-select primary (0), secondary (1)
320 *
321 * 0x62: USBIRQ:
322 * bit 6 OHCI function disabled (0), enabled (1)
323 *
324 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
325 *
326 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
327 *
328 * We support USBIRQ (in addition to INTA-INTD) and keep the
329 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
330 *
331 * Currently the only reported exception is the new SiS 65x chipset
332 * which includes the SiS 69x southbridge. Here we have the 85C503
333 * router revision 0x04 and there are changes in the register layout
334 * mostly related to the different USB HCs with USB 2.0 support.
335 *
336 * Onchip routing for router rev-id 0x04 (try-and-error observation)
337 *
338 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
339 * bit 6-4 are probably unused, not like 5595
340 */
342 #define PIRQ_SIS_IRQ_MASK 0x0f
343 #define PIRQ_SIS_IRQ_DISABLE 0x80
344 #define PIRQ_SIS_USB_ENABLE 0x40
346 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
347 {
348 u8 x;
349 int reg;
351 reg = pirq;
352 if (reg >= 0x01 && reg <= 0x04)
353 reg += 0x40;
354 pci_read_config_byte(router, reg, &x);
355 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
356 }
358 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
359 {
360 u8 x;
361 int reg;
363 reg = pirq;
364 if (reg >= 0x01 && reg <= 0x04)
365 reg += 0x40;
366 pci_read_config_byte(router, reg, &x);
367 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
368 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
369 pci_write_config_byte(router, reg, x);
370 return 1;
371 }
374 /*
375 * VLSI: nibble offset 0x74 - educated guess due to routing table and
376 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
377 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
378 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
379 * for the busbridge to the docking station.
380 */
382 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
383 {
384 if (pirq > 8) {
385 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
386 return 0;
387 }
388 return read_config_nybble(router, 0x74, pirq-1);
389 }
391 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
392 {
393 if (pirq > 8) {
394 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
395 return 0;
396 }
397 write_config_nybble(router, 0x74, pirq-1, irq);
398 return 1;
399 }
401 /*
402 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
403 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
404 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
405 * register is a straight binary coding of desired PIC IRQ (low nibble).
406 *
407 * The 'link' value in the PIRQ table is already in the correct format
408 * for the Index register. There are some special index values:
409 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
410 * and 0x03 for SMBus.
411 */
412 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
413 {
414 outb_p(pirq, 0xc00);
415 return inb(0xc01) & 0xf;
416 }
418 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
419 {
420 outb_p(pirq, 0xc00);
421 outb_p(irq, 0xc01);
422 return 1;
423 }
425 /* Support for AMD756 PCI IRQ Routing
426 * Jhon H. Caicedo <jhcaiced@osso.org.co>
427 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
428 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
429 * The AMD756 pirq rules are nibble-based
430 * offset 0x56 0-3 PIRQA 4-7 PIRQB
431 * offset 0x57 0-3 PIRQC 4-7 PIRQD
432 */
433 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
434 {
435 u8 irq;
436 irq = 0;
437 if (pirq <= 4)
438 {
439 irq = read_config_nybble(router, 0x56, pirq - 1);
440 }
441 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
442 dev->vendor, dev->device, pirq, irq);
443 return irq;
444 }
446 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
447 {
448 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
449 dev->vendor, dev->device, pirq, irq);
450 if (pirq <= 4)
451 {
452 write_config_nybble(router, 0x56, pirq - 1, irq);
453 }
454 return 1;
455 }
457 #ifdef CONFIG_PCI_BIOS
459 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
460 {
461 struct pci_dev *bridge;
462 int pin = pci_get_interrupt_pin(dev, &bridge);
463 return pcibios_set_irq_routing(bridge, pin, irq);
464 }
466 #endif
468 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
469 {
470 static struct pci_device_id pirq_440gx[] = {
471 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
472 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
473 { },
474 };
476 /* 440GX has a proprietary PIRQ router -- don't use it */
477 if (pci_dev_present(pirq_440gx))
478 return 0;
480 switch(device)
481 {
482 case PCI_DEVICE_ID_INTEL_82371FB_0:
483 case PCI_DEVICE_ID_INTEL_82371SB_0:
484 case PCI_DEVICE_ID_INTEL_82371AB_0:
485 case PCI_DEVICE_ID_INTEL_82371MX:
486 case PCI_DEVICE_ID_INTEL_82443MX_0:
487 case PCI_DEVICE_ID_INTEL_82801AA_0:
488 case PCI_DEVICE_ID_INTEL_82801AB_0:
489 case PCI_DEVICE_ID_INTEL_82801BA_0:
490 case PCI_DEVICE_ID_INTEL_82801BA_10:
491 case PCI_DEVICE_ID_INTEL_82801CA_0:
492 case PCI_DEVICE_ID_INTEL_82801CA_12:
493 case PCI_DEVICE_ID_INTEL_82801DB_0:
494 case PCI_DEVICE_ID_INTEL_82801E_0:
495 case PCI_DEVICE_ID_INTEL_82801EB_0:
496 case PCI_DEVICE_ID_INTEL_ESB_1:
497 case PCI_DEVICE_ID_INTEL_ICH6_0:
498 case PCI_DEVICE_ID_INTEL_ICH6_1:
499 case PCI_DEVICE_ID_INTEL_ICH7_0:
500 case PCI_DEVICE_ID_INTEL_ICH7_1:
501 case PCI_DEVICE_ID_INTEL_ICH7_30:
502 case PCI_DEVICE_ID_INTEL_ICH7_31:
503 case PCI_DEVICE_ID_INTEL_ESB2_0:
504 r->name = "PIIX/ICH";
505 r->get = pirq_piix_get;
506 r->set = pirq_piix_set;
507 return 1;
508 }
509 return 0;
510 }
512 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
513 {
514 /* FIXME: We should move some of the quirk fixup stuff here */
515 switch(device)
516 {
517 case PCI_DEVICE_ID_VIA_82C586_0:
518 case PCI_DEVICE_ID_VIA_82C596:
519 case PCI_DEVICE_ID_VIA_82C686:
520 case PCI_DEVICE_ID_VIA_8231:
521 /* FIXME: add new ones for 8233/5 */
522 r->name = "VIA";
523 r->get = pirq_via_get;
524 r->set = pirq_via_set;
525 return 1;
526 }
527 return 0;
528 }
530 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
531 {
532 switch(device)
533 {
534 case PCI_DEVICE_ID_VLSI_82C534:
535 r->name = "VLSI 82C534";
536 r->get = pirq_vlsi_get;
537 r->set = pirq_vlsi_set;
538 return 1;
539 }
540 return 0;
541 }
544 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
545 {
546 switch(device)
547 {
548 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
549 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
550 r->name = "ServerWorks";
551 r->get = pirq_serverworks_get;
552 r->set = pirq_serverworks_set;
553 return 1;
554 }
555 return 0;
556 }
558 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
559 {
560 if (device != PCI_DEVICE_ID_SI_503)
561 return 0;
563 r->name = "SIS";
564 r->get = pirq_sis_get;
565 r->set = pirq_sis_set;
566 return 1;
567 }
569 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
570 {
571 switch(device)
572 {
573 case PCI_DEVICE_ID_CYRIX_5520:
574 r->name = "NatSemi";
575 r->get = pirq_cyrix_get;
576 r->set = pirq_cyrix_set;
577 return 1;
578 }
579 return 0;
580 }
582 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
583 {
584 switch(device)
585 {
586 case PCI_DEVICE_ID_OPTI_82C700:
587 r->name = "OPTI";
588 r->get = pirq_opti_get;
589 r->set = pirq_opti_set;
590 return 1;
591 }
592 return 0;
593 }
595 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
596 {
597 switch(device)
598 {
599 case PCI_DEVICE_ID_ITE_IT8330G_0:
600 r->name = "ITE";
601 r->get = pirq_ite_get;
602 r->set = pirq_ite_set;
603 return 1;
604 }
605 return 0;
606 }
608 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
609 {
610 switch(device)
611 {
612 case PCI_DEVICE_ID_AL_M1533:
613 case PCI_DEVICE_ID_AL_M1563:
614 printk("PCI: Using ALI IRQ Router\n");
615 r->name = "ALI";
616 r->get = pirq_ali_get;
617 r->set = pirq_ali_set;
618 return 1;
619 }
620 return 0;
621 }
623 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
624 {
625 switch(device)
626 {
627 case PCI_DEVICE_ID_AMD_VIPER_740B:
628 r->name = "AMD756";
629 break;
630 case PCI_DEVICE_ID_AMD_VIPER_7413:
631 r->name = "AMD766";
632 break;
633 case PCI_DEVICE_ID_AMD_VIPER_7443:
634 r->name = "AMD768";
635 break;
636 default:
637 return 0;
638 }
639 r->get = pirq_amd756_get;
640 r->set = pirq_amd756_set;
641 return 1;
642 }
644 static __initdata struct irq_router_handler pirq_routers[] = {
645 { PCI_VENDOR_ID_INTEL, intel_router_probe },
646 { PCI_VENDOR_ID_AL, ali_router_probe },
647 { PCI_VENDOR_ID_ITE, ite_router_probe },
648 { PCI_VENDOR_ID_VIA, via_router_probe },
649 { PCI_VENDOR_ID_OPTI, opti_router_probe },
650 { PCI_VENDOR_ID_SI, sis_router_probe },
651 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
652 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
653 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
654 { PCI_VENDOR_ID_AMD, amd_router_probe },
655 /* Someone with docs needs to add the ATI Radeon IGP */
656 { 0, NULL }
657 };
658 static struct irq_router pirq_router;
659 static struct pci_dev *pirq_router_dev;
662 /*
663 * FIXME: should we have an option to say "generic for
664 * chipset" ?
665 */
667 static void __init pirq_find_router(struct irq_router *r)
668 {
669 struct irq_routing_table *rt = pirq_table;
670 struct irq_router_handler *h;
672 #ifdef CONFIG_PCI_BIOS
673 if (!rt->signature) {
674 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
675 r->set = pirq_bios_set;
676 r->name = "BIOS";
677 return;
678 }
679 #endif
681 /* Default unless a driver reloads it */
682 r->name = "default";
683 r->get = NULL;
684 r->set = NULL;
686 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
687 rt->rtr_vendor, rt->rtr_device);
689 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
690 if (!pirq_router_dev) {
691 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
692 return;
693 }
695 for( h = pirq_routers; h->vendor; h++) {
696 /* First look for a router match */
697 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
698 break;
699 /* Fall back to a device match */
700 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
701 break;
702 }
703 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
704 pirq_router.name,
705 pirq_router_dev->vendor,
706 pirq_router_dev->device,
707 pci_name(pirq_router_dev));
708 }
710 static struct irq_info *pirq_get_info(struct pci_dev *dev)
711 {
712 struct irq_routing_table *rt = pirq_table;
713 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
714 struct irq_info *info;
716 for (info = rt->slots; entries--; info++)
717 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
718 return info;
719 return NULL;
720 }
722 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
723 {
724 u8 pin;
725 struct irq_info *info;
726 int i, pirq, newirq;
727 int irq = 0;
728 u32 mask;
729 struct irq_router *r = &pirq_router;
730 struct pci_dev *dev2 = NULL;
731 char *msg = NULL;
733 /* Find IRQ pin */
734 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
735 if (!pin) {
736 DBG(" -> no interrupt pin\n");
737 return 0;
738 }
739 pin = pin - 1;
741 /* Find IRQ routing entry */
743 if (!pirq_table)
744 return 0;
746 DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin);
747 info = pirq_get_info(dev);
748 if (!info) {
749 DBG(" -> not found in routing table\n");
750 return 0;
751 }
752 pirq = info->irq[pin].link;
753 mask = info->irq[pin].bitmap;
754 if (!pirq) {
755 DBG(" -> not routed\n");
756 return 0;
757 }
758 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
759 mask &= pcibios_irq_mask;
761 /* Work around broken HP Pavilion Notebooks which assign USB to
762 IRQ 9 even though it is actually wired to IRQ 11 */
764 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
765 dev->irq = 11;
766 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
767 r->set(pirq_router_dev, dev, pirq, 11);
768 }
770 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
771 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
772 pirq = 0x68;
773 mask = 0x400;
774 dev->irq = r->get(pirq_router_dev, dev, pirq);
775 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
776 }
778 /*
779 * Find the best IRQ to assign: use the one
780 * reported by the device if possible.
781 */
782 newirq = dev->irq;
783 if (!((1 << newirq) & mask)) {
784 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
785 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
786 }
787 if (!newirq && assign) {
788 for (i = 0; i < 16; i++) {
789 if (!(mask & (1 << i)))
790 continue;
791 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
792 newirq = i;
793 }
794 }
795 DBG(" -> newirq=%d", newirq);
797 /* Check if it is hardcoded */
798 if ((pirq & 0xf0) == 0xf0) {
799 irq = pirq & 0xf;
800 DBG(" -> hardcoded IRQ %d\n", irq);
801 msg = "Hardcoded";
802 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
803 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
804 DBG(" -> got IRQ %d\n", irq);
805 msg = "Found";
806 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
807 DBG(" -> assigning IRQ %d", newirq);
808 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
809 eisa_set_level_irq(newirq);
810 DBG(" ... OK\n");
811 msg = "Assigned";
812 irq = newirq;
813 }
814 }
816 if (!irq) {
817 DBG(" ... failed\n");
818 if (newirq && mask == (1 << newirq)) {
819 msg = "Guessed";
820 irq = newirq;
821 } else
822 return 0;
823 }
824 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
826 /* Update IRQ for all devices with the same pirq value */
827 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
828 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
829 if (!pin)
830 continue;
831 pin--;
832 info = pirq_get_info(dev2);
833 if (!info)
834 continue;
835 if (info->irq[pin].link == pirq) {
836 /* We refuse to override the dev->irq information. Give a warning! */
837 if ( dev2->irq && dev2->irq != irq && \
838 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
839 ((1 << dev2->irq) & mask)) ) {
840 #ifndef CONFIG_PCI_MSI
841 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
842 pci_name(dev2), dev2->irq, irq);
843 #endif
844 continue;
845 }
846 dev2->irq = irq;
847 pirq_penalty[irq]++;
848 if (dev != dev2)
849 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
850 }
851 }
852 return 1;
853 }
855 static void __init pcibios_fixup_irqs(void)
856 {
857 struct pci_dev *dev = NULL;
858 u8 pin;
860 DBG("PCI: IRQ fixup\n");
861 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
862 /*
863 * If the BIOS has set an out of range IRQ number, just ignore it.
864 * Also keep track of which IRQ's are already in use.
865 */
866 if (dev->irq >= 16) {
867 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
868 dev->irq = 0;
869 }
870 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
871 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
872 pirq_penalty[dev->irq] = 0;
873 pirq_penalty[dev->irq]++;
874 }
876 dev = NULL;
877 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
878 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
879 #ifdef CONFIG_X86_IO_APIC
880 /*
881 * Recalculate IRQ numbers if we use the I/O APIC.
882 */
883 if (io_apic_assign_pci_irqs)
884 {
885 int irq;
887 if (pin) {
888 pin--; /* interrupt pins are numbered starting from 1 */
889 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
890 /*
891 * Busses behind bridges are typically not listed in the MP-table.
892 * In this case we have to look up the IRQ based on the parent bus,
893 * parent slot, and pin number. The SMP code detects such bridged
894 * busses itself so we should get into this branch reliably.
895 */
896 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
897 struct pci_dev * bridge = dev->bus->self;
899 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
900 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
901 PCI_SLOT(bridge->devfn), pin);
902 if (irq >= 0)
903 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
904 pci_name(bridge), 'A' + pin, irq);
905 }
906 if (irq >= 0) {
907 if (use_pci_vector() &&
908 !platform_legacy_irq(irq))
909 irq = IO_APIC_VECTOR(irq);
911 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
912 pci_name(dev), 'A' + pin, irq);
913 dev->irq = irq;
914 }
915 }
916 }
917 #endif
918 /*
919 * Still no IRQ? Try to lookup one...
920 */
921 if (pin && !dev->irq)
922 pcibios_lookup_irq(dev, 0);
923 }
924 }
926 /*
927 * Work around broken HP Pavilion Notebooks which assign USB to
928 * IRQ 9 even though it is actually wired to IRQ 11
929 */
930 static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
931 {
932 if (!broken_hp_bios_irq9) {
933 broken_hp_bios_irq9 = 1;
934 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
935 }
936 return 0;
937 }
939 /*
940 * Work around broken Acer TravelMate 360 Notebooks which assign
941 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
942 */
943 static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
944 {
945 if (!acer_tm360_irqrouting) {
946 acer_tm360_irqrouting = 1;
947 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
948 }
949 return 0;
950 }
952 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
953 {
954 .callback = fix_broken_hp_bios_irq9,
955 .ident = "HP Pavilion N5400 Series Laptop",
956 .matches = {
957 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
958 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
959 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
960 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
961 },
962 },
963 {
964 .callback = fix_acer_tm360_irqrouting,
965 .ident = "Acer TravelMate 36x Laptop",
966 .matches = {
967 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
968 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
969 },
970 },
971 { }
972 };
974 static int __init pcibios_irq_init(void)
975 {
976 DBG("PCI: IRQ init\n");
978 if (pcibios_enable_irq || raw_pci_ops == NULL)
979 return 0;
981 dmi_check_system(pciirq_dmi_table);
983 pirq_table = pirq_find_routing_table();
985 #ifdef CONFIG_PCI_BIOS
986 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
987 pirq_table = pcibios_get_irq_routing_table();
988 #endif
989 if (pirq_table) {
990 pirq_peer_trick();
991 pirq_find_router(&pirq_router);
992 if (pirq_table->exclusive_irqs) {
993 int i;
994 for (i=0; i<16; i++)
995 if (!(pirq_table->exclusive_irqs & (1 << i)))
996 pirq_penalty[i] += 100;
997 }
998 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
999 if (io_apic_assign_pci_irqs)
1000 pirq_table = NULL;
1003 pcibios_enable_irq = pirq_enable_irq;
1005 pcibios_fixup_irqs();
1006 return 0;
1009 subsys_initcall(pcibios_irq_init);
1012 static void pirq_penalize_isa_irq(int irq)
1014 /*
1015 * If any ISAPnP device reports an IRQ in its list of possible
1016 * IRQ's, we try to avoid assigning it to PCI devices.
1017 */
1018 if (irq < 16)
1019 pirq_penalty[irq] += 100;
1022 void pcibios_penalize_isa_irq(int irq)
1024 #ifdef CONFIG_ACPI_PCI
1025 if (!acpi_noirq)
1026 acpi_penalize_isa_irq(irq);
1027 else
1028 #endif
1029 pirq_penalize_isa_irq(irq);
1032 static int pirq_enable_irq(struct pci_dev *dev)
1034 u8 pin;
1035 struct pci_dev *temp_dev;
1037 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1038 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1039 char *msg = "";
1041 pin--; /* interrupt pins are numbered starting from 1 */
1043 if (io_apic_assign_pci_irqs) {
1044 int irq;
1046 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1047 /*
1048 * Busses behind bridges are typically not listed in the MP-table.
1049 * In this case we have to look up the IRQ based on the parent bus,
1050 * parent slot, and pin number. The SMP code detects such bridged
1051 * busses itself so we should get into this branch reliably.
1052 */
1053 temp_dev = dev;
1054 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1055 struct pci_dev * bridge = dev->bus->self;
1057 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1058 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1059 PCI_SLOT(bridge->devfn), pin);
1060 if (irq >= 0)
1061 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1062 pci_name(bridge), 'A' + pin, irq);
1063 dev = bridge;
1065 dev = temp_dev;
1066 if (irq >= 0) {
1067 #ifdef CONFIG_PCI_MSI
1068 if (!platform_legacy_irq(irq))
1069 irq = IO_APIC_VECTOR(irq);
1070 #endif
1071 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1072 pci_name(dev), 'A' + pin, irq);
1073 dev->irq = irq;
1074 return 0;
1075 } else
1076 msg = " Probably buggy MP table.";
1077 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1078 msg = "";
1079 else
1080 msg = " Please try using pci=biosirq.";
1082 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1083 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1084 return 0;
1086 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1087 'A' + pin, pci_name(dev), msg);
1089 return 0;
1092 int pci_vector_resources(int last, int nr_released)
1094 int count = nr_released;
1096 int next = last;
1097 int offset = (last % 8);
1099 while (next < FIRST_SYSTEM_VECTOR) {
1100 next += 8;
1101 #ifdef CONFIG_X86_64
1102 if (next == IA32_SYSCALL_VECTOR)
1103 continue;
1104 #else
1105 if (next == SYSCALL_VECTOR)
1106 continue;
1107 #endif
1108 count++;
1109 if (next >= FIRST_SYSTEM_VECTOR) {
1110 if (offset%8) {
1111 next = FIRST_DEVICE_VECTOR + offset;
1112 offset++;
1113 continue;
1115 count--;
1119 return count;