ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-i386/mach-xen/asm/pgtable-3level.h @ 14019:4b9680c58d73

linux/x86: Clean up page table handling headers

- remove dead code
- fix line breaking and space vs. tab usage
- remove redundant parentheses

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author kfraser@localhost.localdomain
date Tue Feb 20 09:41:32 2007 +0000 (2007-02-20)
parents d2dff286994d
children 14c25e48a557
line source
1 #ifndef _I386_PGTABLE_3LEVEL_H
2 #define _I386_PGTABLE_3LEVEL_H
4 #include <asm-generic/pgtable-nopud.h>
6 /*
7 * Intel Physical Address Extension (PAE) Mode - three-level page
8 * tables on PPro+ CPUs.
9 *
10 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
11 */
13 #define pte_ERROR(e) \
14 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15 #define pmd_ERROR(e) \
16 printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
17 #define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
20 #define pud_none(pud) 0
21 #define pud_bad(pud) 0
22 #define pud_present(pud) 1
24 /*
25 * Is the pte executable?
26 */
27 static inline int pte_x(pte_t pte)
28 {
29 return !(pte_val(pte) & _PAGE_NX);
30 }
32 /*
33 * All present user-pages with !NX bit are user-executable:
34 */
35 static inline int pte_exec(pte_t pte)
36 {
37 return pte_user(pte) && pte_x(pte);
38 }
39 /*
40 * All present pages with !NX bit are kernel-executable:
41 */
42 static inline int pte_exec_kernel(pte_t pte)
43 {
44 return pte_x(pte);
45 }
47 /* Rules for using set_pte: the pte being assigned *must* be
48 * either not present or in a state where the hardware will
49 * not attempt to update the pte. In places where this is
50 * not possible, use pte_get_and_clear to obtain the old pte
51 * value and then use set_pte to update it. -ben
52 */
53 #define __HAVE_ARCH_SET_PTE_ATOMIC
55 static inline void set_pte(pte_t *ptep, pte_t pte)
56 {
57 ptep->pte_high = pte.pte_high;
58 smp_wmb();
59 ptep->pte_low = pte.pte_low;
60 }
61 #define set_pte_atomic(pteptr,pteval) \
62 set_64bit((unsigned long long *)(pteptr),pte_val_ma(pteval))
64 #define set_pte_at(_mm,addr,ptep,pteval) do { \
65 if (((_mm) != current->mm && (_mm) != &init_mm) || \
66 HYPERVISOR_update_va_mapping((addr), (pteval), 0)) \
67 set_pte((ptep), (pteval)); \
68 } while (0)
70 #define set_pte_at_sync(_mm,addr,ptep,pteval) do { \
71 if (((_mm) != current->mm && (_mm) != &init_mm) || \
72 HYPERVISOR_update_va_mapping((addr), (pteval), UVMF_INVLPG)) { \
73 set_pte((ptep), (pteval)); \
74 xen_invlpg((addr)); \
75 } \
76 } while (0)
78 #define set_pmd(pmdptr,pmdval) \
79 xen_l2_entry_update((pmdptr), (pmdval))
80 #define set_pud(pudptr,pudval) \
81 xen_l3_entry_update((pudptr), (pudval))
83 /*
84 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
85 * the TLB via cr3 if the top-level pgd is changed...
86 * We do not let the generic code free and clear pgd entries due to
87 * this erratum.
88 */
89 static inline void pud_clear (pud_t * pud) { }
91 #define pud_page(pud) \
92 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
94 #define pud_page_kernel(pud) \
95 ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
98 /* Find an entry in the second-level page table.. */
99 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
100 pmd_index(address))
102 /*
103 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
104 * entry, so clear the bottom half first and enforce ordering with a compiler
105 * barrier.
106 */
107 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
108 {
109 ptep->pte_low = 0;
110 smp_wmb();
111 ptep->pte_high = 0;
112 }
114 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
116 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
117 {
118 pte_t res;
120 /* xchg acts as a barrier before the setting of the high bits */
121 res.pte_low = xchg(&ptep->pte_low, 0);
122 res.pte_high = ptep->pte_high;
123 ptep->pte_high = 0;
125 return res;
126 }
128 static inline int pte_same(pte_t a, pte_t b)
129 {
130 return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
131 }
133 #define pte_page(x) pfn_to_page(pte_pfn(x))
135 static inline int pte_none(pte_t pte)
136 {
137 return !pte.pte_low && !pte.pte_high;
138 }
140 #define __pte_mfn(_pte) (((_pte).pte_low >> PAGE_SHIFT) | \
141 ((_pte).pte_high << (32-PAGE_SHIFT)))
142 #define pte_mfn(_pte) ((_pte).pte_low & _PAGE_PRESENT ? \
143 __pte_mfn(_pte) : pfn_to_mfn(__pte_mfn(_pte)))
144 #define pte_pfn(_pte) ((_pte).pte_low & _PAGE_PRESENT ? \
145 mfn_to_local_pfn(__pte_mfn(_pte)) : __pte_mfn(_pte))
147 extern unsigned long long __supported_pte_mask;
149 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
150 {
151 return __pte((((unsigned long long)page_nr << PAGE_SHIFT) |
152 pgprot_val(pgprot)) & __supported_pte_mask);
153 }
155 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
156 {
157 return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) |
158 pgprot_val(pgprot)) & __supported_pte_mask);
159 }
161 /*
162 * Bits 0, 6 and 7 are taken in the low part of the pte,
163 * put the 32 bits of offset into the high part.
164 */
165 #define pte_to_pgoff(pte) ((pte).pte_high)
166 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
167 #define PTE_FILE_MAX_BITS 32
169 /* Encode and de-code a swap entry */
170 #define __swp_type(x) (((x).val) & 0x1f)
171 #define __swp_offset(x) ((x).val >> 5)
172 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
173 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
174 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
176 #define __pmd_free_tlb(tlb, x) do { } while (0)
178 void vmalloc_sync_all(void);
180 #endif /* _I386_PGTABLE_3LEVEL_H */