ia64/xen-unstable

view xenolinux-2.4.16-sparse/include/asm-xeno/hypervisor.h @ 86:4a10fe9b20ec

bitkeeper revision 1.15 (3e24a984iRiWWcgfKCxu2p5q3YbxXw)

Many files:
First half of support for per-domain GDTs and LDTs
author kaf24@labyrinth.cl.cam.ac.uk
date Wed Jan 15 00:21:24 2003 +0000 (2003-01-15)
parents af2f305e6020
children b0d356ed774b 73643659824d
line source
1 /******************************************************************************
2 * hypervisor.h
3 *
4 * Linux-specific hypervisor handling.
5 *
6 * Copyright (c) 2002, K A Fraser
7 */
9 #ifndef __HYPERVISOR_H__
10 #define __HYPERVISOR_H__
12 #include <asm/hypervisor-ifs/hypervisor-if.h>
13 #include <asm/ptrace.h>
15 /* arch/xeno/kernel/setup.c */
16 union start_info_union
17 {
18 start_info_t start_info;
19 char padding[512];
20 };
21 extern union start_info_union start_info_union;
22 #define start_info (start_info_union.start_info)
24 /* arch/xeno/kernel/hypervisor.c */
25 void do_hypervisor_callback(struct pt_regs *regs);
28 /* arch/xeno/mm/hypervisor.c */
29 /*
30 * NB. ptr values should be fake-physical. 'vals' should be already
31 * fully adjusted (ie. for start_info.phys_base).
32 */
34 extern unsigned int pt_update_queue_idx;
36 void queue_l1_entry_update(unsigned long ptr, unsigned long val);
37 void queue_l2_entry_update(unsigned long ptr, unsigned long val);
38 void queue_pt_switch(unsigned long ptr);
39 void queue_tlb_flush(void);
40 void queue_invlpg(unsigned long ptr);
41 void queue_pgd_pin(unsigned long ptr);
42 void queue_pgd_unpin(unsigned long ptr);
43 void queue_pte_pin(unsigned long ptr);
44 void queue_pte_unpin(unsigned long ptr);
46 #define PT_UPDATE_DEBUG 0
48 #if PT_UPDATE_DEBUG > 0
49 typedef struct {
50 unsigned long ptr, val, pteval;
51 void *ptep;
52 int line; char *file;
53 } page_update_debug_t;
54 extern page_update_debug_t update_debug_queue[];
55 #define queue_l1_entry_update(_p,_v) ({ \
56 update_debug_queue[pt_update_queue_idx].ptr = (_p); \
57 update_debug_queue[pt_update_queue_idx].val = (_v); \
58 update_debug_queue[pt_update_queue_idx].line = __LINE__; \
59 update_debug_queue[pt_update_queue_idx].file = __FILE__; \
60 queue_l1_entry_update((_p),(_v)); \
61 })
62 #define queue_l2_entry_update(_p,_v) ({ \
63 update_debug_queue[pt_update_queue_idx].ptr = (_p); \
64 update_debug_queue[pt_update_queue_idx].val = (_v); \
65 update_debug_queue[pt_update_queue_idx].line = __LINE__; \
66 update_debug_queue[pt_update_queue_idx].file = __FILE__; \
67 queue_l2_entry_update((_p),(_v)); \
68 })
69 #endif
71 #if PT_UPDATE_DEBUG > 1
72 #undef queue_l1_entry_update
73 #undef queue_l2_entry_update
74 #define queue_l1_entry_update(_p,_v) ({ \
75 update_debug_queue[pt_update_queue_idx].ptr = (_p); \
76 update_debug_queue[pt_update_queue_idx].val = (_v); \
77 update_debug_queue[pt_update_queue_idx].line = __LINE__; \
78 update_debug_queue[pt_update_queue_idx].file = __FILE__; \
79 printk("L1 %s %d: %08lx (%08lx -> %08lx)\n", __FILE__, __LINE__, \
80 (_p)+start_info.phys_base, *(unsigned long *)__va(_p), \
81 (unsigned long)(_v)); \
82 queue_l1_entry_update((_p),(_v)); \
83 })
84 #define queue_l2_entry_update(_p,_v) ({ \
85 update_debug_queue[pt_update_queue_idx].ptr = (_p); \
86 update_debug_queue[pt_update_queue_idx].val = (_v); \
87 update_debug_queue[pt_update_queue_idx].line = __LINE__; \
88 update_debug_queue[pt_update_queue_idx].file = __FILE__; \
89 printk("L2 %s %d: %08lx (%08lx -> %08lx)\n", __FILE__, __LINE__, \
90 (_p)+start_info.phys_base, *(unsigned long *)__va(_p), \
91 (unsigned long)(_v)); \
92 queue_l2_entry_update((_p),(_v)); \
93 })
94 #define queue_pt_switch(_p) ({ \
95 printk("PTSWITCH %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
96 queue_pt_switch(_p); \
97 })
98 #define queue_tlb_flush() ({ \
99 printk("TLB FLUSH %s %d\n", __FILE__, __LINE__); \
100 queue_tlb_flush(); \
101 })
102 #define queue_invlpg(_p) ({ \
103 printk("INVLPG %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
104 queue_invlpg(_p); \
105 })
106 #define queue_pgd_pin(_p) ({ \
107 printk("PGD PIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
108 queue_pgd_pin(_p); \
109 })
110 #define queue_pgd_unpin(_p) ({ \
111 printk("PGD UNPIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
112 queue_pgd_unpin(_p); \
113 })
114 #define queue_pte_pin(_p) ({ \
115 printk("PTE PIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
116 queue_pte_pin(_p); \
117 })
118 #define queue_pte_unpin(_p) ({ \
119 printk("PTE UNPIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
120 queue_pte_unpin(_p); \
121 })
122 #endif
124 void _flush_page_update_queue(void);
125 static inline int flush_page_update_queue(void)
126 {
127 unsigned int idx = pt_update_queue_idx;
128 if ( idx != 0 ) _flush_page_update_queue();
129 return idx;
130 }
131 #define XENO_flush_page_update_queue() (_flush_page_update_queue())
134 /*
135 * Assembler stubs for hyper-calls.
136 */
138 static inline int HYPERVISOR_set_trap_table(trap_info_t *table)
139 {
140 int ret;
141 __asm__ __volatile__ (
142 TRAP_INSTR
143 : "=a" (ret) : "0" (__HYPERVISOR_set_trap_table),
144 "b" (table) );
146 return ret;
147 }
150 static inline int HYPERVISOR_pt_update(page_update_request_t *req, int count)
151 {
152 int ret;
153 __asm__ __volatile__ (
154 TRAP_INSTR
155 : "=a" (ret) : "0" (__HYPERVISOR_pt_update),
156 "b" (req), "c" (count) );
158 return ret;
159 }
162 static inline int HYPERVISOR_console_write(const char *str, int count)
163 {
164 int ret;
165 __asm__ __volatile__ (
166 TRAP_INSTR
167 : "=a" (ret) : "0" (__HYPERVISOR_console_write),
168 "b" (str), "c" (count) );
171 return ret;
172 }
174 static inline int HYPERVISOR_set_gdt(unsigned long *frame_list, int entries)
175 {
176 int ret;
177 __asm__ __volatile__ (
178 TRAP_INSTR
179 : "=a" (ret) : "0" (__HYPERVISOR_set_gdt),
180 "b" (frame_list), "c" (entries) );
183 return ret;
184 }
186 static inline int HYPERVISOR_stack_and_ldt_switch(
187 unsigned long ss, unsigned long esp, unsigned long ldts)
188 {
189 int ret;
190 __asm__ __volatile__ (
191 TRAP_INSTR
192 : "=a" (ret) : "0" (__HYPERVISOR_stack_and_ldt_switch),
193 "b" (ss), "c" (esp), "d" (ldts) );
195 return ret;
196 }
198 static inline int HYPERVISOR_net_update(void)
199 {
200 int ret;
201 __asm__ __volatile__ (
202 TRAP_INSTR
203 : "=a" (ret) : "0" (__HYPERVISOR_net_update) );
205 return ret;
206 }
208 static inline int HYPERVISOR_fpu_taskswitch(void)
209 {
210 int ret;
211 __asm__ __volatile__ (
212 TRAP_INSTR
213 : "=a" (ret) : "0" (__HYPERVISOR_fpu_taskswitch) );
215 return ret;
216 }
218 static inline int HYPERVISOR_yield(void)
219 {
220 int ret;
221 __asm__ __volatile__ (
222 TRAP_INSTR
223 : "=a" (ret) : "0" (__HYPERVISOR_yield) );
225 return ret;
226 }
228 static inline int HYPERVISOR_exit(void)
229 {
230 int ret;
231 __asm__ __volatile__ (
232 TRAP_INSTR
233 : "=a" (ret) : "0" (__HYPERVISOR_exit) );
235 return ret;
236 }
238 static inline int HYPERVISOR_dom0_op(void *dom0_op)
239 {
240 int ret;
241 __asm__ __volatile__ (
242 TRAP_INSTR
243 : "=a" (ret) : "0" (__HYPERVISOR_dom0_op),
244 "b" (dom0_op) : "memory" );
246 return ret;
247 }
249 static inline int HYPERVISOR_network_op(void *network_op)
250 {
251 int ret;
252 __asm__ __volatile__ (
253 TRAP_INSTR
254 : "=a" (ret) : "0" (__HYPERVISOR_network_op),
255 "b" (network_op) );
257 return ret;
258 }
260 static inline int HYPERVISOR_set_debugreg(int reg, unsigned long value)
261 {
262 int ret;
263 __asm__ __volatile__ (
264 TRAP_INSTR
265 : "=a" (ret) : "0" (__HYPERVISOR_set_debugreg),
266 "b" (reg), "c" (value) );
268 return ret;
269 }
271 static inline unsigned long HYPERVISOR_get_debugreg(int reg)
272 {
273 unsigned long ret;
274 __asm__ __volatile__ (
275 TRAP_INSTR
276 : "=a" (ret) : "0" (__HYPERVISOR_get_debugreg),
277 "b" (reg) );
279 return ret;
280 }
282 static inline int HYPERVISOR_update_descriptor(
283 unsigned long pa, unsigned long word1, unsigned long word2)
284 {
285 int ret;
286 __asm__ __volatile__ (
287 TRAP_INSTR
288 : "=a" (ret) : "0" (__HYPERVISOR_set_gdt),
289 "b" (pa), "c" (word1), "d" (word2) );
292 return ret;
293 }
295 #endif /* __HYPERVISOR_H__ */