ia64/xen-unstable

view xen-2.4.16/include/asm-i386/processor.h @ 86:4a10fe9b20ec

bitkeeper revision 1.15 (3e24a984iRiWWcgfKCxu2p5q3YbxXw)

Many files:
First half of support for per-domain GDTs and LDTs
author kaf24@labyrinth.cl.cam.ac.uk
date Wed Jan 15 00:21:24 2003 +0000 (2003-01-15)
parents 1ef2026299c3
children 88c1cf85fc8f 2f78322be16a
line source
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/page.h>
11 #include <asm/types.h>
12 #include <asm/cpufeature.h>
13 #include <xeno/config.h>
14 #include <hypervisor-ifs/hypervisor-if.h>
17 /*
18 * Default implementation of macro that returns current
19 * instruction pointer ("program counter").
20 */
21 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
23 /*
24 * CPU type and hardware bug flags. Kept separately for each CPU.
25 * Members of this structure are referenced in head.S, so think twice
26 * before touching them. [mj]
27 */
29 struct cpuinfo_x86 {
30 __u8 x86; /* CPU family */
31 __u8 x86_vendor; /* CPU vendor */
32 __u8 x86_model;
33 __u8 x86_mask;
34 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
35 __u32 x86_capability[NCAPINTS];
36 char x86_vendor_id[16];
37 unsigned long *pgd_quick;
38 unsigned long *pmd_quick;
39 unsigned long *pte_quick;
40 unsigned long pgtable_cache_sz;
41 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
43 #define X86_VENDOR_INTEL 0
44 #define X86_VENDOR_CYRIX 1
45 #define X86_VENDOR_AMD 2
46 #define X86_VENDOR_UMC 3
47 #define X86_VENDOR_NEXGEN 4
48 #define X86_VENDOR_CENTAUR 5
49 #define X86_VENDOR_RISE 6
50 #define X86_VENDOR_TRANSMETA 7
51 #define X86_VENDOR_UNKNOWN 0xff
53 /*
54 * capabilities of CPUs
55 */
57 extern struct cpuinfo_x86 boot_cpu_data;
58 extern struct tss_struct init_tss[NR_CPUS];
60 #ifdef CONFIG_SMP
61 extern struct cpuinfo_x86 cpu_data[];
62 #define current_cpu_data cpu_data[smp_processor_id()]
63 #else
64 #define cpu_data (&boot_cpu_data)
65 #define current_cpu_data boot_cpu_data
66 #endif
68 #define cpu_has_pge (test_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability))
69 #define cpu_has_pse (test_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability))
70 #define cpu_has_pae (test_bit(X86_FEATURE_PAE, boot_cpu_data.x86_capability))
71 #define cpu_has_tsc (test_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability))
72 #define cpu_has_de (test_bit(X86_FEATURE_DE, boot_cpu_data.x86_capability))
73 #define cpu_has_vme (test_bit(X86_FEATURE_VME, boot_cpu_data.x86_capability))
74 #define cpu_has_fxsr (test_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability))
75 #define cpu_has_xmm (test_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability))
76 #define cpu_has_fpu (test_bit(X86_FEATURE_FPU, boot_cpu_data.x86_capability))
77 #define cpu_has_apic (test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability))
79 extern void identify_cpu(struct cpuinfo_x86 *);
80 extern void print_cpu_info(struct cpuinfo_x86 *);
81 extern void dodgy_tsc(void);
83 /*
84 * EFLAGS bits
85 */
86 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
87 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
88 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
89 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
90 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
91 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
92 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
93 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
94 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
95 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
96 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
97 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
98 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
99 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
100 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
101 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
102 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
104 /*
105 * Generic CPUID function
106 */
107 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
108 {
109 __asm__("cpuid"
110 : "=a" (*eax),
111 "=b" (*ebx),
112 "=c" (*ecx),
113 "=d" (*edx)
114 : "0" (op));
115 }
117 /*
118 * CPUID functions returning a single datum
119 */
120 static inline unsigned int cpuid_eax(unsigned int op)
121 {
122 unsigned int eax;
124 __asm__("cpuid"
125 : "=a" (eax)
126 : "0" (op)
127 : "bx", "cx", "dx");
128 return eax;
129 }
130 static inline unsigned int cpuid_ebx(unsigned int op)
131 {
132 unsigned int eax, ebx;
134 __asm__("cpuid"
135 : "=a" (eax), "=b" (ebx)
136 : "0" (op)
137 : "cx", "dx" );
138 return ebx;
139 }
140 static inline unsigned int cpuid_ecx(unsigned int op)
141 {
142 unsigned int eax, ecx;
144 __asm__("cpuid"
145 : "=a" (eax), "=c" (ecx)
146 : "0" (op)
147 : "bx", "dx" );
148 return ecx;
149 }
150 static inline unsigned int cpuid_edx(unsigned int op)
151 {
152 unsigned int eax, edx;
154 __asm__("cpuid"
155 : "=a" (eax), "=d" (edx)
156 : "0" (op)
157 : "bx", "cx");
158 return edx;
159 }
161 /*
162 * Intel CPU features in CR4
163 */
164 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
165 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
166 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
167 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
168 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
169 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
170 #define X86_CR4_MCE 0x0040 /* Machine check enable */
171 #define X86_CR4_PGE 0x0080 /* enable global pages */
172 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
173 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
174 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
176 /*
177 * Save the cr4 feature set we're using (ie
178 * Pentium 4MB enable and PPro Global page
179 * enable), so that any CPU's that boot up
180 * after us can get the correct flags.
181 */
182 extern unsigned long mmu_cr4_features;
184 static inline void set_in_cr4 (unsigned long mask)
185 {
186 mmu_cr4_features |= mask;
187 __asm__("movl %%cr4,%%eax\n\t"
188 "orl %0,%%eax\n\t"
189 "movl %%eax,%%cr4\n"
190 : : "irg" (mask)
191 :"ax");
192 }
194 static inline void clear_in_cr4 (unsigned long mask)
195 {
196 mmu_cr4_features &= ~mask;
197 __asm__("movl %%cr4,%%eax\n\t"
198 "andl %0,%%eax\n\t"
199 "movl %%eax,%%cr4\n"
200 : : "irg" (~mask)
201 :"ax");
202 }
204 /*
205 * Cyrix CPU configuration register indexes
206 */
207 #define CX86_CCR0 0xc0
208 #define CX86_CCR1 0xc1
209 #define CX86_CCR2 0xc2
210 #define CX86_CCR3 0xc3
211 #define CX86_CCR4 0xe8
212 #define CX86_CCR5 0xe9
213 #define CX86_CCR6 0xea
214 #define CX86_CCR7 0xeb
215 #define CX86_DIR0 0xfe
216 #define CX86_DIR1 0xff
217 #define CX86_ARR_BASE 0xc4
218 #define CX86_RCR_BASE 0xdc
220 /*
221 * Cyrix CPU indexed register access macros
222 */
224 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
226 #define setCx86(reg, data) do { \
227 outb((reg), 0x22); \
228 outb((data), 0x23); \
229 } while (0)
231 #define EISA_bus (0)
232 #define MCA_bus (0)
234 /* from system description table in BIOS. Mostly for MCA use, but
235 others may find it useful. */
236 extern unsigned int machine_id;
237 extern unsigned int machine_submodel_id;
238 extern unsigned int BIOS_revision;
239 extern unsigned int mca_pentium_flag;
241 /*
242 * User space process size: 3GB (default).
243 */
244 #define TASK_SIZE (PAGE_OFFSET)
246 /* This decides where the kernel will search for a free chunk of vm
247 * space during mmap's.
248 */
249 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
251 /*
252 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
253 */
254 #define IO_BITMAP_SIZE 32
255 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
256 #define INVALID_IO_BITMAP_OFFSET 0x8000
258 struct i387_fsave_struct {
259 long cwd;
260 long swd;
261 long twd;
262 long fip;
263 long fcs;
264 long foo;
265 long fos;
266 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
267 long status; /* software status information */
268 };
270 struct i387_fxsave_struct {
271 unsigned short cwd;
272 unsigned short swd;
273 unsigned short twd;
274 unsigned short fop;
275 long fip;
276 long fcs;
277 long foo;
278 long fos;
279 long mxcsr;
280 long reserved;
281 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
282 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
283 long padding[56];
284 } __attribute__ ((aligned (16)));
286 struct i387_soft_struct {
287 long cwd;
288 long swd;
289 long twd;
290 long fip;
291 long fcs;
292 long foo;
293 long fos;
294 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
295 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
296 struct info *info;
297 unsigned long entry_eip;
298 };
300 union i387_union {
301 struct i387_fsave_struct fsave;
302 struct i387_fxsave_struct fxsave;
303 struct i387_soft_struct soft;
304 };
306 typedef struct {
307 unsigned long seg;
308 } mm_segment_t;
310 struct tss_struct {
311 unsigned short back_link,__blh;
312 unsigned long esp0;
313 unsigned short ss0,__ss0h;
314 unsigned long esp1;
315 unsigned short ss1,__ss1h;
316 unsigned long esp2;
317 unsigned short ss2,__ss2h;
318 unsigned long __cr3;
319 unsigned long eip;
320 unsigned long eflags;
321 unsigned long eax,ecx,edx,ebx;
322 unsigned long esp;
323 unsigned long ebp;
324 unsigned long esi;
325 unsigned long edi;
326 unsigned short es, __esh;
327 unsigned short cs, __csh;
328 unsigned short ss, __ssh;
329 unsigned short ds, __dsh;
330 unsigned short fs, __fsh;
331 unsigned short gs, __gsh;
332 unsigned short ldt, __ldth;
333 unsigned short trace, bitmap;
334 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
335 /*
336 * pads the TSS to be cacheline-aligned (size is 0x100)
337 */
338 unsigned long __cacheline_filler[5];
339 };
341 struct thread_struct {
342 unsigned long esp0; /* top of the stack */
343 unsigned long eip; /* in kernel space, saved on task switch */
344 unsigned long esp; /* "" */
345 unsigned long fs; /* "" (NB. DS/ES constant in mon, so no save) */
346 unsigned long gs; /* "" ("") */
347 unsigned long esp1, ss1;
348 /* Hardware debugging registers */
349 unsigned long debugreg[8]; /* %%db0-7 debug registers */
350 /* fault info */
351 unsigned long cr2, trap_no, error_code;
352 /* floating point info */
353 union i387_union i387;
354 /* Trap info. */
355 trap_info_t traps[256];
356 };
358 #define INIT_THREAD { \
359 sizeof(idle0_stack) + (long) &idle0_stack, /* esp0 */ \
360 0, 0, 0, 0, 0, 0, \
361 { [0 ... 7] = 0 }, /* debugging registers */ \
362 0, 0, 0, \
363 { { 0, }, }, /* 387 state */ \
364 { {0} } /* io permissions */ \
365 }
367 #define INIT_TSS { \
368 0,0, /* back_link, __blh */ \
369 sizeof(idle0_stack) + (long) &idle0_stack, /* esp0 */ \
370 __HYPERVISOR_DS, 0, /* ss0 */ \
371 0,0,0,0,0,0, /* stack1, stack2 */ \
372 0, /* cr3 */ \
373 0,0, /* eip,eflags */ \
374 0,0,0,0, /* eax,ecx,edx,ebx */ \
375 0,0,0,0, /* esp,ebp,esi,edi */ \
376 0,0,0,0,0,0, /* es,cs,ss */ \
377 0,0,0,0,0,0, /* ds,fs,gs */ \
378 0,0, /* ldt */ \
379 0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */ \
380 {~0, } /* ioperm */ \
381 }
383 #define start_thread(regs, new_eip, new_esp) do { \
384 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
385 set_fs(USER_DS); \
386 regs->xds = __USER_DS; \
387 regs->xes = __USER_DS; \
388 regs->xss = __USER_DS; \
389 regs->xcs = __USER_CS; \
390 regs->eip = new_eip; \
391 regs->esp = new_esp; \
392 } while (0)
394 /* Forward declaration, a strange C thing */
395 struct task_struct;
396 struct mm_struct;
398 /* Free all resources held by a thread. */
399 extern void release_thread(struct task_struct *);
400 /*
401 * create a kernel thread without removing it from tasklists
402 */
403 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
405 /* Copy and release all segment info associated with a VM */
406 extern void copy_segments(struct task_struct *p, struct mm_struct * mm);
407 extern void release_segments(struct mm_struct * mm);
409 /*
410 * Return saved PC of a blocked thread.
411 */
412 static inline unsigned long thread_saved_pc(struct thread_struct *t)
413 {
414 return ((unsigned long *)t->esp)[3];
415 }
417 unsigned long get_wchan(struct task_struct *p);
418 #define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
419 #define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
421 #define THREAD_SIZE (2*PAGE_SIZE)
422 #define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
423 #define free_task_struct(p) free_pages((unsigned long) (p), 1)
424 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
426 #define idle0_task (idle0_task_union.task)
427 #define idle0_stack (idle0_task_union.stack)
429 struct microcode {
430 unsigned int hdrver;
431 unsigned int rev;
432 unsigned int date;
433 unsigned int sig;
434 unsigned int cksum;
435 unsigned int ldrver;
436 unsigned int pf;
437 unsigned int reserved[5];
438 unsigned int bits[500];
439 };
441 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
442 #define MICROCODE_IOCFREE _IO('6',0)
444 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
445 static inline void rep_nop(void)
446 {
447 __asm__ __volatile__("rep;nop");
448 }
450 #define cpu_relax() rep_nop()
452 /* Prefetch instructions for Pentium III and AMD Athlon */
453 #ifdef CONFIG_MPENTIUMIII
455 #define ARCH_HAS_PREFETCH
456 extern inline void prefetch(const void *x)
457 {
458 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
459 }
461 #elif CONFIG_X86_USE_3DNOW
463 #define ARCH_HAS_PREFETCH
464 #define ARCH_HAS_PREFETCHW
465 #define ARCH_HAS_SPINLOCK_PREFETCH
467 extern inline void prefetch(const void *x)
468 {
469 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
470 }
472 extern inline void prefetchw(const void *x)
473 {
474 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
475 }
476 #define spin_lock_prefetch(x) prefetchw(x)
478 #endif
480 #endif /* __ASM_I386_PROCESSOR_H */