ia64/xen-unstable

view xen-2.4.16/arch/i386/setup.c @ 86:4a10fe9b20ec

bitkeeper revision 1.15 (3e24a984iRiWWcgfKCxu2p5q3YbxXw)

Many files:
First half of support for per-domain GDTs and LDTs
author kaf24@labyrinth.cl.cam.ac.uk
date Wed Jan 15 00:21:24 2003 +0000 (2003-01-15)
parents c3e6a52cd801
children b0d356ed774b 2868f9ebcc69
line source
2 #include <xeno/config.h>
3 #include <xeno/init.h>
4 #include <xeno/interrupt.h>
5 #include <xeno/lib.h>
6 #include <xeno/sched.h>
7 #include <xeno/pci.h>
8 #include <asm/bitops.h>
9 #include <asm/smp.h>
10 #include <asm/processor.h>
11 #include <asm/mpspec.h>
12 #include <asm/apic.h>
13 #include <asm/desc.h>
14 #include <asm/domain_page.h>
16 struct cpuinfo_x86 boot_cpu_data = { 0 };
17 /* Lots of nice things, since we only target PPro+. */
18 unsigned long mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE;
19 unsigned long wait_init_idle;
21 /* Basic page table for each CPU in the system. */
22 l2_pgentry_t *idle_pg_table[NR_CPUS] = { idle0_pg_table };
24 /* for asm/domain_page.h, map_domain_page() */
25 unsigned long *mapcache[NR_CPUS];
27 /* Standard macro to see if a specific flag is changeable */
28 static inline int flag_is_changeable_p(u32 flag)
29 {
30 u32 f1, f2;
32 asm("pushfl\n\t"
33 "pushfl\n\t"
34 "popl %0\n\t"
35 "movl %0,%1\n\t"
36 "xorl %2,%0\n\t"
37 "pushl %0\n\t"
38 "popfl\n\t"
39 "pushfl\n\t"
40 "popl %0\n\t"
41 "popfl\n\t"
42 : "=&r" (f1), "=&r" (f2)
43 : "ir" (flag));
45 return ((f1^f2) & flag) != 0;
46 }
48 /* Probe for the CPUID instruction */
49 static int __init have_cpuid_p(void)
50 {
51 return flag_is_changeable_p(X86_EFLAGS_ID);
52 }
54 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
55 {
56 char *v = c->x86_vendor_id;
58 if (!strcmp(v, "GenuineIntel"))
59 c->x86_vendor = X86_VENDOR_INTEL;
60 else if (!strcmp(v, "AuthenticAMD"))
61 c->x86_vendor = X86_VENDOR_AMD;
62 else if (!strcmp(v, "CyrixInstead"))
63 c->x86_vendor = X86_VENDOR_CYRIX;
64 else if (!strcmp(v, "UMC UMC UMC "))
65 c->x86_vendor = X86_VENDOR_UMC;
66 else if (!strcmp(v, "CentaurHauls"))
67 c->x86_vendor = X86_VENDOR_CENTAUR;
68 else if (!strcmp(v, "NexGenDriven"))
69 c->x86_vendor = X86_VENDOR_NEXGEN;
70 else if (!strcmp(v, "RiseRiseRise"))
71 c->x86_vendor = X86_VENDOR_RISE;
72 else if (!strcmp(v, "GenuineTMx86") ||
73 !strcmp(v, "TransmetaCPU"))
74 c->x86_vendor = X86_VENDOR_TRANSMETA;
75 else
76 c->x86_vendor = X86_VENDOR_UNKNOWN;
77 }
79 static void __init init_intel(struct cpuinfo_x86 *c)
80 {
81 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it */
82 if ( c->x86 == 6 && c->x86_model < 3 && c->x86_mask < 3 )
83 clear_bit(X86_FEATURE_SEP, &c->x86_capability);
84 }
86 static void __init init_amd(struct cpuinfo_x86 *c)
87 {
88 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
89 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
90 clear_bit(0*32+31, &c->x86_capability);
92 switch(c->x86)
93 {
94 case 5:
95 panic("AMD K6 is not supported.\n");
96 case 6: /* An Athlon/Duron. We can trust the BIOS probably */
97 break;
98 }
99 }
101 /*
102 * This does the hard work of actually picking apart the CPU stuff...
103 */
104 void __init identify_cpu(struct cpuinfo_x86 *c)
105 {
106 int junk, i;
107 u32 xlvl, tfms;
109 c->x86_vendor = X86_VENDOR_UNKNOWN;
110 c->cpuid_level = -1; /* CPUID not detected */
111 c->x86_model = c->x86_mask = 0; /* So far unknown... */
112 c->x86_vendor_id[0] = '\0'; /* Unset */
113 memset(&c->x86_capability, 0, sizeof c->x86_capability);
115 if ( !have_cpuid_p() )
116 panic("Ancient processors not supported\n");
118 /* Get vendor name */
119 cpuid(0x00000000, &c->cpuid_level,
120 (int *)&c->x86_vendor_id[0],
121 (int *)&c->x86_vendor_id[8],
122 (int *)&c->x86_vendor_id[4]);
124 get_cpu_vendor(c);
126 if ( c->cpuid_level == 0 )
127 panic("Decrepit CPUID not supported\n");
129 cpuid(0x00000001, &tfms, &junk, &junk,
130 &c->x86_capability[0]);
131 c->x86 = (tfms >> 8) & 15;
132 c->x86_model = (tfms >> 4) & 15;
133 c->x86_mask = tfms & 15;
135 /* AMD-defined flags: level 0x80000001 */
136 xlvl = cpuid_eax(0x80000000);
137 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
138 if ( xlvl >= 0x80000001 )
139 c->x86_capability[1] = cpuid_edx(0x80000001);
140 }
142 /* Transmeta-defined flags: level 0x80860001 */
143 xlvl = cpuid_eax(0x80860000);
144 if ( (xlvl & 0xffff0000) == 0x80860000 ) {
145 if ( xlvl >= 0x80860001 )
146 c->x86_capability[2] = cpuid_edx(0x80860001);
147 }
149 printk("CPU: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
150 c->x86_capability[0],
151 c->x86_capability[1],
152 c->x86_capability[2],
153 c->x86_vendor);
155 switch ( c->x86_vendor ) {
156 case X86_VENDOR_INTEL:
157 init_intel(c);
158 break;
159 case X86_VENDOR_AMD:
160 init_amd(c);
161 break;
162 default:
163 panic("Only support Intel processors (P6+)\n");
164 }
166 printk("CPU caps: %08x %08x %08x %08x\n",
167 c->x86_capability[0],
168 c->x86_capability[1],
169 c->x86_capability[2],
170 c->x86_capability[3]);
172 /*
173 * On SMP, boot_cpu_data holds the common feature set between
174 * all CPUs; so make sure that we indicate which features are
175 * common between the CPUs. The first time this routine gets
176 * executed, c == &boot_cpu_data.
177 */
178 if ( c != &boot_cpu_data ) {
179 /* AND the already accumulated flags with these */
180 for ( i = 0 ; i < NCAPINTS ; i++ )
181 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
182 }
183 }
186 unsigned long cpu_initialized;
187 void __init cpu_init(void)
188 {
189 int nr = smp_processor_id();
190 struct tss_struct * t = &init_tss[nr];
191 l2_pgentry_t *pl2e;
193 if ( test_and_set_bit(nr, &cpu_initialized) )
194 panic("CPU#%d already initialized!!!\n", nr);
195 printk("Initializing CPU#%d\n", nr);
197 /* Set up GDT and IDT. */
198 SET_GDT_ENTRIES(current, DEFAULT_GDT_ENTRIES);
199 SET_GDT_ADDRESS(current, DEFAULT_GDT_ADDRESS);
200 __asm__ __volatile__("lgdt %0": "=m" (*current->mm.gdt));
201 __asm__ __volatile__("lidt %0": "=m" (idt_descr));
203 /* No nested task. */
204 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
206 /* Ensure FPU gets initialised for each domain. */
207 stts();
209 /* Set up and load the per-CPU TSS and LDT. */
210 t->ss0 = __HYPERVISOR_DS;
211 t->esp0 = current->thread.esp0;
212 set_tss_desc(nr,t);
213 load_TR(nr);
214 __asm__ __volatile__("lldt %%ax"::"a" (0));
216 /* Clear all 6 debug registers. */
217 #define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
218 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
219 #undef CD
221 /* Install correct page table. */
222 __asm__ __volatile__ ("movl %%eax,%%cr3"
223 : : "a" (pagetable_val(current->mm.pagetable)));
225 /* Set up mapping cache for domain pages. */
226 pl2e = idle_pg_table[nr] + (MAPCACHE_VIRT_START >> L2_PAGETABLE_SHIFT);
227 mapcache[nr] = (unsigned long *)get_free_page(GFP_KERNEL);
228 clear_page(mapcache[nr]);
229 *pl2e = mk_l2_pgentry(__pa(mapcache[nr]) | PAGE_HYPERVISOR);
231 /* Stick the idle task on the run queue. */
232 (void)wake_up(current);
233 }
235 static void __init do_initcalls(void)
236 {
237 initcall_t *call;
239 call = &__initcall_start;
240 do {
241 (*call)();
242 call++;
243 } while (call < &__initcall_end);
244 }
246 /*
247 * IBM-compatible BIOSes place drive info tables at initial interrupt
248 * vectors 0x41 and 0x46. These are in the for of 16-bit-mode far ptrs.
249 */
250 struct drive_info_struct { unsigned char dummy[32]; } drive_info;
251 void get_bios_driveinfo(void)
252 {
253 unsigned long seg, off, tab1, tab2;
255 off = (unsigned long)*(unsigned short *)(4*0x41+0);
256 seg = (unsigned long)*(unsigned short *)(4*0x41+2);
257 tab1 = (seg<<4) + off;
259 off = (unsigned long)*(unsigned short *)(4*0x46+0);
260 seg = (unsigned long)*(unsigned short *)(4*0x46+2);
261 tab2 = (seg<<4) + off;
263 printk("Reading BIOS drive-info tables at 0x%05lx and 0x%05lx\n",
264 tab1, tab2);
266 memcpy(drive_info.dummy+ 0, (char *)tab1, 16);
267 memcpy(drive_info.dummy+16, (char *)tab2, 16);
268 }
271 unsigned long pci_mem_start = 0x10000000;
273 void __init start_of_day(void)
274 {
275 extern void trap_init(void);
276 extern void init_IRQ(void);
277 extern void time_init(void);
278 extern void softirq_init(void);
279 extern void timer_bh(void);
280 extern void tqueue_bh(void);
281 extern void immediate_bh(void);
282 extern void init_timervecs(void);
283 extern int setup_network_devices(void);
284 extern void net_init(void);
286 unsigned long low_mem_size;
288 /*
289 * We do this early, but tables are in the lowest 1MB (usually
290 * 0xfe000-0xfffff). Therefore they're unlikely to ever get clobbered.
291 */
292 get_bios_driveinfo();
294 /* Tell the PCI layer not to allocate too close to the RAM area.. */
295 low_mem_size = ((max_page << PAGE_SHIFT) + 0xfffff) & ~0xfffff;
296 if ( low_mem_size > pci_mem_start ) pci_mem_start = low_mem_size;
298 identify_cpu(&boot_cpu_data); /* get CPU type info */
299 if ( cpu_has_fxsr ) set_in_cr4(X86_CR4_OSFXSR);
300 if ( cpu_has_xmm ) set_in_cr4(X86_CR4_OSXMMEXCPT);
301 find_smp_config(); /* find ACPI tables */
302 smp_alloc_memory(); /* trampoline which other CPUs jump at */
303 paging_init(); /* not much here now, but sets up fixmap */
304 if ( smp_found_config ) get_smp_config();
305 domain_init();
306 trap_init();
307 init_IRQ(); /* installs simple interrupt wrappers. Starts HZ clock. */
308 time_init(); /* installs software handler for HZ clock. */
309 softirq_init();
310 init_timervecs();
311 init_bh(TIMER_BH, timer_bh);
312 init_bh(TQUEUE_BH, tqueue_bh);
313 init_bh(IMMEDIATE_BH, immediate_bh);
314 init_apic_mappings(); /* make APICs addressable in our pagetables. */
316 #ifndef CONFIG_SMP
317 APIC_init_uniprocessor();
318 #else
319 smp_boot_cpus(); /*
320 * Does loads of stuff, including kicking the local
321 * APIC, and the IO APIC after other CPUs are booted.
322 * Each IRQ is preferably handled by IO-APIC, but
323 * fall thru to 8259A if we have to (but slower).
324 */
325 #endif
327 sti();
329 zap_low_mappings();
330 kmem_cache_init();
331 kmem_cache_sizes_init(max_page);
332 #ifdef CONFIG_PCI
333 pci_init();
334 #endif
335 do_initcalls();
336 if ( !setup_network_devices() )
337 panic("Must have a network device!\n");
338 net_init(); /* initializes virtual network system. */
340 #ifdef CONFIG_SMP
341 wait_init_idle = cpu_online_map;
342 clear_bit(smp_processor_id(), &wait_init_idle);
343 smp_threads_ready = 1;
344 smp_commence(); /* Tell other CPUs that state of the world is stable. */
345 while (wait_init_idle)
346 {
347 cpu_relax();
348 barrier();
349 }
350 #endif
351 }