ia64/xen-unstable

view xen/arch/x86/io_apic.c @ 19706:49e8816db57a

x86: pin_2_irq[].pin should be initialised to -1.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jun 03 12:35:25 2009 +0100 (2009-06-03)
parents 6705898f768d
children
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/init.h>
26 #include <xen/irq.h>
27 #include <xen/delay.h>
28 #include <xen/sched.h>
29 #include <xen/acpi.h>
30 #include <xen/pci.h>
31 #include <xen/pci_regs.h>
32 #include <xen/keyhandler.h>
33 #include <asm/io.h>
34 #include <asm/mc146818rtc.h>
35 #include <asm/smp.h>
36 #include <asm/desc.h>
37 #include <asm/msi.h>
38 #include <mach_apic.h>
39 #include <io_ports.h>
40 #include <public/physdev.h>
42 /* Different to Linux: our implementation can be simpler. */
43 #define make_8259A_irq(irq) (io_apic_irqs &= ~(1<<(irq)))
45 int (*ioapic_renumber_irq)(int ioapic, int irq);
46 atomic_t irq_mis_count;
48 /* Where if anywhere is the i8259 connect in external int mode */
49 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
51 static DEFINE_SPINLOCK(ioapic_lock);
53 int skip_ioapic_setup;
55 #ifndef sis_apic_bug
56 /*
57 * Is the SiS APIC rmw bug present?
58 * -1 = don't know, 0 = no, 1 = yes
59 */
60 int sis_apic_bug = -1;
61 #endif
63 /*
64 * # of IRQ routing registers
65 */
66 int nr_ioapic_registers[MAX_IO_APICS];
68 int disable_timer_pin_1 __initdata;
70 /*
71 * Rough estimation of how many shared IRQs there are, can
72 * be changed anytime.
73 */
74 #define MAX_PLUS_SHARED_IRQS nr_irqs
75 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + nr_irqs)
77 /*
78 * This is performance-critical, we want to do it O(1)
79 *
80 * the indexing order of this array favors 1:1 mappings
81 * between pins and IRQs.
82 */
84 static struct irq_pin_list {
85 int apic, pin;
86 unsigned int next;
87 } *irq_2_pin;
88 static unsigned int irq_2_pin_free_entry;
90 /*
91 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
92 * shared ISA-space IRQs, so we have to support them. We are super
93 * fast in the common case, and fast for shared ISA-space IRQs.
94 */
95 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
96 {
97 struct irq_pin_list *entry = irq_2_pin + irq;
99 while (entry->next) {
100 BUG_ON((entry->apic == apic) && (entry->pin == pin));
101 entry = irq_2_pin + entry->next;
102 }
104 BUG_ON((entry->apic == apic) && (entry->pin == pin));
106 if (entry->pin != -1) {
107 if (irq_2_pin_free_entry >= PIN_MAP_SIZE)
108 panic("io_apic.c: whoops");
109 entry->next = irq_2_pin_free_entry;
110 entry = irq_2_pin + entry->next;
111 irq_2_pin_free_entry = entry->next;
112 entry->next = 0;
113 }
114 entry->apic = apic;
115 entry->pin = pin;
116 }
118 static void remove_pin_at_irq(unsigned int irq, int apic, int pin)
119 {
120 struct irq_pin_list *entry, *prev;
122 for (entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next]) {
123 if ((entry->apic == apic) && (entry->pin == pin))
124 break;
125 if (!entry->next)
126 BUG();
127 }
129 entry->pin = entry->apic = -1;
131 if (entry != &irq_2_pin[irq]) {
132 /* Removed entry is not at head of list. */
133 prev = &irq_2_pin[irq];
134 while (&irq_2_pin[prev->next] != entry)
135 prev = &irq_2_pin[prev->next];
136 prev->next = entry->next;
137 entry->next = irq_2_pin_free_entry;
138 irq_2_pin_free_entry = entry - irq_2_pin;
139 } else if (entry->next != 0) {
140 /* Removed entry is at head of multi-item list. */
141 prev = entry;
142 entry = &irq_2_pin[entry->next];
143 *prev = *entry;
144 entry->pin = entry->apic = -1;
145 entry->next = irq_2_pin_free_entry;
146 irq_2_pin_free_entry = entry - irq_2_pin;
147 }
148 }
150 /*
151 * Reroute an IRQ to a different pin.
152 */
153 static void __init replace_pin_at_irq(unsigned int irq,
154 int oldapic, int oldpin,
155 int newapic, int newpin)
156 {
157 struct irq_pin_list *entry = irq_2_pin + irq;
159 while (1) {
160 if (entry->apic == oldapic && entry->pin == oldpin) {
161 entry->apic = newapic;
162 entry->pin = newpin;
163 }
164 if (!entry->next)
165 break;
166 entry = irq_2_pin + entry->next;
167 }
168 }
170 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
171 {
172 struct irq_pin_list *entry = irq_2_pin + irq;
173 unsigned int pin, reg;
175 for (;;) {
176 pin = entry->pin;
177 if (pin == -1)
178 break;
179 reg = io_apic_read(entry->apic, 0x10 + pin*2);
180 reg &= ~disable;
181 reg |= enable;
182 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
183 if (!entry->next)
184 break;
185 entry = irq_2_pin + entry->next;
186 }
187 }
189 /* mask = 1 */
190 static void __mask_IO_APIC_irq (unsigned int irq)
191 {
192 __modify_IO_APIC_irq(irq, 0x00010000, 0);
193 }
195 /* mask = 0 */
196 static void __unmask_IO_APIC_irq (unsigned int irq)
197 {
198 __modify_IO_APIC_irq(irq, 0, 0x00010000);
199 }
201 /* trigger = 0 */
202 static void __edge_IO_APIC_irq (unsigned int irq)
203 {
204 __modify_IO_APIC_irq(irq, 0, 0x00008000);
205 }
207 /* trigger = 1 */
208 static void __level_IO_APIC_irq (unsigned int irq)
209 {
210 __modify_IO_APIC_irq(irq, 0x00008000, 0);
211 }
213 static void mask_IO_APIC_irq (unsigned int irq)
214 {
215 unsigned long flags;
217 spin_lock_irqsave(&ioapic_lock, flags);
218 __mask_IO_APIC_irq(irq);
219 spin_unlock_irqrestore(&ioapic_lock, flags);
220 }
222 static void unmask_IO_APIC_irq (unsigned int irq)
223 {
224 unsigned long flags;
226 spin_lock_irqsave(&ioapic_lock, flags);
227 __unmask_IO_APIC_irq(irq);
228 spin_unlock_irqrestore(&ioapic_lock, flags);
229 }
231 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
232 {
233 struct IO_APIC_route_entry entry;
234 unsigned long flags;
236 /* Check delivery_mode to be sure we're not clearing an SMI pin */
237 spin_lock_irqsave(&ioapic_lock, flags);
238 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
239 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
240 spin_unlock_irqrestore(&ioapic_lock, flags);
241 if (entry.delivery_mode == dest_SMI)
242 return;
244 /*
245 * Disable it in the IO-APIC irq-routing table:
246 */
247 memset(&entry, 0, sizeof(entry));
248 entry.mask = 1;
249 spin_lock_irqsave(&ioapic_lock, flags);
250 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
251 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
252 spin_unlock_irqrestore(&ioapic_lock, flags);
253 }
255 static void clear_IO_APIC (void)
256 {
257 int apic, pin;
259 for (apic = 0; apic < nr_ioapics; apic++)
260 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
261 clear_IO_APIC_pin(apic, pin);
262 }
264 #ifdef CONFIG_SMP
265 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
266 {
267 unsigned long flags;
268 int pin;
269 struct irq_pin_list *entry = irq_2_pin + irq;
270 unsigned int apicid_value;
272 cpus_and(cpumask, cpumask, cpu_online_map);
273 if (cpus_empty(cpumask))
274 cpumask = TARGET_CPUS;
276 apicid_value = cpu_mask_to_apicid(cpumask);
277 /* Prepare to do the io_apic_write */
278 apicid_value = apicid_value << 24;
279 spin_lock_irqsave(&ioapic_lock, flags);
280 for (;;) {
281 pin = entry->pin;
282 if (pin == -1)
283 break;
284 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
285 if (!entry->next)
286 break;
287 entry = irq_2_pin + entry->next;
288 }
289 set_irq_info(irq, cpumask);
290 spin_unlock_irqrestore(&ioapic_lock, flags);
291 }
292 #endif /* CONFIG_SMP */
294 /*
295 * Find the IRQ entry number of a certain pin.
296 */
297 static int find_irq_entry(int apic, int pin, int type)
298 {
299 int i;
301 for (i = 0; i < mp_irq_entries; i++)
302 if (mp_irqs[i].mpc_irqtype == type &&
303 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
304 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
305 mp_irqs[i].mpc_dstirq == pin)
306 return i;
308 return -1;
309 }
311 /*
312 * Find the pin to which IRQ[irq] (ISA) is connected
313 */
314 static int __init find_isa_irq_pin(int irq, int type)
315 {
316 int i;
318 for (i = 0; i < mp_irq_entries; i++) {
319 int lbus = mp_irqs[i].mpc_srcbus;
321 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
322 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
323 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
324 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
325 ) &&
326 (mp_irqs[i].mpc_irqtype == type) &&
327 (mp_irqs[i].mpc_srcbusirq == irq))
329 return mp_irqs[i].mpc_dstirq;
330 }
331 return -1;
332 }
334 static int __init find_isa_irq_apic(int irq, int type)
335 {
336 int i;
338 for (i = 0; i < mp_irq_entries; i++) {
339 int lbus = mp_irqs[i].mpc_srcbus;
341 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
342 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
343 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
344 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
345 ) &&
346 (mp_irqs[i].mpc_irqtype == type) &&
347 (mp_irqs[i].mpc_srcbusirq == irq))
348 break;
349 }
350 if (i < mp_irq_entries) {
351 int apic;
352 for(apic = 0; apic < nr_ioapics; apic++) {
353 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
354 return apic;
355 }
356 }
358 return -1;
359 }
361 /*
362 * Find a specific PCI IRQ entry.
363 * Not an __init, possibly needed by modules
364 */
365 static int pin_2_irq(int idx, int apic, int pin);
367 /*
368 * This function currently is only a helper for the i386 smp boot process where
369 * we need to reprogram the ioredtbls to cater for the cpus which have come online
370 * so mask in all cases should simply be TARGET_CPUS
371 */
372 #ifdef CONFIG_SMP
373 void /*__init*/ setup_ioapic_dest(void)
374 {
375 int pin, ioapic, irq, irq_entry;
377 if (skip_ioapic_setup == 1)
378 return;
380 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
381 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
382 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
383 if (irq_entry == -1)
384 continue;
385 irq = pin_2_irq(irq_entry, ioapic, pin);
386 set_ioapic_affinity_irq(irq, TARGET_CPUS);
387 }
389 }
390 }
391 #endif
393 /*
394 * EISA Edge/Level control register, ELCR
395 */
396 static int EISA_ELCR(unsigned int irq)
397 {
398 if (irq < 16) {
399 unsigned int port = 0x4d0 + (irq >> 3);
400 return (inb(port) >> (irq & 7)) & 1;
401 }
402 apic_printk(APIC_VERBOSE, KERN_INFO
403 "Broken MPtable reports ISA irq %d\n", irq);
404 return 0;
405 }
407 /* EISA interrupts are always polarity zero and can be edge or level
408 * trigger depending on the ELCR value. If an interrupt is listed as
409 * EISA conforming in the MP table, that means its trigger type must
410 * be read in from the ELCR */
412 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
413 #define default_EISA_polarity(idx) (0)
415 /* ISA interrupts are always polarity zero edge triggered,
416 * when listed as conforming in the MP table. */
418 #define default_ISA_trigger(idx) (0)
419 #define default_ISA_polarity(idx) (0)
421 /* PCI interrupts are always polarity one level triggered,
422 * when listed as conforming in the MP table. */
424 #define default_PCI_trigger(idx) (1)
425 #define default_PCI_polarity(idx) (1)
427 /* MCA interrupts are always polarity zero level triggered,
428 * when listed as conforming in the MP table. */
430 #define default_MCA_trigger(idx) (1)
431 #define default_MCA_polarity(idx) (0)
433 /* NEC98 interrupts are always polarity zero edge triggered,
434 * when listed as conforming in the MP table. */
436 #define default_NEC98_trigger(idx) (0)
437 #define default_NEC98_polarity(idx) (0)
439 static int __init MPBIOS_polarity(int idx)
440 {
441 int bus = mp_irqs[idx].mpc_srcbus;
442 int polarity;
444 /*
445 * Determine IRQ line polarity (high active or low active):
446 */
447 switch (mp_irqs[idx].mpc_irqflag & 3)
448 {
449 case 0: /* conforms, ie. bus-type dependent polarity */
450 {
451 switch (mp_bus_id_to_type[bus])
452 {
453 case MP_BUS_ISA: /* ISA pin */
454 {
455 polarity = default_ISA_polarity(idx);
456 break;
457 }
458 case MP_BUS_EISA: /* EISA pin */
459 {
460 polarity = default_EISA_polarity(idx);
461 break;
462 }
463 case MP_BUS_PCI: /* PCI pin */
464 {
465 polarity = default_PCI_polarity(idx);
466 break;
467 }
468 case MP_BUS_MCA: /* MCA pin */
469 {
470 polarity = default_MCA_polarity(idx);
471 break;
472 }
473 case MP_BUS_NEC98: /* NEC 98 pin */
474 {
475 polarity = default_NEC98_polarity(idx);
476 break;
477 }
478 default:
479 {
480 printk(KERN_WARNING "broken BIOS!!\n");
481 polarity = 1;
482 break;
483 }
484 }
485 break;
486 }
487 case 1: /* high active */
488 {
489 polarity = 0;
490 break;
491 }
492 case 2: /* reserved */
493 {
494 printk(KERN_WARNING "broken BIOS!!\n");
495 polarity = 1;
496 break;
497 }
498 case 3: /* low active */
499 {
500 polarity = 1;
501 break;
502 }
503 default: /* invalid */
504 {
505 printk(KERN_WARNING "broken BIOS!!\n");
506 polarity = 1;
507 break;
508 }
509 }
510 return polarity;
511 }
513 static int MPBIOS_trigger(int idx)
514 {
515 int bus = mp_irqs[idx].mpc_srcbus;
516 int trigger;
518 /*
519 * Determine IRQ trigger mode (edge or level sensitive):
520 */
521 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
522 {
523 case 0: /* conforms, ie. bus-type dependent */
524 {
525 switch (mp_bus_id_to_type[bus])
526 {
527 case MP_BUS_ISA: /* ISA pin */
528 {
529 trigger = default_ISA_trigger(idx);
530 break;
531 }
532 case MP_BUS_EISA: /* EISA pin */
533 {
534 trigger = default_EISA_trigger(idx);
535 break;
536 }
537 case MP_BUS_PCI: /* PCI pin */
538 {
539 trigger = default_PCI_trigger(idx);
540 break;
541 }
542 case MP_BUS_MCA: /* MCA pin */
543 {
544 trigger = default_MCA_trigger(idx);
545 break;
546 }
547 case MP_BUS_NEC98: /* NEC 98 pin */
548 {
549 trigger = default_NEC98_trigger(idx);
550 break;
551 }
552 default:
553 {
554 printk(KERN_WARNING "broken BIOS!!\n");
555 trigger = 1;
556 break;
557 }
558 }
559 break;
560 }
561 case 1: /* edge */
562 {
563 trigger = 0;
564 break;
565 }
566 case 2: /* reserved */
567 {
568 printk(KERN_WARNING "broken BIOS!!\n");
569 trigger = 1;
570 break;
571 }
572 case 3: /* level */
573 {
574 trigger = 1;
575 break;
576 }
577 default: /* invalid */
578 {
579 printk(KERN_WARNING "broken BIOS!!\n");
580 trigger = 0;
581 break;
582 }
583 }
584 return trigger;
585 }
587 static inline int irq_polarity(int idx)
588 {
589 return MPBIOS_polarity(idx);
590 }
592 static inline int irq_trigger(int idx)
593 {
594 return MPBIOS_trigger(idx);
595 }
597 static int pin_2_irq(int idx, int apic, int pin)
598 {
599 int irq, i;
600 int bus = mp_irqs[idx].mpc_srcbus;
602 /*
603 * Debugging check, we are in big trouble if this message pops up!
604 */
605 if (mp_irqs[idx].mpc_dstirq != pin)
606 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
608 switch (mp_bus_id_to_type[bus])
609 {
610 case MP_BUS_ISA: /* ISA pin */
611 case MP_BUS_EISA:
612 case MP_BUS_MCA:
613 case MP_BUS_NEC98:
614 {
615 irq = mp_irqs[idx].mpc_srcbusirq;
616 break;
617 }
618 case MP_BUS_PCI: /* PCI pin */
619 {
620 /*
621 * PCI IRQs are mapped in order
622 */
623 i = irq = 0;
624 while (i < apic)
625 irq += nr_ioapic_registers[i++];
626 irq += pin;
628 /*
629 * For MPS mode, so far only needed by ES7000 platform
630 */
631 if (ioapic_renumber_irq)
632 irq = ioapic_renumber_irq(apic, irq);
634 break;
635 }
636 default:
637 {
638 printk(KERN_ERR "unknown bus type %d.\n",bus);
639 irq = 0;
640 break;
641 }
642 }
644 return irq;
645 }
647 static inline int IO_APIC_irq_trigger(int irq)
648 {
649 int apic, idx, pin;
651 for (apic = 0; apic < nr_ioapics; apic++) {
652 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
653 idx = find_irq_entry(apic,pin,mp_INT);
654 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
655 return irq_trigger(idx);
656 }
657 }
658 /*
659 * nonexistent IRQs are edge default
660 */
661 return 0;
662 }
664 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
665 u8 *irq_vector __read_mostly = (u8 *)(1UL << (BITS_PER_LONG - 1));
667 static struct hw_interrupt_type ioapic_level_type;
668 static struct hw_interrupt_type ioapic_edge_type;
670 #define IOAPIC_AUTO -1
671 #define IOAPIC_EDGE 0
672 #define IOAPIC_LEVEL 1
674 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
675 {
676 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
677 trigger == IOAPIC_LEVEL)
678 irq_desc[vector].handler = &ioapic_level_type;
679 else
680 irq_desc[vector].handler = &ioapic_edge_type;
681 }
683 static void __init setup_IO_APIC_irqs(void)
684 {
685 struct IO_APIC_route_entry entry;
686 int apic, pin, idx, irq, first_notcon = 1, vector;
687 unsigned long flags;
689 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
691 for (apic = 0; apic < nr_ioapics; apic++) {
692 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
694 /*
695 * add it to the IO-APIC irq-routing table:
696 */
697 memset(&entry,0,sizeof(entry));
699 entry.delivery_mode = INT_DELIVERY_MODE;
700 entry.dest_mode = INT_DEST_MODE;
701 entry.mask = 0; /* enable IRQ */
702 entry.dest.logical.logical_dest =
703 cpu_mask_to_apicid(TARGET_CPUS);
705 idx = find_irq_entry(apic,pin,mp_INT);
706 if (idx == -1) {
707 if (first_notcon) {
708 apic_printk(APIC_VERBOSE, KERN_DEBUG
709 " IO-APIC (apicid-pin) %d-%d",
710 mp_ioapics[apic].mpc_apicid,
711 pin);
712 first_notcon = 0;
713 } else
714 apic_printk(APIC_VERBOSE, ", %d-%d",
715 mp_ioapics[apic].mpc_apicid, pin);
716 continue;
717 }
719 entry.trigger = irq_trigger(idx);
720 entry.polarity = irq_polarity(idx);
722 if (irq_trigger(idx)) {
723 entry.trigger = 1;
724 entry.mask = 1;
725 }
727 irq = pin_2_irq(idx, apic, pin);
728 /*
729 * skip adding the timer int on secondary nodes, which causes
730 * a small but painful rift in the time-space continuum
731 */
732 if (multi_timer_check(apic, irq))
733 continue;
734 else
735 add_pin_to_irq(irq, apic, pin);
737 if (!apic && !IO_APIC_IRQ(irq))
738 continue;
740 if (IO_APIC_IRQ(irq)) {
741 vector = assign_irq_vector(irq);
742 entry.vector = vector;
743 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
745 if (!apic && (irq < 16))
746 disable_8259A_irq(irq);
747 }
748 spin_lock_irqsave(&ioapic_lock, flags);
749 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
750 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
751 set_native_irq_info(entry.vector, TARGET_CPUS);
752 spin_unlock_irqrestore(&ioapic_lock, flags);
753 }
754 }
756 if (!first_notcon)
757 apic_printk(APIC_VERBOSE, " not connected.\n");
758 }
760 /*
761 * Set up the 8259A-master output pin:
762 */
763 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
764 {
765 struct IO_APIC_route_entry entry;
766 unsigned long flags;
768 memset(&entry,0,sizeof(entry));
770 disable_8259A_irq(0);
772 /* mask LVT0 */
773 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
775 /*
776 * We use logical delivery to get the timer IRQ
777 * to the first CPU.
778 */
779 entry.dest_mode = INT_DEST_MODE;
780 entry.mask = 0; /* unmask IRQ now */
781 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
782 entry.delivery_mode = INT_DELIVERY_MODE;
783 entry.polarity = 0;
784 entry.trigger = 0;
785 entry.vector = vector;
787 /*
788 * The timer IRQ doesn't have to know that behind the
789 * scene we have a 8259A-master in AEOI mode ...
790 */
791 irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
793 /*
794 * Add it to the IO-APIC irq-routing table:
795 */
796 spin_lock_irqsave(&ioapic_lock, flags);
797 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
798 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
799 spin_unlock_irqrestore(&ioapic_lock, flags);
801 enable_8259A_irq(0);
802 }
804 static inline void UNEXPECTED_IO_APIC(void)
805 {
806 }
808 void /*__init*/ __print_IO_APIC(void)
809 {
810 int apic, i;
811 union IO_APIC_reg_00 reg_00;
812 union IO_APIC_reg_01 reg_01;
813 union IO_APIC_reg_02 reg_02;
814 union IO_APIC_reg_03 reg_03;
815 unsigned long flags;
817 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
818 for (i = 0; i < nr_ioapics; i++)
819 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
820 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
822 /*
823 * We are a bit conservative about what we expect. We have to
824 * know about every hardware change ASAP.
825 */
826 printk(KERN_INFO "testing the IO APIC.......................\n");
828 for (apic = 0; apic < nr_ioapics; apic++) {
830 spin_lock_irqsave(&ioapic_lock, flags);
831 reg_00.raw = io_apic_read(apic, 0);
832 reg_01.raw = io_apic_read(apic, 1);
833 if (reg_01.bits.version >= 0x10)
834 reg_02.raw = io_apic_read(apic, 2);
835 if (reg_01.bits.version >= 0x20)
836 reg_03.raw = io_apic_read(apic, 3);
837 spin_unlock_irqrestore(&ioapic_lock, flags);
839 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
840 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
841 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
842 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
843 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
844 if (reg_00.bits.ID >= get_physical_broadcast())
845 UNEXPECTED_IO_APIC();
846 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
847 UNEXPECTED_IO_APIC();
849 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
850 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
851 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
852 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
853 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
854 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
855 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
856 (reg_01.bits.entries != 0x2E) &&
857 (reg_01.bits.entries != 0x3F)
858 )
859 UNEXPECTED_IO_APIC();
861 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
862 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
863 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
864 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
865 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
866 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
867 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
868 )
869 UNEXPECTED_IO_APIC();
870 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
871 UNEXPECTED_IO_APIC();
873 /*
874 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
875 * but the value of reg_02 is read as the previous read register
876 * value, so ignore it if reg_02 == reg_01.
877 */
878 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
879 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
880 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
881 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
882 UNEXPECTED_IO_APIC();
883 }
885 /*
886 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
887 * or reg_03, but the value of reg_0[23] is read as the previous read
888 * register value, so ignore it if reg_03 == reg_0[12].
889 */
890 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
891 reg_03.raw != reg_01.raw) {
892 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
893 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
894 if (reg_03.bits.__reserved_1)
895 UNEXPECTED_IO_APIC();
896 }
898 printk(KERN_DEBUG ".... IRQ redirection table:\n");
900 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
901 " Stat Dest Deli Vect: \n");
903 for (i = 0; i <= reg_01.bits.entries; i++) {
904 struct IO_APIC_route_entry entry;
906 spin_lock_irqsave(&ioapic_lock, flags);
907 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
908 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
909 spin_unlock_irqrestore(&ioapic_lock, flags);
911 printk(KERN_DEBUG " %02x %03X %02X ",
912 i,
913 entry.dest.logical.logical_dest,
914 entry.dest.physical.physical_dest
915 );
917 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
918 entry.mask,
919 entry.trigger,
920 entry.irr,
921 entry.polarity,
922 entry.delivery_status,
923 entry.dest_mode,
924 entry.delivery_mode,
925 entry.vector
926 );
927 }
928 }
929 printk(KERN_INFO "Using vector-based indexing\n");
930 printk(KERN_DEBUG "IRQ to pin mappings:\n");
931 for (i = 0; i < nr_irqs; i++) {
932 struct irq_pin_list *entry = irq_2_pin + i;
933 if (entry->pin < 0)
934 continue;
935 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
936 for (;;) {
937 printk("-> %d:%d", entry->apic, entry->pin);
938 if (!entry->next)
939 break;
940 entry = irq_2_pin + entry->next;
941 }
942 printk("\n");
943 }
945 printk(KERN_INFO ".................................... done.\n");
947 return;
948 }
950 void print_IO_APIC(void)
951 {
952 if (apic_verbosity != APIC_QUIET)
953 __print_IO_APIC();
954 }
956 void print_IO_APIC_keyhandler(unsigned char key)
957 {
958 __print_IO_APIC();
959 }
961 static void __init enable_IO_APIC(void)
962 {
963 int i8259_apic, i8259_pin;
964 int i, apic;
965 unsigned long flags;
967 /* Initialise dynamic irq_2_pin free list. */
968 irq_2_pin = xmalloc_array(struct irq_pin_list, PIN_MAP_SIZE);
969 memset(irq_2_pin, 0, nr_irqs * sizeof(*irq_2_pin));
970 for (i = 0; i < PIN_MAP_SIZE; i++)
971 irq_2_pin[i].pin = -1;
972 for (i = irq_2_pin_free_entry = nr_irqs; i < PIN_MAP_SIZE; i++)
973 irq_2_pin[i].next = i + 1;
975 for(apic = 0; apic < nr_ioapics; apic++) {
976 int pin;
977 /* See if any of the pins is in ExtINT mode */
978 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
979 struct IO_APIC_route_entry entry;
980 spin_lock_irqsave(&ioapic_lock, flags);
981 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
982 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
983 spin_unlock_irqrestore(&ioapic_lock, flags);
986 /* If the interrupt line is enabled and in ExtInt mode
987 * I have found the pin where the i8259 is connected.
988 */
989 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
990 ioapic_i8259.apic = apic;
991 ioapic_i8259.pin = pin;
992 goto found_i8259;
993 }
994 }
995 }
996 found_i8259:
997 /* Look to see what if the MP table has reported the ExtINT */
998 /* If we could not find the appropriate pin by looking at the ioapic
999 * the i8259 probably is not connected the ioapic but give the
1000 * mptable a chance anyway.
1001 */
1002 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1003 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1004 /* Trust the MP table if nothing is setup in the hardware */
1005 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1006 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1007 ioapic_i8259.pin = i8259_pin;
1008 ioapic_i8259.apic = i8259_apic;
1010 /* Complain if the MP table and the hardware disagree */
1011 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1012 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1014 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1017 /*
1018 * Do not trust the IO-APIC being empty at bootup
1019 */
1020 clear_IO_APIC();
1023 /*
1024 * Not an __init, needed by the reboot code
1025 */
1026 void disable_IO_APIC(void)
1028 /*
1029 * Clear the IO-APIC before rebooting:
1030 */
1031 clear_IO_APIC();
1033 /*
1034 * If the i8259 is routed through an IOAPIC
1035 * Put that IOAPIC in virtual wire mode
1036 * so legacy interrupts can be delivered.
1037 */
1038 if (ioapic_i8259.pin != -1) {
1039 struct IO_APIC_route_entry entry;
1040 unsigned long flags;
1042 memset(&entry, 0, sizeof(entry));
1043 entry.mask = 0; /* Enabled */
1044 entry.trigger = 0; /* Edge */
1045 entry.irr = 0;
1046 entry.polarity = 0; /* High */
1047 entry.delivery_status = 0;
1048 entry.dest_mode = 0; /* Physical */
1049 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1050 entry.vector = 0;
1051 entry.dest.physical.physical_dest =
1052 get_apic_id();
1054 /*
1055 * Add it to the IO-APIC irq-routing table:
1056 */
1057 spin_lock_irqsave(&ioapic_lock, flags);
1058 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1059 *(((int *)&entry)+1));
1060 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1061 *(((int *)&entry)+0));
1062 spin_unlock_irqrestore(&ioapic_lock, flags);
1064 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1067 /*
1068 * function to set the IO-APIC physical IDs based on the
1069 * values stored in the MPC table.
1071 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1072 */
1074 #ifndef CONFIG_X86_NUMAQ
1075 static void __init setup_ioapic_ids_from_mpc(void)
1077 union IO_APIC_reg_00 reg_00;
1078 physid_mask_t phys_id_present_map;
1079 int apic;
1080 int i;
1081 unsigned char old_id;
1082 unsigned long flags;
1084 /*
1085 * Don't check I/O APIC IDs for xAPIC systems. They have
1086 * no meaning without the serial APIC bus.
1087 */
1088 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1089 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1090 return;
1092 /*
1093 * This is broken; anything with a real cpu count has to
1094 * circumvent this idiocy regardless.
1095 */
1096 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1098 /*
1099 * Set the IOAPIC ID to the value stored in the MPC table.
1100 */
1101 for (apic = 0; apic < nr_ioapics; apic++) {
1103 /* Read the register 0 value */
1104 spin_lock_irqsave(&ioapic_lock, flags);
1105 reg_00.raw = io_apic_read(apic, 0);
1106 spin_unlock_irqrestore(&ioapic_lock, flags);
1108 old_id = mp_ioapics[apic].mpc_apicid;
1110 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1111 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1112 apic, mp_ioapics[apic].mpc_apicid);
1113 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1114 reg_00.bits.ID);
1115 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1118 /*
1119 * Sanity check, is the ID really free? Every APIC in a
1120 * system must have a unique ID or we get lots of nice
1121 * 'stuck on smp_invalidate_needed IPI wait' messages.
1122 */
1123 if (check_apicid_used(phys_id_present_map,
1124 mp_ioapics[apic].mpc_apicid)) {
1125 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1126 apic, mp_ioapics[apic].mpc_apicid);
1127 for (i = 0; i < get_physical_broadcast(); i++)
1128 if (!physid_isset(i, phys_id_present_map))
1129 break;
1130 if (i >= get_physical_broadcast())
1131 panic("Max APIC ID exceeded!\n");
1132 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1133 i);
1134 physid_set(i, phys_id_present_map);
1135 mp_ioapics[apic].mpc_apicid = i;
1136 } else {
1137 physid_mask_t tmp;
1138 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1139 apic_printk(APIC_VERBOSE, "Setting %d in the "
1140 "phys_id_present_map\n",
1141 mp_ioapics[apic].mpc_apicid);
1142 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1146 /*
1147 * We need to adjust the IRQ routing table
1148 * if the ID changed.
1149 */
1150 if (old_id != mp_ioapics[apic].mpc_apicid)
1151 for (i = 0; i < mp_irq_entries; i++)
1152 if (mp_irqs[i].mpc_dstapic == old_id)
1153 mp_irqs[i].mpc_dstapic
1154 = mp_ioapics[apic].mpc_apicid;
1156 /*
1157 * Read the right value from the MPC table and
1158 * write it into the ID register.
1159 */
1160 apic_printk(APIC_VERBOSE, KERN_INFO
1161 "...changing IO-APIC physical APIC ID to %d ...",
1162 mp_ioapics[apic].mpc_apicid);
1164 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1165 spin_lock_irqsave(&ioapic_lock, flags);
1166 io_apic_write(apic, 0, reg_00.raw);
1167 spin_unlock_irqrestore(&ioapic_lock, flags);
1169 /*
1170 * Sanity check
1171 */
1172 spin_lock_irqsave(&ioapic_lock, flags);
1173 reg_00.raw = io_apic_read(apic, 0);
1174 spin_unlock_irqrestore(&ioapic_lock, flags);
1175 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1176 printk("could not set ID!\n");
1177 else
1178 apic_printk(APIC_VERBOSE, " ok.\n");
1181 #else
1182 static void __init setup_ioapic_ids_from_mpc(void) { }
1183 #endif
1185 /*
1186 * There is a nasty bug in some older SMP boards, their mptable lies
1187 * about the timer IRQ. We do the following to work around the situation:
1189 * - timer IRQ defaults to IO-APIC IRQ
1190 * - if this function detects that timer IRQs are defunct, then we fall
1191 * back to ISA timer IRQs
1192 */
1193 static int __init timer_irq_works(void)
1195 extern unsigned long pit0_ticks;
1196 unsigned long t1, flags;
1198 t1 = pit0_ticks;
1199 mb();
1201 local_save_flags(flags);
1202 local_irq_enable();
1203 /* Let ten ticks pass... */
1204 mdelay((10 * 1000) / HZ);
1205 local_irq_restore(flags);
1207 /*
1208 * Expect a few ticks at least, to be sure some possible
1209 * glue logic does not lock up after one or two first
1210 * ticks in a non-ExtINT mode. Also the local APIC
1211 * might have cached one ExtINT interrupt. Finally, at
1212 * least one tick may be lost due to delays.
1213 */
1214 mb();
1215 if (pit0_ticks - t1 > 4)
1216 return 1;
1218 return 0;
1221 /*
1222 * In the SMP+IOAPIC case it might happen that there are an unspecified
1223 * number of pending IRQ events unhandled. These cases are very rare,
1224 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1225 * better to do it this way as thus we do not have to be aware of
1226 * 'pending' interrupts in the IRQ path, except at this point.
1227 */
1228 /*
1229 * Edge triggered needs to resend any interrupt
1230 * that was delayed but this is now handled in the device
1231 * independent code.
1232 */
1234 /*
1235 * Starting up a edge-triggered IO-APIC interrupt is
1236 * nasty - we need to make sure that we get the edge.
1237 * If it is already asserted for some reason, we need
1238 * return 1 to indicate that is was pending.
1240 * This is not complete - we should be able to fake
1241 * an edge even if it isn't on the 8259A...
1242 */
1243 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1245 int was_pending = 0;
1246 unsigned long flags;
1248 spin_lock_irqsave(&ioapic_lock, flags);
1249 if (irq < 16) {
1250 disable_8259A_irq(irq);
1251 if (i8259A_irq_pending(irq))
1252 was_pending = 1;
1254 __unmask_IO_APIC_irq(irq);
1255 spin_unlock_irqrestore(&ioapic_lock, flags);
1257 return was_pending;
1260 /*
1261 * Once we have recorded IRQ_PENDING already, we can mask the
1262 * interrupt for real. This prevents IRQ storms from unhandled
1263 * devices.
1264 */
1265 static void ack_edge_ioapic_irq(unsigned int irq)
1267 if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
1268 == (IRQ_PENDING | IRQ_DISABLED))
1269 mask_IO_APIC_irq(irq);
1270 ack_APIC_irq();
1273 /*
1274 * Level triggered interrupts can just be masked,
1275 * and shutting down and starting up the interrupt
1276 * is the same as enabling and disabling them -- except
1277 * with a startup need to return a "was pending" value.
1279 * Level triggered interrupts are special because we
1280 * do not touch any IO-APIC register while handling
1281 * them. We ack the APIC in the end-IRQ handler, not
1282 * in the start-IRQ-handler. Protection against reentrance
1283 * from the same interrupt is still provided, both by the
1284 * generic IRQ layer and by the fact that an unacked local
1285 * APIC does not accept IRQs.
1286 */
1287 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1289 unmask_IO_APIC_irq(irq);
1291 return 0; /* don't check for pending */
1294 int ioapic_ack_new = 1;
1295 static void setup_ioapic_ack(char *s)
1297 if ( !strcmp(s, "old") )
1298 ioapic_ack_new = 0;
1299 else if ( !strcmp(s, "new") )
1300 ioapic_ack_new = 1;
1301 else
1302 printk("Unknown ioapic_ack value specified: '%s'\n", s);
1304 custom_param("ioapic_ack", setup_ioapic_ack);
1306 static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1308 unsigned long v;
1309 int i;
1311 if ( ioapic_ack_new )
1312 return;
1314 mask_IO_APIC_irq(irq);
1316 /*
1317 * It appears there is an erratum which affects at least version 0x11
1318 * of I/O APIC (that's the 82093AA and cores integrated into various
1319 * chipsets). Under certain conditions a level-triggered interrupt is
1320 * erroneously delivered as edge-triggered one but the respective IRR
1321 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1322 * message but it will never arrive and further interrupts are blocked
1323 * from the source. The exact reason is so far unknown, but the
1324 * phenomenon was observed when two consecutive interrupt requests
1325 * from a given source get delivered to the same CPU and the source is
1326 * temporarily disabled in between.
1328 * A workaround is to simulate an EOI message manually. We achieve it
1329 * by setting the trigger mode to edge and then to level when the edge
1330 * trigger mode gets detected in the TMR of a local APIC for a
1331 * level-triggered interrupt. We mask the source for the time of the
1332 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1333 * The idea is from Manfred Spraul. --macro
1334 */
1335 i = IO_APIC_VECTOR(irq);
1337 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1339 ack_APIC_irq();
1341 if (!(v & (1 << (i & 0x1f)))) {
1342 atomic_inc(&irq_mis_count);
1343 spin_lock(&ioapic_lock);
1344 __edge_IO_APIC_irq(irq);
1345 __level_IO_APIC_irq(irq);
1346 spin_unlock(&ioapic_lock);
1350 static void end_level_ioapic_irq (unsigned int irq)
1352 unsigned long v;
1353 int i;
1355 if ( !ioapic_ack_new )
1357 if ( !(irq_desc[IO_APIC_VECTOR(irq)].status & IRQ_DISABLED) )
1358 unmask_IO_APIC_irq(irq);
1359 return;
1362 /*
1363 * It appears there is an erratum which affects at least version 0x11
1364 * of I/O APIC (that's the 82093AA and cores integrated into various
1365 * chipsets). Under certain conditions a level-triggered interrupt is
1366 * erroneously delivered as edge-triggered one but the respective IRR
1367 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1368 * message but it will never arrive and further interrupts are blocked
1369 * from the source. The exact reason is so far unknown, but the
1370 * phenomenon was observed when two consecutive interrupt requests
1371 * from a given source get delivered to the same CPU and the source is
1372 * temporarily disabled in between.
1374 * A workaround is to simulate an EOI message manually. We achieve it
1375 * by setting the trigger mode to edge and then to level when the edge
1376 * trigger mode gets detected in the TMR of a local APIC for a
1377 * level-triggered interrupt. We mask the source for the time of the
1378 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1379 * The idea is from Manfred Spraul. --macro
1380 */
1381 i = IO_APIC_VECTOR(irq);
1383 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1385 ack_APIC_irq();
1387 if (!(v & (1 << (i & 0x1f)))) {
1388 atomic_inc(&irq_mis_count);
1389 spin_lock(&ioapic_lock);
1390 __mask_IO_APIC_irq(irq);
1391 __edge_IO_APIC_irq(irq);
1392 __level_IO_APIC_irq(irq);
1393 if ( !(irq_desc[IO_APIC_VECTOR(irq)].status & IRQ_DISABLED) )
1394 __unmask_IO_APIC_irq(irq);
1395 spin_unlock(&ioapic_lock);
1399 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1401 int irq = vector_to_irq(vector);
1402 return startup_edge_ioapic_irq(irq);
1405 static void ack_edge_ioapic_vector(unsigned int vector)
1407 int irq = vector_to_irq(vector);
1408 ack_edge_ioapic_irq(irq);
1411 static unsigned int startup_level_ioapic_vector(unsigned int vector)
1413 int irq = vector_to_irq(vector);
1414 return startup_level_ioapic_irq (irq);
1417 static void mask_and_ack_level_ioapic_vector(unsigned int vector)
1419 int irq = vector_to_irq(vector);
1420 mask_and_ack_level_ioapic_irq(irq);
1423 static void end_level_ioapic_vector(unsigned int vector)
1425 int irq = vector_to_irq(vector);
1426 end_level_ioapic_irq(irq);
1429 static void mask_IO_APIC_vector(unsigned int vector)
1431 int irq = vector_to_irq(vector);
1432 mask_IO_APIC_irq(irq);
1435 static void unmask_IO_APIC_vector(unsigned int vector)
1437 int irq = vector_to_irq(vector);
1438 unmask_IO_APIC_irq(irq);
1441 static void set_ioapic_affinity_vector(
1442 unsigned int vector, cpumask_t cpu_mask)
1444 int irq = vector_to_irq(vector);
1446 set_native_irq_info(vector, cpu_mask);
1447 set_ioapic_affinity_irq(irq, cpu_mask);
1450 static void disable_edge_ioapic_vector(unsigned int vector)
1454 static void end_edge_ioapic_vector(unsigned int vector)
1458 /*
1459 * Level and edge triggered IO-APIC interrupts need different handling,
1460 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1461 * handled with the level-triggered descriptor, but that one has slightly
1462 * more overhead. Level-triggered interrupts cannot be handled with the
1463 * edge-triggered handler, without risking IRQ storms and other ugly
1464 * races.
1465 */
1466 static struct hw_interrupt_type ioapic_edge_type = {
1467 .typename = "IO-APIC-edge",
1468 .startup = startup_edge_ioapic_vector,
1469 .shutdown = disable_edge_ioapic_vector,
1470 .enable = unmask_IO_APIC_vector,
1471 .disable = disable_edge_ioapic_vector,
1472 .ack = ack_edge_ioapic_vector,
1473 .end = end_edge_ioapic_vector,
1474 .set_affinity = set_ioapic_affinity_vector,
1475 };
1477 static struct hw_interrupt_type ioapic_level_type = {
1478 .typename = "IO-APIC-level",
1479 .startup = startup_level_ioapic_vector,
1480 .shutdown = mask_IO_APIC_vector,
1481 .enable = unmask_IO_APIC_vector,
1482 .disable = mask_IO_APIC_vector,
1483 .ack = mask_and_ack_level_ioapic_vector,
1484 .end = end_level_ioapic_vector,
1485 .set_affinity = set_ioapic_affinity_vector,
1486 };
1488 static unsigned int startup_msi_vector(unsigned int vector)
1490 unmask_msi_vector(vector);
1491 return 0;
1494 static void ack_msi_vector(unsigned int vector)
1496 if ( msi_maskable_irq(irq_desc[vector].msi_desc) )
1497 ack_APIC_irq(); /* ACKTYPE_NONE */
1500 static void end_msi_vector(unsigned int vector)
1502 if ( !msi_maskable_irq(irq_desc[vector].msi_desc) )
1503 ack_APIC_irq(); /* ACKTYPE_EOI */
1506 static void shutdown_msi_vector(unsigned int vector)
1508 mask_msi_vector(vector);
1511 static void set_msi_affinity_vector(unsigned int vector, cpumask_t cpu_mask)
1513 set_native_irq_info(vector, cpu_mask);
1514 set_msi_affinity(vector, cpu_mask);
1517 /*
1518 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1519 * which implement the MSI or MSI-X Capability Structure.
1520 */
1521 struct hw_interrupt_type pci_msi_type = {
1522 .typename = "PCI-MSI",
1523 .startup = startup_msi_vector,
1524 .shutdown = shutdown_msi_vector,
1525 .enable = unmask_msi_vector,
1526 .disable = mask_msi_vector,
1527 .ack = ack_msi_vector,
1528 .end = end_msi_vector,
1529 .set_affinity = set_msi_affinity_vector,
1530 };
1532 static inline void init_IO_APIC_traps(void)
1534 int irq;
1535 /* Xen: This is way simpler than the Linux implementation. */
1536 for (irq = 0; irq < 16 ; irq++)
1537 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
1538 make_8259A_irq(irq);
1541 static void enable_lapic_vector(unsigned int vector)
1543 unsigned long v;
1545 v = apic_read(APIC_LVT0);
1546 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1549 static void disable_lapic_vector(unsigned int vector)
1551 unsigned long v;
1553 v = apic_read(APIC_LVT0);
1554 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1557 static void ack_lapic_vector(unsigned int vector)
1559 ack_APIC_irq();
1562 static void end_lapic_vector(unsigned int vector) { /* nothing */ }
1564 static struct hw_interrupt_type lapic_irq_type = {
1565 .typename = "local-APIC-edge",
1566 .startup = NULL, /* startup_irq() not used for IRQ0 */
1567 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1568 .enable = enable_lapic_vector,
1569 .disable = disable_lapic_vector,
1570 .ack = ack_lapic_vector,
1571 .end = end_lapic_vector
1572 };
1574 /*
1575 * This looks a bit hackish but it's about the only one way of sending
1576 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1577 * not support the ExtINT mode, unfortunately. We need to send these
1578 * cycles as some i82489DX-based boards have glue logic that keeps the
1579 * 8259A interrupt line asserted until INTA. --macro
1580 */
1581 static inline void unlock_ExtINT_logic(void)
1583 int apic, pin, i;
1584 struct IO_APIC_route_entry entry0, entry1;
1585 unsigned char save_control, save_freq_select;
1586 unsigned long flags;
1588 pin = find_isa_irq_pin(8, mp_INT);
1589 apic = find_isa_irq_apic(8, mp_INT);
1590 if (pin == -1)
1591 return;
1593 spin_lock_irqsave(&ioapic_lock, flags);
1594 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1595 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1596 spin_unlock_irqrestore(&ioapic_lock, flags);
1597 clear_IO_APIC_pin(apic, pin);
1599 memset(&entry1, 0, sizeof(entry1));
1601 entry1.dest_mode = 0; /* physical delivery */
1602 entry1.mask = 0; /* unmask IRQ now */
1603 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1604 entry1.delivery_mode = dest_ExtINT;
1605 entry1.polarity = entry0.polarity;
1606 entry1.trigger = 0;
1607 entry1.vector = 0;
1609 spin_lock_irqsave(&ioapic_lock, flags);
1610 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1611 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1612 spin_unlock_irqrestore(&ioapic_lock, flags);
1614 save_control = CMOS_READ(RTC_CONTROL);
1615 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1616 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1617 RTC_FREQ_SELECT);
1618 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1620 i = 100;
1621 while (i-- > 0) {
1622 mdelay(10);
1623 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1624 i -= 10;
1627 CMOS_WRITE(save_control, RTC_CONTROL);
1628 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1629 clear_IO_APIC_pin(apic, pin);
1631 spin_lock_irqsave(&ioapic_lock, flags);
1632 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1633 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1634 spin_unlock_irqrestore(&ioapic_lock, flags);
1637 int timer_uses_ioapic_pin_0;
1639 /*
1640 * This code may look a bit paranoid, but it's supposed to cooperate with
1641 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1642 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1643 * fanatically on his truly buggy board.
1644 */
1645 static inline void check_timer(void)
1647 int apic1, pin1, apic2, pin2;
1648 int vector;
1649 unsigned long flags;
1651 local_irq_save(flags);
1653 /*
1654 * get/set the timer IRQ vector:
1655 */
1656 disable_8259A_irq(0);
1657 vector = assign_irq_vector(0);
1659 irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
1660 irq_desc[IO_APIC_VECTOR(0)].depth = 0;
1661 irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
1663 /*
1664 * Subtle, code in do_timer_interrupt() expects an AEOI
1665 * mode for the 8259A whenever interrupts are routed
1666 * through I/O APICs. Also IRQ0 has to be enabled in
1667 * the 8259A which implies the virtual wire has to be
1668 * disabled in the local APIC.
1669 */
1670 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1671 init_8259A(1);
1672 /* XEN: Ripped out the legacy missed-tick logic, so below is not needed. */
1673 /*timer_ack = 1;*/
1674 /*enable_8259A_irq(0);*/
1676 pin1 = find_isa_irq_pin(0, mp_INT);
1677 apic1 = find_isa_irq_apic(0, mp_INT);
1678 pin2 = ioapic_i8259.pin;
1679 apic2 = ioapic_i8259.apic;
1681 if (pin1 == 0)
1682 timer_uses_ioapic_pin_0 = 1;
1684 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1685 vector, apic1, pin1, apic2, pin2);
1687 if (pin1 != -1) {
1688 /*
1689 * Ok, does IRQ0 through the IOAPIC work?
1690 */
1691 unmask_IO_APIC_irq(0);
1692 if (timer_irq_works()) {
1693 local_irq_restore(flags);
1694 if (disable_timer_pin_1 > 0)
1695 clear_IO_APIC_pin(apic1, pin1);
1696 return;
1698 clear_IO_APIC_pin(apic1, pin1);
1699 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
1700 "IO-APIC\n");
1703 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1704 if (pin2 != -1) {
1705 printk("\n..... (found pin %d) ...", pin2);
1706 /*
1707 * legacy devices should be connected to IO APIC #0
1708 */
1709 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1710 if (timer_irq_works()) {
1711 local_irq_restore(flags);
1712 printk("works.\n");
1713 if (pin1 != -1)
1714 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1715 else
1716 add_pin_to_irq(0, apic2, pin2);
1717 return;
1719 /*
1720 * Cleanup, just in case ...
1721 */
1722 clear_IO_APIC_pin(apic2, pin2);
1724 printk(" failed.\n");
1726 if (nmi_watchdog == NMI_IO_APIC) {
1727 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1728 nmi_watchdog = 0;
1731 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1733 disable_8259A_irq(0);
1734 irq_desc[vector].handler = &lapic_irq_type;
1735 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1736 enable_8259A_irq(0);
1738 if (timer_irq_works()) {
1739 local_irq_restore(flags);
1740 printk(" works.\n");
1741 return;
1743 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1744 printk(" failed.\n");
1746 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1748 /*timer_ack = 0;*/
1749 init_8259A(0);
1750 make_8259A_irq(0);
1751 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1753 unlock_ExtINT_logic();
1755 local_irq_restore(flags);
1757 if (timer_irq_works()) {
1758 printk(" works.\n");
1759 return;
1761 printk(" failed :(.\n");
1762 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1763 "report. Then try booting with the 'noapic' option");
1766 /*
1768 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1769 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1770 * Linux doesn't really care, as it's not actually used
1771 * for any interrupt handling anyway.
1772 */
1773 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1775 static struct IO_APIC_route_entry *ioapic_pm_state;
1777 static void __init ioapic_pm_state_alloc(void)
1779 int i, nr_entry = 0;
1781 for (i = 0; i < nr_ioapics; i++)
1782 nr_entry += nr_ioapic_registers[i];
1784 ioapic_pm_state = _xmalloc(sizeof(struct IO_APIC_route_entry)*nr_entry,
1785 sizeof(struct IO_APIC_route_entry));
1786 BUG_ON(ioapic_pm_state == NULL);
1789 void __init setup_IO_APIC(void)
1791 enable_IO_APIC();
1793 if (acpi_ioapic)
1794 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1795 else
1796 io_apic_irqs = ~PIC_IRQS;
1798 printk("ENABLING IO-APIC IRQs\n");
1799 printk(" -> Using %s ACK method\n", ioapic_ack_new ? "new" : "old");
1801 /*
1802 * Set up IO-APIC IRQ routing.
1803 */
1804 if (!acpi_ioapic)
1805 setup_ioapic_ids_from_mpc();
1806 sync_Arb_IDs();
1807 setup_IO_APIC_irqs();
1808 init_IO_APIC_traps();
1809 check_timer();
1810 print_IO_APIC();
1811 ioapic_pm_state_alloc();
1813 register_keyhandler('z', print_IO_APIC_keyhandler, "print ioapic info");
1816 void ioapic_suspend(void)
1818 struct IO_APIC_route_entry *entry = ioapic_pm_state;
1819 unsigned long flags;
1820 int apic, i;
1822 spin_lock_irqsave(&ioapic_lock, flags);
1823 for (apic = 0; apic < nr_ioapics; apic++) {
1824 for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) {
1825 *(((int *)entry) + 1) = io_apic_read(apic, 0x11 + 2 * i);
1826 *(((int *)entry) + 0) = io_apic_read(apic, 0x10 + 2 * i);
1829 spin_unlock_irqrestore(&ioapic_lock, flags);
1832 void ioapic_resume(void)
1834 struct IO_APIC_route_entry *entry = ioapic_pm_state;
1835 unsigned long flags;
1836 union IO_APIC_reg_00 reg_00;
1837 int i, apic;
1839 spin_lock_irqsave(&ioapic_lock, flags);
1840 for (apic = 0; apic < nr_ioapics; apic++){
1841 reg_00.raw = io_apic_read(apic, 0);
1842 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) {
1843 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1844 io_apic_write(apic, 0, reg_00.raw);
1846 for (i = 0; i < nr_ioapic_registers[apic]; i++, entry++) {
1847 io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1));
1848 io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0));
1851 spin_unlock_irqrestore(&ioapic_lock, flags);
1854 /* --------------------------------------------------------------------------
1855 ACPI-based IOAPIC Configuration
1856 -------------------------------------------------------------------------- */
1858 #ifdef CONFIG_ACPI_BOOT
1860 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1862 union IO_APIC_reg_00 reg_00;
1863 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
1864 physid_mask_t tmp;
1865 unsigned long flags;
1866 int i = 0;
1868 /*
1869 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1870 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1871 * supports up to 16 on one shared APIC bus.
1873 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1874 * advantage of new APIC bus architecture.
1875 */
1877 if (physids_empty(apic_id_map))
1878 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
1880 spin_lock_irqsave(&ioapic_lock, flags);
1881 reg_00.raw = io_apic_read(ioapic, 0);
1882 spin_unlock_irqrestore(&ioapic_lock, flags);
1884 if (apic_id >= get_physical_broadcast()) {
1885 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1886 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1887 apic_id = reg_00.bits.ID;
1890 /*
1891 * Every APIC in a system must have a unique ID or we get lots of nice
1892 * 'stuck on smp_invalidate_needed IPI wait' messages.
1893 */
1894 if (check_apicid_used(apic_id_map, apic_id)) {
1896 for (i = 0; i < get_physical_broadcast(); i++) {
1897 if (!check_apicid_used(apic_id_map, i))
1898 break;
1901 if (i == get_physical_broadcast())
1902 panic("Max apic_id exceeded!\n");
1904 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1905 "trying %d\n", ioapic, apic_id, i);
1907 apic_id = i;
1910 tmp = apicid_to_cpu_present(apic_id);
1911 physids_or(apic_id_map, apic_id_map, tmp);
1913 if (reg_00.bits.ID != apic_id) {
1914 reg_00.bits.ID = apic_id;
1916 spin_lock_irqsave(&ioapic_lock, flags);
1917 io_apic_write(ioapic, 0, reg_00.raw);
1918 reg_00.raw = io_apic_read(ioapic, 0);
1919 spin_unlock_irqrestore(&ioapic_lock, flags);
1921 /* Sanity check */
1922 if (reg_00.bits.ID != apic_id) {
1923 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
1924 return -1;
1928 apic_printk(APIC_VERBOSE, KERN_INFO
1929 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1931 return apic_id;
1935 int __init io_apic_get_version (int ioapic)
1937 union IO_APIC_reg_01 reg_01;
1938 unsigned long flags;
1940 spin_lock_irqsave(&ioapic_lock, flags);
1941 reg_01.raw = io_apic_read(ioapic, 1);
1942 spin_unlock_irqrestore(&ioapic_lock, flags);
1944 return reg_01.bits.version;
1948 int __init io_apic_get_redir_entries (int ioapic)
1950 union IO_APIC_reg_01 reg_01;
1951 unsigned long flags;
1953 spin_lock_irqsave(&ioapic_lock, flags);
1954 reg_01.raw = io_apic_read(ioapic, 1);
1955 spin_unlock_irqrestore(&ioapic_lock, flags);
1957 return reg_01.bits.entries;
1961 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1963 struct IO_APIC_route_entry entry;
1964 unsigned long flags;
1966 if (!IO_APIC_IRQ(irq)) {
1967 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1968 ioapic);
1969 return -EINVAL;
1972 /*
1973 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1974 * Note that we mask (disable) IRQs now -- these get enabled when the
1975 * corresponding device driver registers for this IRQ.
1976 */
1978 memset(&entry,0,sizeof(entry));
1980 entry.delivery_mode = INT_DELIVERY_MODE;
1981 entry.dest_mode = INT_DEST_MODE;
1982 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1983 entry.trigger = edge_level;
1984 entry.polarity = active_high_low;
1985 entry.mask = 1;
1987 /*
1988 * IRQs < 16 are already in the irq_2_pin[] map
1989 */
1990 if (irq >= 16)
1991 add_pin_to_irq(irq, ioapic, pin);
1993 entry.vector = assign_irq_vector(irq);
1995 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
1996 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
1997 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1998 edge_level, active_high_low);
2000 ioapic_register_intr(irq, entry.vector, edge_level);
2002 if (!ioapic && (irq < 16))
2003 disable_8259A_irq(irq);
2005 spin_lock_irqsave(&ioapic_lock, flags);
2006 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2007 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2008 set_native_irq_info(entry.vector, TARGET_CPUS);
2009 spin_unlock_irqrestore(&ioapic_lock, flags);
2011 return 0;
2014 #endif /*CONFIG_ACPI_BOOT*/
2016 static int ioapic_physbase_to_id(unsigned long physbase)
2018 int apic;
2019 for ( apic = 0; apic < nr_ioapics; apic++ )
2020 if ( mp_ioapics[apic].mpc_apicaddr == physbase )
2021 return apic;
2022 return -EINVAL;
2025 int ioapic_guest_read(unsigned long physbase, unsigned int reg, u32 *pval)
2027 int apic;
2028 unsigned long flags;
2030 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2031 return apic;
2033 spin_lock_irqsave(&ioapic_lock, flags);
2034 *pval = io_apic_read(apic, reg);
2035 spin_unlock_irqrestore(&ioapic_lock, flags);
2037 return 0;
2040 #define WARN_BOGUS_WRITE(f, a...) \
2041 dprintk(XENLOG_INFO, "\n%s: " \
2042 "apic=%d, pin=%d, old_irq=%d, new_irq=%d\n" \
2043 "%s: old_entry=%08x, new_entry=%08x\n" \
2044 "%s: " f, __FUNCTION__, apic, pin, old_irq, new_irq, \
2045 __FUNCTION__, *(u32 *)&old_rte, *(u32 *)&new_rte, \
2046 __FUNCTION__ , ##a )
2048 int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val)
2050 int apic, pin, old_irq = -1, new_irq = -1;
2051 struct IO_APIC_route_entry old_rte = { 0 }, new_rte = { 0 };
2052 unsigned long flags;
2054 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2055 return apic;
2057 /* Only write to the first half of a route entry. */
2058 if ( (reg < 0x10) || (reg & 1) )
2059 return 0;
2061 pin = (reg - 0x10) >> 1;
2063 /* Write first half from guest; second half is target info. */
2064 *(u32 *)&new_rte = val;
2065 new_rte.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2067 /*
2068 * What about weird destination types?
2069 * SMI: Ignore? Ought to be set up by the BIOS.
2070 * NMI: Ignore? Watchdog functionality is Xen's concern.
2071 * INIT: Definitely ignore: probably a guest OS bug.
2072 * ExtINT: Ignore? Linux only asserts this at start of day.
2073 * For now, print a message and return an error. We can fix up on demand.
2074 */
2075 if ( new_rte.delivery_mode > dest_LowestPrio )
2077 printk("ERROR: Attempt to write weird IOAPIC destination mode!\n");
2078 printk(" APIC=%d/%d, lo-reg=%x\n", apic, pin, val);
2079 return -EINVAL;
2082 /*
2083 * The guest does not know physical APIC arrangement (flat vs. cluster).
2084 * Apply genapic conventions for this platform.
2085 */
2086 new_rte.delivery_mode = INT_DELIVERY_MODE;
2087 new_rte.dest_mode = INT_DEST_MODE;
2089 spin_lock_irqsave(&ioapic_lock, flags);
2091 /* Read first (interesting) half of current routing entry. */
2092 *(u32 *)&old_rte = io_apic_read(apic, 0x10 + 2 * pin);
2094 /* No change to the first half of the routing entry? Bail quietly. */
2095 if ( *(u32 *)&old_rte == *(u32 *)&new_rte )
2097 spin_unlock_irqrestore(&ioapic_lock, flags);
2098 return 0;
2101 /* Special delivery modes (SMI,NMI,INIT,ExtInt) should have no vector. */
2102 if ( (old_rte.delivery_mode > dest_LowestPrio) && (old_rte.vector != 0) )
2104 WARN_BOGUS_WRITE("Special delivery mode %d with non-zero vector "
2105 "%02x\n", old_rte.delivery_mode, old_rte.vector);
2106 /* Nobble the vector here as it does not relate to a valid irq. */
2107 old_rte.vector = 0;
2110 if ( old_rte.vector >= FIRST_DYNAMIC_VECTOR )
2111 old_irq = vector_irq[old_rte.vector];
2112 if ( new_rte.vector >= FIRST_DYNAMIC_VECTOR )
2113 new_irq = vector_irq[new_rte.vector];
2115 if ( (old_irq != new_irq) && (old_irq >= 0) && IO_APIC_IRQ(old_irq) )
2117 if ( irq_desc[IO_APIC_VECTOR(old_irq)].action )
2119 WARN_BOGUS_WRITE("Attempt to remove IO-APIC pin of in-use IRQ!\n");
2120 spin_unlock_irqrestore(&ioapic_lock, flags);
2121 return 0;
2124 remove_pin_at_irq(old_irq, apic, pin);
2127 if ( (new_irq >= 0) && IO_APIC_IRQ(new_irq) )
2129 if ( irq_desc[IO_APIC_VECTOR(new_irq)].action )
2131 WARN_BOGUS_WRITE("Attempt to %s IO-APIC pin for in-use IRQ!\n",
2132 (old_irq != new_irq) ? "add" : "modify");
2133 spin_unlock_irqrestore(&ioapic_lock, flags);
2134 return 0;
2137 /* Set the correct irq-handling type. */
2138 irq_desc[IO_APIC_VECTOR(new_irq)].handler = new_rte.trigger ?
2139 &ioapic_level_type: &ioapic_edge_type;
2141 if ( old_irq != new_irq )
2142 add_pin_to_irq(new_irq, apic, pin);
2144 /* Mask iff level triggered. */
2145 new_rte.mask = new_rte.trigger;
2147 else if ( !new_rte.mask )
2149 /* This pin leads nowhere but the guest has not masked it. */
2150 WARN_BOGUS_WRITE("Installing bogus unmasked IO-APIC entry!\n");
2151 new_rte.mask = 1;
2155 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&new_rte) + 0));
2156 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&new_rte) + 1));
2158 spin_unlock_irqrestore(&ioapic_lock, flags);
2160 return 0;
2163 void dump_ioapic_irq_info(void)
2165 struct irq_pin_list *entry;
2166 struct IO_APIC_route_entry rte;
2167 unsigned int irq, pin, printed = 0;
2168 unsigned long flags;
2170 for ( irq = 0; irq < nr_irqs; irq++ )
2172 entry = &irq_2_pin[irq];
2173 if ( entry->pin == -1 )
2174 continue;
2176 if ( !printed++ )
2177 printk("IO-APIC interrupt information:\n");
2179 printk(" IRQ%3d Vec%3d:\n", irq, irq_to_vector(irq));
2181 for ( ; ; )
2183 pin = entry->pin;
2185 printk(" Apic 0x%02x, Pin %2d: ", entry->apic, pin);
2187 spin_lock_irqsave(&ioapic_lock, flags);
2188 *(((int *)&rte) + 0) = io_apic_read(entry->apic, 0x10 + 2 * pin);
2189 *(((int *)&rte) + 1) = io_apic_read(entry->apic, 0x11 + 2 * pin);
2190 spin_unlock_irqrestore(&ioapic_lock, flags);
2192 printk("vector=%u, delivery_mode=%u, dest_mode=%s, "
2193 "delivery_status=%d, polarity=%d, irr=%d, "
2194 "trigger=%s, mask=%d\n",
2195 rte.vector, rte.delivery_mode,
2196 rte.dest_mode ? "logical" : "physical",
2197 rte.delivery_status, rte.polarity, rte.irr,
2198 rte.trigger ? "level" : "edge", rte.mask);
2200 if ( entry->next == 0 )
2201 break;
2202 entry = &irq_2_pin[entry->next];
2207 void __init init_ioapic_mappings(void)
2209 unsigned long ioapic_phys;
2210 unsigned int i, idx = FIX_IO_APIC_BASE_0;
2211 union IO_APIC_reg_01 reg_01;
2213 if ( smp_found_config )
2214 nr_irqs = 0;
2215 for ( i = 0; i < nr_ioapics; i++ )
2217 if ( smp_found_config )
2219 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2220 if ( !ioapic_phys )
2222 printk(KERN_ERR "WARNING: bogus zero IO-APIC address "
2223 "found in MPTABLE, disabling IO/APIC support!\n");
2224 smp_found_config = 0;
2225 skip_ioapic_setup = 1;
2226 goto fake_ioapic_page;
2229 else
2231 fake_ioapic_page:
2232 ioapic_phys = __pa(alloc_xenheap_page());
2233 clear_page(__va(ioapic_phys));
2235 set_fixmap_nocache(idx, ioapic_phys);
2236 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2237 __fix_to_virt(idx), ioapic_phys);
2238 idx++;
2240 if ( smp_found_config )
2242 /* The number of IO-APIC IRQ registers (== #pins): */
2243 reg_01.raw = io_apic_read(i, 1);
2244 nr_ioapic_registers[i] = reg_01.bits.entries + 1;
2245 nr_irqs += nr_ioapic_registers[i];
2248 if ( !smp_found_config || skip_ioapic_setup || nr_irqs < 16 )
2249 nr_irqs = 16;
2250 else if ( nr_irqs > PAGE_SIZE * 8 )
2252 /* for PHYSDEVOP_pirq_eoi_gmfn guest assumptions */
2253 printk(KERN_WARNING "Limiting number of IRQs found (%u) to %lu\n",
2254 nr_irqs, PAGE_SIZE * 8);
2255 nr_irqs = PAGE_SIZE * 8;