ia64/xen-unstable

view xen/include/asm-powerpc/processor.h @ 12923:489e4d09ffb7

[XEN][POWERPC] Conistence with log vs. order
We use "log" for a log2 value, "order" is the log2 of page size, so:
order = log - PAGE_SHIFT
It is confusing, but more so if we are not consistent.
Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Jimi Xenidis <jimix@watson.ibm.com>
date Fri Sep 29 09:53:39 2006 -0400 (2006-09-29)
parents ae1f00361a8e
children 176c7264715c
line source
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 *
16 * Copyright (C) IBM Corp. 2005, 2006
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
21 #ifndef _ASM_PROCESSOR_H_
22 #define _ASM_PROCESSOR_H_
24 #include <xen/config.h>
25 #include <asm/reg_defs.h>
26 #include <asm/msr.h>
28 #define IOBMP_BYTES 8192
29 #define IOBMP_INVALID_OFFSET 0x8000
31 /* most assembler do not know this instruction */
32 #define HRFID .long 0x4c000224
34 /* Processor Version Register (PVR) field extraction */
36 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
37 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
39 #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
41 /*
42 * IBM has further subdivided the standard PowerPC 16-bit version and
43 * revision subfields of the PVR for the PowerPC 403s into the following:
44 */
46 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
47 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
48 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
49 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
50 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
51 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
53 /* Processor Version Numbers */
55 #define PVR_403GA 0x00200000
56 #define PVR_403GB 0x00200100
57 #define PVR_403GC 0x00200200
58 #define PVR_403GCX 0x00201400
59 #define PVR_405GP 0x40110000
60 #define PVR_STB03XXX 0x40310000
61 #define PVR_NP405H 0x41410000
62 #define PVR_NP405L 0x41610000
63 #define PVR_601 0x00010000
64 #define PVR_602 0x00050000
65 #define PVR_603 0x00030000
66 #define PVR_603e 0x00060000
67 #define PVR_603ev 0x00070000
68 #define PVR_603r 0x00071000
69 #define PVR_604 0x00040000
70 #define PVR_604e 0x00090000
71 #define PVR_604r 0x000A0000
72 #define PVR_620 0x00140000
73 #define PVR_740 0x00080000
74 #define PVR_750 PVR_740
75 #define PVR_740P 0x10080000
76 #define PVR_750P PVR_740P
77 #define PVR_7400 0x000C0000
78 #define PVR_7410 0x800C0000
79 #define PVR_7450 0x80000000
80 #define PVR_8540 0x80200000
81 #define PVR_8560 0x80200000
82 /*
83 * For the 8xx processors, all of them report the same PVR family for
84 * the PowerPC core. The various versions of these processors must be
85 * differentiated by the version number in the Communication Processor
86 * Module (CPM).
87 */
88 #define PVR_821 0x00500000
89 #define PVR_823 PVR_821
90 #define PVR_850 PVR_821
91 #define PVR_860 PVR_821
92 #define PVR_8240 0x00810100
93 #define PVR_8245 0x80811014
94 #define PVR_8260 PVR_8240
96 /* 64-bit processors */
97 /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
98 #define PV_NORTHSTAR 0x0033
99 #define PV_PULSAR 0x0034
100 #define PV_POWER4 0x0035
101 #define PV_ICESTAR 0x0036
102 #define PV_SSTAR 0x0037
103 #define PV_POWER4p 0x0038
104 #define PV_970 0x0039
105 #define PV_POWER5 0x003A
106 #define PV_POWER5p 0x003B
107 #define PV_970FX 0x003C
108 #define PV_630 0x0040
109 #define PV_630p 0x0041
110 #define PV_970MP 0x0044
111 #define PV_BE 0x0070
113 #ifndef __ASSEMBLY__
114 #include <xen/types.h>
116 struct domain;
117 struct vcpu;
118 struct cpu_user_regs;
119 extern int cpu_machinecheck(struct cpu_user_regs *);
120 extern void show_registers(struct cpu_user_regs *);
121 extern unsigned int cpu_extent_order(void);
122 extern unsigned int cpu_default_rma_order_pages(void);
123 extern int cpu_rma_valid(unsigned int order);
124 extern uint cpu_large_page_orders(uint *sizes, uint max);
125 extern void cpu_initialize(int cpuid);
126 extern void cpu_init_vcpu(struct vcpu *);
127 extern int cpu_io_mfn(ulong mfn);
128 extern void save_cpu_sprs(struct vcpu *);
129 extern void load_cpu_sprs(struct vcpu *);
130 extern void flush_segments(void);
131 extern void dump_segments(int valid);
133 #define ARCH_HAS_PREFETCH
134 static inline void prefetch(const void *x) {;}
136 static __inline__ void sync(void)
137 {
138 __asm__ __volatile__ ("sync");
139 }
141 static __inline__ void isync(void)
142 {
143 __asm__ __volatile__ ("isync");
144 }
146 static inline ulong mfmsr(void) {
147 ulong msr;
148 __asm__ __volatile__ ("mfmsr %0" : "=&r"(msr));
149 return msr;
150 }
152 static inline void nop(void) {
153 __asm__ __volatile__ ("nop");
154 }
155 #define cpu_relax() nop()
157 static inline unsigned int mfpir(void)
158 {
159 unsigned int pir;
160 __asm__ __volatile__ ("mfspr %0, %1" : "=r" (pir): "i"(SPRN_PIR));
161 return pir;
162 }
164 static inline unsigned int mftbu(void)
165 {
166 unsigned int tbu;
167 __asm__ __volatile__ ("mftbu %0" : "=r" (tbu));
168 return tbu;
169 }
171 static inline unsigned int mftbl(void)
172 {
173 unsigned int tbl;
174 __asm__ __volatile__ ("mftbl %0" : "=r" (tbl));
175 return tbl;
176 }
178 static inline unsigned int mfdec(void)
179 {
180 unsigned int tmp;
181 __asm__ __volatile__ ("mfdec %0" : "=r"(tmp));
182 return tmp;
183 }
184 static inline void mtdec(unsigned int ticks)
185 {
186 __asm__ __volatile__ ("mtdec %0" : : "r" (ticks));
187 }
189 static inline u32 mfpvr(void) {
190 u32 pvr;
191 asm volatile("mfpvr %0" : "=&r" (pvr));
192 return pvr;
193 }
195 static inline ulong mfr1(void)
196 {
197 ulong r1;
198 asm volatile("mr %0, 1" : "=&r" (r1));
199 return r1;
200 }
202 static inline void mtsprg0(ulong val)
203 {
204 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG0), "r"(val));
205 }
206 static inline ulong mfsprg0(void)
207 {
208 ulong val;
209 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG0));
210 return val;
211 }
213 static inline void mtsprg1(ulong val)
214 {
215 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG1), "r"(val));
216 }
217 static inline ulong mfsprg1(void)
218 {
219 ulong val;
220 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG1));
221 return val;
222 }
224 static inline void mtsprg2(ulong val)
225 {
226 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG2), "r"(val));
227 }
228 static inline ulong mfsprg2(void)
229 {
230 ulong val;
231 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG2));
232 return val;
233 }
235 static inline void mtsprg3(ulong val)
236 {
237 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG3), "r"(val));
238 }
239 static inline ulong mfsprg3(void)
240 {
241 ulong val;
242 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG3));
243 return val;
244 }
246 static inline void mtsdr1(ulong val)
247 {
248 __asm__ __volatile__ ("mtsdr1 %0" : : "r"(val));
249 }
250 static inline ulong mfsdr1(void)
251 {
252 ulong val;
253 __asm__ __volatile__ ("mfsdr1 %0" : "=r"(val));
254 return val;
255 }
257 static inline void mtdar(ulong val)
258 {
259 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_DAR), "r"(val));
260 }
261 static inline ulong mfdar(void)
262 {
263 ulong val;
264 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_DAR));
265 return val;
266 }
268 static inline void mtdsisr(ulong val)
269 {
270 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_DSISR), "r"(val));
271 }
272 static inline unsigned mfdsisr(void)
273 {
274 unsigned val;
275 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_DSISR));
276 return val;
277 }
279 #ifdef CONFIG_MAMBO
280 static inline int on_mambo(void)
281 {
282 return !!(mfmsr() & MSR_MAMBO);
283 }
284 #else /* CONFIG_MAMBO */
285 static inline int on_mambo(void) { return 0; }
286 #endif
288 #endif /* __ASSEMBLY__ */
290 #include <asm/powerpc64/processor.h>
292 #endif