ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/kernel/setup.c @ 10705:47fc48740d45

[IA64] Support domU coredump on ia64

This patch supports domU coredump on ia64. xen_panic_event() is
registered to panic_notifier_list, and xen_panic_event() calls
HYPERVISOR_shutdown(SHUTDOWN_crash) at panic time.

If xend is notified of crash status, xend calls dumpCore()
and create domU's core in /var/xen/dump.

For sample crash module and usage, see:

http://lists.xensource.com/archives/html/xen-ia64-devel/2006-07/msg00230.html

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
[minor code re-arrangement]
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild.aw
date Mon Jul 24 14:26:03 2006 -0600 (2006-07-24)
parents 8dc4af3f192c
children 29ef650eb22a d8338b28bcd6
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/platform.h>
45 #include <linux/pm.h>
46 #include <linux/cpufreq.h>
48 #include <asm/ia32.h>
49 #include <asm/machvec.h>
50 #include <asm/mca.h>
51 #include <asm/meminit.h>
52 #include <asm/page.h>
53 #include <asm/patch.h>
54 #include <asm/pgtable.h>
55 #include <asm/processor.h>
56 #include <asm/sal.h>
57 #include <asm/sections.h>
58 #include <asm/serial.h>
59 #include <asm/setup.h>
60 #include <asm/smp.h>
61 #include <asm/system.h>
62 #include <asm/unistd.h>
63 #include <asm/system.h>
64 #ifdef CONFIG_XEN
65 #include <asm/hypervisor.h>
66 #endif
67 #include <linux/dma-mapping.h>
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 #ifdef CONFIG_XEN
79 static int
80 xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
81 {
82 HYPERVISOR_shutdown(SHUTDOWN_crash);
83 /* we're never actually going to get here... */
84 return NOTIFY_DONE;
85 }
87 static struct notifier_block xen_panic_block = {
88 xen_panic_event, NULL, 0 /* try to go last */
89 };
90 #endif
92 extern void ia64_setup_printk_clock(void);
94 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
95 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
96 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
97 unsigned long ia64_cycles_per_usec;
98 struct ia64_boot_param *ia64_boot_param;
99 struct screen_info screen_info;
100 unsigned long vga_console_iobase;
101 unsigned long vga_console_membase;
103 static struct resource data_resource = {
104 .name = "Kernel data",
105 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
106 };
108 static struct resource code_resource = {
109 .name = "Kernel code",
110 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
111 };
112 extern void efi_initialize_iomem_resources(struct resource *,
113 struct resource *);
114 extern char _text[], _end[], _etext[];
116 unsigned long ia64_max_cacheline_size;
118 int dma_get_cache_alignment(void)
119 {
120 return ia64_max_cacheline_size;
121 }
122 EXPORT_SYMBOL(dma_get_cache_alignment);
124 unsigned long ia64_iobase; /* virtual address for I/O accesses */
125 EXPORT_SYMBOL(ia64_iobase);
126 struct io_space io_space[MAX_IO_SPACES];
127 EXPORT_SYMBOL(io_space);
128 unsigned int num_io_spaces;
130 /*
131 * "flush_icache_range()" needs to know what processor dependent stride size to use
132 * when it makes i-cache(s) coherent with d-caches.
133 */
134 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
135 unsigned long ia64_i_cache_stride_shift = ~0;
137 /*
138 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
139 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
140 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
141 * address of the second buffer must be aligned to (merge_mask+1) in order to be
142 * mergeable). By default, we assume there is no I/O MMU which can merge physically
143 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
144 * page-size of 2^64.
145 */
146 unsigned long ia64_max_iommu_merge_mask = ~0UL;
147 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
149 /*
150 * We use a special marker for the end of memory and it uses the extra (+1) slot
151 */
152 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
153 int num_rsvd_regions;
156 /*
157 * Filter incoming memory segments based on the primitive map created from the boot
158 * parameters. Segments contained in the map are removed from the memory ranges. A
159 * caller-specified function is called with the memory ranges that remain after filtering.
160 * This routine does not assume the incoming segments are sorted.
161 */
162 int
163 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
164 {
165 unsigned long range_start, range_end, prev_start;
166 void (*func)(unsigned long, unsigned long, int);
167 int i;
169 #if IGNORE_PFN0
170 if (start == PAGE_OFFSET) {
171 printk(KERN_WARNING "warning: skipping physical page 0\n");
172 start += PAGE_SIZE;
173 if (start >= end) return 0;
174 }
175 #endif
176 /*
177 * lowest possible address(walker uses virtual)
178 */
179 prev_start = PAGE_OFFSET;
180 func = arg;
182 for (i = 0; i < num_rsvd_regions; ++i) {
183 range_start = max(start, prev_start);
184 range_end = min(end, rsvd_region[i].start);
186 if (range_start < range_end)
187 call_pernode_memory(__pa(range_start), range_end - range_start, func);
189 /* nothing more available in this segment */
190 if (range_end == end) return 0;
192 prev_start = rsvd_region[i].end;
193 }
194 /* end of memory marker allows full processing inside loop body */
195 return 0;
196 }
198 static void
199 sort_regions (struct rsvd_region *rsvd_region, int max)
200 {
201 int j;
203 /* simple bubble sorting */
204 while (max--) {
205 for (j = 0; j < max; ++j) {
206 if (rsvd_region[j].start > rsvd_region[j+1].start) {
207 struct rsvd_region tmp;
208 tmp = rsvd_region[j];
209 rsvd_region[j] = rsvd_region[j + 1];
210 rsvd_region[j + 1] = tmp;
211 }
212 }
213 }
214 }
216 /*
217 * Request address space for all standard resources
218 */
219 static int __init register_memory(void)
220 {
221 code_resource.start = ia64_tpa(_text);
222 code_resource.end = ia64_tpa(_etext) - 1;
223 data_resource.start = ia64_tpa(_etext);
224 data_resource.end = ia64_tpa(_end) - 1;
225 efi_initialize_iomem_resources(&code_resource, &data_resource);
227 return 0;
228 }
230 __initcall(register_memory);
232 /**
233 * reserve_memory - setup reserved memory areas
234 *
235 * Setup the reserved memory areas set aside for the boot parameters,
236 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
237 * see include/asm-ia64/meminit.h if you need to define more.
238 */
239 void
240 reserve_memory (void)
241 {
242 int n = 0;
244 /*
245 * none of the entries in this table overlap
246 */
247 rsvd_region[n].start = (unsigned long) ia64_boot_param;
248 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
249 n++;
251 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
252 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
253 n++;
255 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
256 rsvd_region[n].end = (rsvd_region[n].start
257 + strlen(__va(ia64_boot_param->command_line)) + 1);
258 n++;
260 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
261 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
262 n++;
264 #ifdef CONFIG_XEN
265 if (is_running_on_xen()) {
266 rsvd_region[n].start = (unsigned long)__va((HYPERVISOR_shared_info->arch.start_info_pfn << PAGE_SHIFT));
267 rsvd_region[n].end = rsvd_region[n].start + PAGE_SIZE;
268 n++;
269 }
270 #endif
272 #ifdef CONFIG_BLK_DEV_INITRD
273 if (ia64_boot_param->initrd_start) {
274 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
275 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
276 n++;
277 }
278 #endif
280 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
281 n++;
283 /* end of memory marker */
284 rsvd_region[n].start = ~0UL;
285 rsvd_region[n].end = ~0UL;
286 n++;
288 num_rsvd_regions = n;
289 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
291 sort_regions(rsvd_region, num_rsvd_regions);
292 }
294 /**
295 * find_initrd - get initrd parameters from the boot parameter structure
296 *
297 * Grab the initrd start and end from the boot parameter struct given us by
298 * the boot loader.
299 */
300 void
301 find_initrd (void)
302 {
303 #ifdef CONFIG_BLK_DEV_INITRD
304 if (ia64_boot_param->initrd_start) {
305 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
306 initrd_end = initrd_start+ia64_boot_param->initrd_size;
308 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
309 initrd_start, ia64_boot_param->initrd_size);
310 }
311 #endif
312 }
314 static void __init
315 io_port_init (void)
316 {
317 unsigned long phys_iobase;
319 /*
320 * Set `iobase' based on the EFI memory map or, failing that, the
321 * value firmware left in ar.k0.
322 *
323 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
324 * the port's virtual address, so ia32_load_state() loads it with a
325 * user virtual address. But in ia64 mode, glibc uses the
326 * *physical* address in ar.k0 to mmap the appropriate area from
327 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
328 * cases, user-mode can only use the legacy 0-64K I/O port space.
329 *
330 * ar.k0 is not involved in kernel I/O port accesses, which can use
331 * any of the I/O port spaces and are done via MMIO using the
332 * virtual mmio_base from the appropriate io_space[].
333 */
334 phys_iobase = efi_get_iobase();
335 if (!phys_iobase) {
336 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
337 printk(KERN_INFO "No I/O port range found in EFI memory map, "
338 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
339 }
340 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
341 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
343 /* setup legacy IO port space */
344 io_space[0].mmio_base = ia64_iobase;
345 io_space[0].sparse = 1;
346 num_io_spaces = 1;
347 }
349 /**
350 * early_console_setup - setup debugging console
351 *
352 * Consoles started here require little enough setup that we can start using
353 * them very early in the boot process, either right after the machine
354 * vector initialization, or even before if the drivers can detect their hw.
355 *
356 * Returns non-zero if a console couldn't be setup.
357 */
358 static inline int __init
359 early_console_setup (char *cmdline)
360 {
361 int earlycons = 0;
363 #ifdef CONFIG_XEN
364 #ifndef CONFIG_IA64_HP_SIM
365 if (is_running_on_xen()) {
366 extern struct console hpsim_cons;
367 hpsim_cons.flags |= CON_BOOT;
368 register_console(&hpsim_cons);
369 earlycons++;
370 }
371 #endif
372 #endif
373 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
374 {
375 extern int sn_serial_console_early_setup(void);
376 if (!sn_serial_console_early_setup())
377 earlycons++;
378 }
379 #endif
380 #ifdef CONFIG_EFI_PCDP
381 if (!efi_setup_pcdp_console(cmdline))
382 earlycons++;
383 #endif
384 #ifdef CONFIG_SERIAL_8250_CONSOLE
385 if (!early_serial_console_init(cmdline))
386 earlycons++;
387 #endif
389 return (earlycons) ? 0 : -1;
390 }
392 static inline void
393 mark_bsp_online (void)
394 {
395 #ifdef CONFIG_SMP
396 /* If we register an early console, allow CPU 0 to printk */
397 cpu_set(smp_processor_id(), cpu_online_map);
398 #endif
399 }
401 #ifdef CONFIG_SMP
402 static void
403 check_for_logical_procs (void)
404 {
405 pal_logical_to_physical_t info;
406 s64 status;
408 status = ia64_pal_logical_to_phys(0, &info);
409 if (status == -1) {
410 printk(KERN_INFO "No logical to physical processor mapping "
411 "available\n");
412 return;
413 }
414 if (status) {
415 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
416 status);
417 return;
418 }
419 /*
420 * Total number of siblings that BSP has. Though not all of them
421 * may have booted successfully. The correct number of siblings
422 * booted is in info.overview_num_log.
423 */
424 smp_num_siblings = info.overview_tpc;
425 smp_num_cpucores = info.overview_cpp;
426 }
427 #endif
429 void __init
430 setup_arch (char **cmdline_p)
431 {
432 unw_init();
434 #ifdef CONFIG_XEN
435 if (is_running_on_xen()) {
436 setup_xen_features();
437 /* Register a call for panic conditions. */
438 notifier_chain_register(&panic_notifier_list, &xen_panic_block);
439 }
440 #endif
442 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
444 *cmdline_p = __va(ia64_boot_param->command_line);
445 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
447 efi_init();
448 io_port_init();
450 #ifdef CONFIG_IA64_GENERIC
451 {
452 const char *mvec_name = strstr (*cmdline_p, "machvec=");
453 char str[64];
455 if (mvec_name) {
456 const char *end;
457 size_t len;
459 mvec_name += 8;
460 end = strchr (mvec_name, ' ');
461 if (end)
462 len = end - mvec_name;
463 else
464 len = strlen (mvec_name);
465 len = min(len, sizeof (str) - 1);
466 strncpy (str, mvec_name, len);
467 str[len] = '\0';
468 mvec_name = str;
469 } else
470 mvec_name = acpi_get_sysname();
471 machvec_init(mvec_name);
472 }
473 #endif
475 if (early_console_setup(*cmdline_p) == 0)
476 mark_bsp_online();
478 parse_early_param();
479 #ifdef CONFIG_ACPI
480 /* Initialize the ACPI boot-time table parser */
481 acpi_table_init();
482 # ifdef CONFIG_ACPI_NUMA
483 acpi_numa_init();
484 # endif
485 #else
486 # ifdef CONFIG_SMP
487 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
488 # endif
489 #endif /* CONFIG_APCI_BOOT */
491 find_memory();
493 /* process SAL system table: */
494 ia64_sal_init(efi.sal_systab);
496 ia64_setup_printk_clock();
498 #ifdef CONFIG_SMP
499 cpu_physical_id(0) = hard_smp_processor_id();
501 cpu_set(0, cpu_sibling_map[0]);
502 cpu_set(0, cpu_core_map[0]);
504 check_for_logical_procs();
505 if (smp_num_cpucores > 1)
506 printk(KERN_INFO
507 "cpu package is Multi-Core capable: number of cores=%d\n",
508 smp_num_cpucores);
509 if (smp_num_siblings > 1)
510 printk(KERN_INFO
511 "cpu package is Multi-Threading capable: number of siblings=%d\n",
512 smp_num_siblings);
513 #endif
515 cpu_init(); /* initialize the bootstrap CPU */
516 mmu_context_init(); /* initialize context_id bitmap */
518 #ifdef CONFIG_ACPI
519 acpi_boot_init();
520 #endif
522 #ifdef CONFIG_VT
523 if (!conswitchp) {
524 # if defined(CONFIG_DUMMY_CONSOLE)
525 conswitchp = &dummy_con;
526 # endif
527 # if defined(CONFIG_VGA_CONSOLE)
528 /*
529 * Non-legacy systems may route legacy VGA MMIO range to system
530 * memory. vga_con probes the MMIO hole, so memory looks like
531 * a VGA device to it. The EFI memory map can tell us if it's
532 * memory so we can avoid this problem.
533 */
534 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
535 conswitchp = &vga_con;
536 # endif
537 }
538 #ifdef CONFIG_XEN
539 if (is_running_on_xen()) {
540 shared_info_t *s = HYPERVISOR_shared_info;
542 xen_start_info = __va(s->arch.start_info_pfn << PAGE_SHIFT);
544 printk("Running on Xen! start_info_pfn=0x%lx nr_pages=%ld "
545 "flags=0x%x\n", s->arch.start_info_pfn,
546 xen_start_info->nr_pages, xen_start_info->flags);
548 /* xen_start_info isn't setup yet, get the flags manually */
549 if (xen_start_info->flags & SIF_INITDOMAIN) {
550 if (!(xen_start_info->flags & SIF_PRIVILEGED))
551 panic("Xen granted us console access "
552 "but not privileged status");
553 } else {
554 extern int console_use_vt;
555 conswitchp = NULL;
556 console_use_vt = 0;
557 }
558 }
559 #endif
560 #endif
562 /* enable IA-64 Machine Check Abort Handling unless disabled */
563 if (!strstr(saved_command_line, "nomca"))
564 ia64_mca_init();
566 platform_setup(cmdline_p);
567 paging_init();
568 contiguous_bitmap_init(max_pfn);
569 }
571 /*
572 * Display cpu info for all cpu's.
573 */
574 static int
575 show_cpuinfo (struct seq_file *m, void *v)
576 {
577 #ifdef CONFIG_SMP
578 # define lpj c->loops_per_jiffy
579 # define cpunum c->cpu
580 #else
581 # define lpj loops_per_jiffy
582 # define cpunum 0
583 #endif
584 static struct {
585 unsigned long mask;
586 const char *feature_name;
587 } feature_bits[] = {
588 { 1UL << 0, "branchlong" },
589 { 1UL << 1, "spontaneous deferral"},
590 { 1UL << 2, "16-byte atomic ops" }
591 };
592 char family[32], features[128], *cp, sep;
593 struct cpuinfo_ia64 *c = v;
594 unsigned long mask;
595 unsigned long proc_freq;
596 int i;
598 mask = c->features;
600 switch (c->family) {
601 case 0x07: memcpy(family, "Itanium", 8); break;
602 case 0x1f: memcpy(family, "Itanium 2", 10); break;
603 default: sprintf(family, "%u", c->family); break;
604 }
606 /* build the feature string: */
607 memcpy(features, " standard", 10);
608 cp = features;
609 sep = 0;
610 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
611 if (mask & feature_bits[i].mask) {
612 if (sep)
613 *cp++ = sep;
614 sep = ',';
615 *cp++ = ' ';
616 strcpy(cp, feature_bits[i].feature_name);
617 cp += strlen(feature_bits[i].feature_name);
618 mask &= ~feature_bits[i].mask;
619 }
620 }
621 if (mask) {
622 /* print unknown features as a hex value: */
623 if (sep)
624 *cp++ = sep;
625 sprintf(cp, " 0x%lx", mask);
626 }
628 proc_freq = cpufreq_quick_get(cpunum);
629 if (!proc_freq)
630 proc_freq = c->proc_freq / 1000;
632 seq_printf(m,
633 "processor : %d\n"
634 "vendor : %s\n"
635 "arch : IA-64\n"
636 "family : %s\n"
637 "model : %u\n"
638 "revision : %u\n"
639 "archrev : %u\n"
640 "features :%s\n" /* don't change this---it _is_ right! */
641 "cpu number : %lu\n"
642 "cpu regs : %u\n"
643 "cpu MHz : %lu.%06lu\n"
644 "itc MHz : %lu.%06lu\n"
645 "BogoMIPS : %lu.%02lu\n",
646 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
647 features, c->ppn, c->number,
648 proc_freq / 1000, proc_freq % 1000,
649 c->itc_freq / 1000000, c->itc_freq % 1000000,
650 lpj*HZ/500000, (lpj*HZ/5000) % 100);
651 #ifdef CONFIG_SMP
652 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
653 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
654 seq_printf(m,
655 "physical id: %u\n"
656 "core id : %u\n"
657 "thread id : %u\n",
658 c->socket_id, c->core_id, c->thread_id);
659 #endif
660 seq_printf(m,"\n");
662 return 0;
663 }
665 static void *
666 c_start (struct seq_file *m, loff_t *pos)
667 {
668 #ifdef CONFIG_SMP
669 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
670 ++*pos;
671 #endif
672 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
673 }
675 static void *
676 c_next (struct seq_file *m, void *v, loff_t *pos)
677 {
678 ++*pos;
679 return c_start(m, pos);
680 }
682 static void
683 c_stop (struct seq_file *m, void *v)
684 {
685 }
687 struct seq_operations cpuinfo_op = {
688 .start = c_start,
689 .next = c_next,
690 .stop = c_stop,
691 .show = show_cpuinfo
692 };
694 void
695 identify_cpu (struct cpuinfo_ia64 *c)
696 {
697 union {
698 unsigned long bits[5];
699 struct {
700 /* id 0 & 1: */
701 char vendor[16];
703 /* id 2 */
704 u64 ppn; /* processor serial number */
706 /* id 3: */
707 unsigned number : 8;
708 unsigned revision : 8;
709 unsigned model : 8;
710 unsigned family : 8;
711 unsigned archrev : 8;
712 unsigned reserved : 24;
714 /* id 4: */
715 u64 features;
716 } field;
717 } cpuid;
718 pal_vm_info_1_u_t vm1;
719 pal_vm_info_2_u_t vm2;
720 pal_status_t status;
721 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
722 int i;
724 for (i = 0; i < 5; ++i)
725 cpuid.bits[i] = ia64_get_cpuid(i);
727 memcpy(c->vendor, cpuid.field.vendor, 16);
728 #ifdef CONFIG_SMP
729 c->cpu = smp_processor_id();
731 /* below default values will be overwritten by identify_siblings()
732 * for Multi-Threading/Multi-Core capable cpu's
733 */
734 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
735 c->socket_id = -1;
737 identify_siblings(c);
738 #endif
739 c->ppn = cpuid.field.ppn;
740 c->number = cpuid.field.number;
741 c->revision = cpuid.field.revision;
742 c->model = cpuid.field.model;
743 c->family = cpuid.field.family;
744 c->archrev = cpuid.field.archrev;
745 c->features = cpuid.field.features;
747 status = ia64_pal_vm_summary(&vm1, &vm2);
748 if (status == PAL_STATUS_SUCCESS) {
749 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
750 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
751 }
752 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
753 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
754 }
756 void
757 setup_per_cpu_areas (void)
758 {
759 /* start_kernel() requires this... */
760 #ifdef CONFIG_ACPI_HOTPLUG_CPU
761 prefill_possible_map();
762 #endif
763 }
765 /*
766 * Calculate the max. cache line size.
767 *
768 * In addition, the minimum of the i-cache stride sizes is calculated for
769 * "flush_icache_range()".
770 */
771 static void
772 get_max_cacheline_size (void)
773 {
774 unsigned long line_size, max = 1;
775 unsigned int cache_size = 0;
776 u64 l, levels, unique_caches;
777 pal_cache_config_info_t cci;
778 s64 status;
780 status = ia64_pal_cache_summary(&levels, &unique_caches);
781 if (status != 0) {
782 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
783 __FUNCTION__, status);
784 max = SMP_CACHE_BYTES;
785 /* Safest setup for "flush_icache_range()" */
786 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
787 goto out;
788 }
790 for (l = 0; l < levels; ++l) {
791 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
792 &cci);
793 if (status != 0) {
794 printk(KERN_ERR
795 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
796 __FUNCTION__, l, status);
797 max = SMP_CACHE_BYTES;
798 /* The safest setup for "flush_icache_range()" */
799 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
800 cci.pcci_unified = 1;
801 }
802 line_size = 1 << cci.pcci_line_size;
803 if (line_size > max)
804 max = line_size;
805 if (cache_size < cci.pcci_cache_size)
806 cache_size = cci.pcci_cache_size;
807 if (!cci.pcci_unified) {
808 status = ia64_pal_cache_config_info(l,
809 /* cache_type (instruction)= */ 1,
810 &cci);
811 if (status != 0) {
812 printk(KERN_ERR
813 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
814 __FUNCTION__, l, status);
815 /* The safest setup for "flush_icache_range()" */
816 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
817 }
818 }
819 if (cci.pcci_stride < ia64_i_cache_stride_shift)
820 ia64_i_cache_stride_shift = cci.pcci_stride;
821 }
822 out:
823 #ifdef CONFIG_SMP
824 max_cache_size = max(max_cache_size, cache_size);
825 #endif
826 if (max > ia64_max_cacheline_size)
827 ia64_max_cacheline_size = max;
828 }
830 /*
831 * cpu_init() initializes state that is per-CPU. This function acts
832 * as a 'CPU state barrier', nothing should get across.
833 */
834 void
835 cpu_init (void)
836 {
837 extern void __devinit ia64_mmu_init (void *);
838 unsigned long num_phys_stacked;
839 pal_vm_info_2_u_t vmi;
840 unsigned int max_ctx;
841 struct cpuinfo_ia64 *cpu_info;
842 void *cpu_data;
844 cpu_data = per_cpu_init();
846 /*
847 * We set ar.k3 so that assembly code in MCA handler can compute
848 * physical addresses of per cpu variables with a simple:
849 * phys = ar.k3 + &per_cpu_var
850 */
851 ia64_set_kr(IA64_KR_PER_CPU_DATA,
852 ia64_tpa(cpu_data) - (long) __per_cpu_start);
854 get_max_cacheline_size();
856 /*
857 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
858 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
859 * depends on the data returned by identify_cpu(). We break the dependency by
860 * accessing cpu_data() through the canonical per-CPU address.
861 */
862 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
863 identify_cpu(cpu_info);
865 #ifdef CONFIG_MCKINLEY
866 {
867 # define FEATURE_SET 16
868 struct ia64_pal_retval iprv;
870 if (cpu_info->family == 0x1f) {
871 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
872 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
873 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
874 (iprv.v1 | 0x80), FEATURE_SET, 0);
875 }
876 }
877 #endif
879 /* Clear the stack memory reserved for pt_regs: */
880 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
882 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
884 /*
885 * Initialize the page-table base register to a global
886 * directory with all zeroes. This ensure that we can handle
887 * TLB-misses to user address-space even before we created the
888 * first user address-space. This may happen, e.g., due to
889 * aggressive use of lfetch.fault.
890 */
891 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
893 /*
894 * Initialize default control register to defer speculative faults except
895 * for those arising from TLB misses, which are not deferred. The
896 * kernel MUST NOT depend on a particular setting of these bits (in other words,
897 * the kernel must have recovery code for all speculative accesses). Turn on
898 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
899 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
900 * be fine).
901 */
902 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
903 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
904 atomic_inc(&init_mm.mm_count);
905 current->active_mm = &init_mm;
906 if (current->mm)
907 BUG();
909 ia64_mmu_init(ia64_imva(cpu_data));
910 ia64_mca_cpu_init(ia64_imva(cpu_data));
912 #ifdef CONFIG_IA32_SUPPORT
913 ia32_cpu_init();
914 #endif
916 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
917 ia64_set_itc(0);
919 /* disable all local interrupt sources: */
920 ia64_set_itv(1 << 16);
921 ia64_set_lrr0(1 << 16);
922 ia64_set_lrr1(1 << 16);
923 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
924 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
926 /* clear TPR & XTP to enable all interrupt classes: */
927 ia64_setreg(_IA64_REG_CR_TPR, 0);
928 #ifdef CONFIG_SMP
929 normal_xtp();
930 #endif
932 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
933 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
934 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
935 else {
936 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
937 max_ctx = (1U << 15) - 1; /* use architected minimum */
938 }
939 while (max_ctx < ia64_ctx.max_ctx) {
940 unsigned int old = ia64_ctx.max_ctx;
941 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
942 break;
943 }
945 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
946 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
947 "stacked regs\n");
948 num_phys_stacked = 96;
949 }
950 /* size of physical stacked register partition plus 8 bytes: */
951 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
952 platform_cpu_init();
954 #ifdef CONFIG_XEN
955 /* Need to be moved into platform_cpu_init later */
956 if (is_running_on_xen()) {
957 extern void xen_smp_intr_init(void);
958 xen_smp_intr_init();
959 }
960 #endif
962 pm_idle = default_idle;
963 }
965 /*
966 * On SMP systems, when the scheduler does migration-cost autodetection,
967 * it needs a way to flush as much of the CPU's caches as possible.
968 */
969 void sched_cacheflush(void)
970 {
971 ia64_sal_cache_flush(3);
972 }
974 void
975 check_bugs (void)
976 {
977 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
978 (unsigned long) __end___mckinley_e9_bundles);
979 }