ia64/xen-unstable

view linux-2.6-xen-sparse/arch/x86_64/kernel/mpparse-xen.c @ 13978:477a3bde3b61

linux: miscellaneous changes after upgrade through 2.6.17.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
author kfraser@localhost.localdomain
date Thu Feb 15 14:12:32 2007 +0000 (2007-02-15)
parents 3adf00179a63
children
line source
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
26 #include <asm/smp.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
32 #include <asm/acpi.h>
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
38 int acpi_found_madt;
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 unsigned char apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 static int mp_current_pci_id = 0;
49 /* I/O APIC entries */
50 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
52 /* # of MP IRQ source entries */
53 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
55 /* MP IRQ source entries */
56 int mp_irq_entries;
58 int nr_ioapics;
59 int pic_mode;
60 unsigned long mp_lapic_addr = 0;
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_id = -1U;
66 /* Internal processor count */
67 unsigned int num_processors __initdata = 0;
69 unsigned disabled_cpus __initdata;
71 /* Bitmask of physically existing CPUs */
72 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
74 /* ACPI MADT entry parsing functions */
75 #ifdef CONFIG_ACPI
76 extern struct acpi_boot_flags acpi_boot;
77 #ifdef CONFIG_X86_LOCAL_APIC
78 extern int acpi_parse_lapic (acpi_table_entry_header *header);
79 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
80 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
81 #endif /*CONFIG_X86_LOCAL_APIC*/
82 #ifdef CONFIG_X86_IO_APIC
83 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
84 #endif /*CONFIG_X86_IO_APIC*/
85 #endif /*CONFIG_ACPI*/
87 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
90 /*
91 * Intel MP BIOS table parsing routines:
92 */
94 /*
95 * Checksum an MP configuration block.
96 */
98 static int __init mpf_checksum(unsigned char *mp, int len)
99 {
100 int sum = 0;
102 while (len--)
103 sum += *mp++;
105 return sum & 0xFF;
106 }
108 #ifndef CONFIG_XEN
109 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
110 {
111 int cpu;
112 unsigned char ver;
113 cpumask_t tmp_map;
115 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
116 disabled_cpus++;
117 return;
118 }
120 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
121 m->mpc_apicid,
122 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
123 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
124 m->mpc_apicver);
126 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
127 Dprintk(" Bootup CPU\n");
128 boot_cpu_id = m->mpc_apicid;
129 }
130 if (num_processors >= NR_CPUS) {
131 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
132 " Processor ignored.\n", NR_CPUS);
133 return;
134 }
136 num_processors++;
137 cpus_complement(tmp_map, cpu_present_map);
138 cpu = first_cpu(tmp_map);
140 #if MAX_APICS < 255
141 if ((int)m->mpc_apicid > MAX_APICS) {
142 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
143 m->mpc_apicid, MAX_APICS);
144 return;
145 }
146 #endif
147 ver = m->mpc_apicver;
149 physid_set(m->mpc_apicid, phys_cpu_present_map);
150 /*
151 * Validate version
152 */
153 if (ver == 0x0) {
154 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
155 ver = 0x10;
156 }
157 apic_version[m->mpc_apicid] = ver;
158 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
159 /*
160 * bios_cpu_apicid is required to have processors listed
161 * in same order as logical cpu numbers. Hence the first
162 * entry is BSP, and so on.
163 */
164 cpu = 0;
165 }
166 bios_cpu_apicid[cpu] = m->mpc_apicid;
167 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
169 cpu_set(cpu, cpu_possible_map);
170 cpu_set(cpu, cpu_present_map);
171 }
172 #else
173 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
174 {
175 num_processors++;
176 }
177 #endif /* CONFIG_XEN */
179 static void __init MP_bus_info (struct mpc_config_bus *m)
180 {
181 char str[7];
183 memcpy(str, m->mpc_bustype, 6);
184 str[6] = 0;
185 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
187 if (strncmp(str, "ISA", 3) == 0) {
188 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
189 } else if (strncmp(str, "EISA", 4) == 0) {
190 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
191 } else if (strncmp(str, "PCI", 3) == 0) {
192 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
193 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
194 mp_current_pci_id++;
195 } else if (strncmp(str, "MCA", 3) == 0) {
196 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
197 } else {
198 printk(KERN_ERR "Unknown bustype %s\n", str);
199 }
200 }
202 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
203 {
204 if (!(m->mpc_flags & MPC_APIC_USABLE))
205 return;
207 printk("I/O APIC #%d Version %d at 0x%X.\n",
208 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
209 if (nr_ioapics >= MAX_IO_APICS) {
210 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
211 MAX_IO_APICS, nr_ioapics);
212 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
213 }
214 if (!m->mpc_apicaddr) {
215 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
216 " found in MP table, skipping!\n");
217 return;
218 }
219 mp_ioapics[nr_ioapics] = *m;
220 nr_ioapics++;
221 }
223 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
224 {
225 mp_irqs [mp_irq_entries] = *m;
226 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
227 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
228 m->mpc_irqtype, m->mpc_irqflag & 3,
229 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
230 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
231 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
232 panic("Max # of irq sources exceeded!!\n");
233 }
235 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
236 {
237 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
238 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
239 m->mpc_irqtype, m->mpc_irqflag & 3,
240 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
241 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
242 /*
243 * Well it seems all SMP boards in existence
244 * use ExtINT/LVT1 == LINT0 and
245 * NMI/LVT2 == LINT1 - the following check
246 * will show us if this assumptions is false.
247 * Until then we do not have to add baggage.
248 */
249 if ((m->mpc_irqtype == mp_ExtINT) &&
250 (m->mpc_destapiclint != 0))
251 BUG();
252 if ((m->mpc_irqtype == mp_NMI) &&
253 (m->mpc_destapiclint != 1))
254 BUG();
255 }
257 /*
258 * Read/parse the MPC
259 */
261 static int __init smp_read_mpc(struct mp_config_table *mpc)
262 {
263 char str[16];
264 int count=sizeof(*mpc);
265 unsigned char *mpt=((unsigned char *)mpc)+count;
267 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
268 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
269 mpc->mpc_signature[0],
270 mpc->mpc_signature[1],
271 mpc->mpc_signature[2],
272 mpc->mpc_signature[3]);
273 return 0;
274 }
275 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
276 printk("SMP mptable: checksum error!\n");
277 return 0;
278 }
279 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
280 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
281 mpc->mpc_spec);
282 return 0;
283 }
284 if (!mpc->mpc_lapic) {
285 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
286 return 0;
287 }
288 memcpy(str,mpc->mpc_oem,8);
289 str[8]=0;
290 printk(KERN_INFO "OEM ID: %s ",str);
292 memcpy(str,mpc->mpc_productid,12);
293 str[12]=0;
294 printk("Product ID: %s ",str);
296 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
298 /* save the local APIC address, it might be non-default */
299 if (!acpi_lapic)
300 mp_lapic_addr = mpc->mpc_lapic;
302 /*
303 * Now process the configuration blocks.
304 */
305 while (count < mpc->mpc_length) {
306 switch(*mpt) {
307 case MP_PROCESSOR:
308 {
309 struct mpc_config_processor *m=
310 (struct mpc_config_processor *)mpt;
311 if (!acpi_lapic)
312 MP_processor_info(m);
313 mpt += sizeof(*m);
314 count += sizeof(*m);
315 break;
316 }
317 case MP_BUS:
318 {
319 struct mpc_config_bus *m=
320 (struct mpc_config_bus *)mpt;
321 MP_bus_info(m);
322 mpt += sizeof(*m);
323 count += sizeof(*m);
324 break;
325 }
326 case MP_IOAPIC:
327 {
328 struct mpc_config_ioapic *m=
329 (struct mpc_config_ioapic *)mpt;
330 MP_ioapic_info(m);
331 mpt+=sizeof(*m);
332 count+=sizeof(*m);
333 break;
334 }
335 case MP_INTSRC:
336 {
337 struct mpc_config_intsrc *m=
338 (struct mpc_config_intsrc *)mpt;
340 MP_intsrc_info(m);
341 mpt+=sizeof(*m);
342 count+=sizeof(*m);
343 break;
344 }
345 case MP_LINTSRC:
346 {
347 struct mpc_config_lintsrc *m=
348 (struct mpc_config_lintsrc *)mpt;
349 MP_lintsrc_info(m);
350 mpt+=sizeof(*m);
351 count+=sizeof(*m);
352 break;
353 }
354 }
355 }
356 clustered_apic_check();
357 if (!num_processors)
358 printk(KERN_ERR "SMP mptable: no processors registered!\n");
359 return num_processors;
360 }
362 static int __init ELCR_trigger(unsigned int irq)
363 {
364 unsigned int port;
366 port = 0x4d0 + (irq >> 3);
367 return (inb(port) >> (irq & 7)) & 1;
368 }
370 static void __init construct_default_ioirq_mptable(int mpc_default_type)
371 {
372 struct mpc_config_intsrc intsrc;
373 int i;
374 int ELCR_fallback = 0;
376 intsrc.mpc_type = MP_INTSRC;
377 intsrc.mpc_irqflag = 0; /* conforming */
378 intsrc.mpc_srcbus = 0;
379 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
381 intsrc.mpc_irqtype = mp_INT;
383 /*
384 * If true, we have an ISA/PCI system with no IRQ entries
385 * in the MP table. To prevent the PCI interrupts from being set up
386 * incorrectly, we try to use the ELCR. The sanity check to see if
387 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
388 * never be level sensitive, so we simply see if the ELCR agrees.
389 * If it does, we assume it's valid.
390 */
391 if (mpc_default_type == 5) {
392 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
394 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
395 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
396 else {
397 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
398 ELCR_fallback = 1;
399 }
400 }
402 for (i = 0; i < 16; i++) {
403 switch (mpc_default_type) {
404 case 2:
405 if (i == 0 || i == 13)
406 continue; /* IRQ0 & IRQ13 not connected */
407 /* fall through */
408 default:
409 if (i == 2)
410 continue; /* IRQ2 is never connected */
411 }
413 if (ELCR_fallback) {
414 /*
415 * If the ELCR indicates a level-sensitive interrupt, we
416 * copy that information over to the MP table in the
417 * irqflag field (level sensitive, active high polarity).
418 */
419 if (ELCR_trigger(i))
420 intsrc.mpc_irqflag = 13;
421 else
422 intsrc.mpc_irqflag = 0;
423 }
425 intsrc.mpc_srcbusirq = i;
426 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
427 MP_intsrc_info(&intsrc);
428 }
430 intsrc.mpc_irqtype = mp_ExtINT;
431 intsrc.mpc_srcbusirq = 0;
432 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
433 MP_intsrc_info(&intsrc);
434 }
436 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
437 {
438 struct mpc_config_processor processor;
439 struct mpc_config_bus bus;
440 struct mpc_config_ioapic ioapic;
441 struct mpc_config_lintsrc lintsrc;
442 int linttypes[2] = { mp_ExtINT, mp_NMI };
443 int i;
445 /*
446 * local APIC has default address
447 */
448 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
450 /*
451 * 2 CPUs, numbered 0 & 1.
452 */
453 processor.mpc_type = MP_PROCESSOR;
454 /* Either an integrated APIC or a discrete 82489DX. */
455 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
456 processor.mpc_cpuflag = CPU_ENABLED;
457 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
458 (boot_cpu_data.x86_model << 4) |
459 boot_cpu_data.x86_mask;
460 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
461 processor.mpc_reserved[0] = 0;
462 processor.mpc_reserved[1] = 0;
463 for (i = 0; i < 2; i++) {
464 processor.mpc_apicid = i;
465 MP_processor_info(&processor);
466 }
468 bus.mpc_type = MP_BUS;
469 bus.mpc_busid = 0;
470 switch (mpc_default_type) {
471 default:
472 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
473 mpc_default_type);
474 /* fall through */
475 case 1:
476 case 5:
477 memcpy(bus.mpc_bustype, "ISA ", 6);
478 break;
479 case 2:
480 case 6:
481 case 3:
482 memcpy(bus.mpc_bustype, "EISA ", 6);
483 break;
484 case 4:
485 case 7:
486 memcpy(bus.mpc_bustype, "MCA ", 6);
487 }
488 MP_bus_info(&bus);
489 if (mpc_default_type > 4) {
490 bus.mpc_busid = 1;
491 memcpy(bus.mpc_bustype, "PCI ", 6);
492 MP_bus_info(&bus);
493 }
495 ioapic.mpc_type = MP_IOAPIC;
496 ioapic.mpc_apicid = 2;
497 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
498 ioapic.mpc_flags = MPC_APIC_USABLE;
499 ioapic.mpc_apicaddr = 0xFEC00000;
500 MP_ioapic_info(&ioapic);
502 /*
503 * We set up most of the low 16 IO-APIC pins according to MPS rules.
504 */
505 construct_default_ioirq_mptable(mpc_default_type);
507 lintsrc.mpc_type = MP_LINTSRC;
508 lintsrc.mpc_irqflag = 0; /* conforming */
509 lintsrc.mpc_srcbusid = 0;
510 lintsrc.mpc_srcbusirq = 0;
511 lintsrc.mpc_destapic = MP_APIC_ALL;
512 for (i = 0; i < 2; i++) {
513 lintsrc.mpc_irqtype = linttypes[i];
514 lintsrc.mpc_destapiclint = i;
515 MP_lintsrc_info(&lintsrc);
516 }
517 }
519 static struct intel_mp_floating *mpf_found;
521 /*
522 * Scan the memory blocks for an SMP configuration block.
523 */
524 void __init get_smp_config (void)
525 {
526 struct intel_mp_floating *mpf = mpf_found;
528 /*
529 * ACPI supports both logical (e.g. Hyper-Threading) and physical
530 * processors, where MPS only supports physical.
531 */
532 if (acpi_lapic && acpi_ioapic) {
533 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
534 return;
535 }
536 else if (acpi_lapic)
537 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
539 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
540 if (mpf->mpf_feature2 & (1<<7)) {
541 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
542 pic_mode = 1;
543 } else {
544 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
545 pic_mode = 0;
546 }
548 /*
549 * Now see if we need to read further.
550 */
551 if (mpf->mpf_feature1 != 0) {
553 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
554 construct_default_ISA_mptable(mpf->mpf_feature1);
556 } else if (mpf->mpf_physptr) {
558 /*
559 * Read the physical hardware table. Anything here will
560 * override the defaults.
561 */
562 if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
563 smp_found_config = 0;
564 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
565 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
566 return;
567 }
568 /*
569 * If there are no explicit MP IRQ entries, then we are
570 * broken. We set up most of the low 16 IO-APIC pins to
571 * ISA defaults and hope it will work.
572 */
573 if (!mp_irq_entries) {
574 struct mpc_config_bus bus;
576 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
578 bus.mpc_type = MP_BUS;
579 bus.mpc_busid = 0;
580 memcpy(bus.mpc_bustype, "ISA ", 6);
581 MP_bus_info(&bus);
583 construct_default_ioirq_mptable(0);
584 }
586 } else
587 BUG();
589 printk(KERN_INFO "Processors: %d\n", num_processors);
590 /*
591 * Only use the first configuration found.
592 */
593 }
595 static int __init smp_scan_config (unsigned long base, unsigned long length)
596 {
597 extern void __bad_mpf_size(void);
598 unsigned int *bp = isa_bus_to_virt(base);
599 struct intel_mp_floating *mpf;
601 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
602 if (sizeof(*mpf) != 16)
603 __bad_mpf_size();
605 while (length > 0) {
606 mpf = (struct intel_mp_floating *)bp;
607 if ((*bp == SMP_MAGIC_IDENT) &&
608 (mpf->mpf_length == 1) &&
609 !mpf_checksum((unsigned char *)bp, 16) &&
610 ((mpf->mpf_specification == 1)
611 || (mpf->mpf_specification == 4)) ) {
613 smp_found_config = 1;
614 mpf_found = mpf;
615 return 1;
616 }
617 bp += 4;
618 length -= 16;
619 }
620 return 0;
621 }
623 void __init find_intel_smp (void)
624 {
625 unsigned int address;
627 /*
628 * FIXME: Linux assumes you have 640K of base ram..
629 * this continues the error...
630 *
631 * 1) Scan the bottom 1K for a signature
632 * 2) Scan the top 1K of base RAM
633 * 3) Scan the 64K of bios
634 */
635 if (smp_scan_config(0x0,0x400) ||
636 smp_scan_config(639*0x400,0x400) ||
637 smp_scan_config(0xF0000,0x10000))
638 return;
639 /*
640 * If it is an SMP machine we should know now, unless the
641 * configuration is in an EISA/MCA bus machine with an
642 * extended bios data area.
643 *
644 * there is a real-mode segmented pointer pointing to the
645 * 4K EBDA area at 0x40E, calculate and scan it here.
646 *
647 * NOTE! There are Linux loaders that will corrupt the EBDA
648 * area, and as such this kind of SMP config may be less
649 * trustworthy, simply because the SMP table may have been
650 * stomped on during early boot. These loaders are buggy and
651 * should be fixed.
652 */
654 address = *(unsigned short *)phys_to_virt(0x40E);
655 address <<= 4;
656 if (smp_scan_config(address, 0x1000))
657 return;
659 /* If we have come this far, we did not find an MP table */
660 printk(KERN_INFO "No mptable found.\n");
661 }
663 /*
664 * - Intel MP Configuration Table
665 */
666 void __init find_smp_config (void)
667 {
668 #ifdef CONFIG_X86_LOCAL_APIC
669 find_intel_smp();
670 #endif
671 }
674 /* --------------------------------------------------------------------------
675 ACPI-based MP Configuration
676 -------------------------------------------------------------------------- */
678 #ifdef CONFIG_ACPI
680 void __init mp_register_lapic_address (
681 u64 address)
682 {
683 #ifndef CONFIG_XEN
684 mp_lapic_addr = (unsigned long) address;
686 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
688 if (boot_cpu_id == -1U)
689 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
691 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
692 #endif
693 }
696 void __cpuinit mp_register_lapic (
697 u8 id,
698 u8 enabled)
699 {
700 struct mpc_config_processor processor;
701 int boot_cpu = 0;
703 if (id >= MAX_APICS) {
704 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
705 id, MAX_APICS);
706 return;
707 }
709 if (id == boot_cpu_physical_apicid)
710 boot_cpu = 1;
712 #ifndef CONFIG_XEN
713 processor.mpc_type = MP_PROCESSOR;
714 processor.mpc_apicid = id;
715 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
716 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
717 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
718 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
719 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
720 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
721 processor.mpc_reserved[0] = 0;
722 processor.mpc_reserved[1] = 0;
723 #endif
725 MP_processor_info(&processor);
726 }
728 #ifdef CONFIG_X86_IO_APIC
730 #define MP_ISA_BUS 0
731 #define MP_MAX_IOAPIC_PIN 127
733 static struct mp_ioapic_routing {
734 int apic_id;
735 int gsi_start;
736 int gsi_end;
737 u32 pin_programmed[4];
738 } mp_ioapic_routing[MAX_IO_APICS];
741 static int mp_find_ioapic (
742 int gsi)
743 {
744 int i = 0;
746 /* Find the IOAPIC that manages this GSI. */
747 for (i = 0; i < nr_ioapics; i++) {
748 if ((gsi >= mp_ioapic_routing[i].gsi_start)
749 && (gsi <= mp_ioapic_routing[i].gsi_end))
750 return i;
751 }
753 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
755 return -1;
756 }
759 void __init mp_register_ioapic (
760 u8 id,
761 u32 address,
762 u32 gsi_base)
763 {
764 int idx = 0;
766 if (nr_ioapics >= MAX_IO_APICS) {
767 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
768 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
769 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
770 }
771 if (!address) {
772 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
773 " found in MADT table, skipping!\n");
774 return;
775 }
777 idx = nr_ioapics++;
779 mp_ioapics[idx].mpc_type = MP_IOAPIC;
780 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
781 mp_ioapics[idx].mpc_apicaddr = address;
783 #ifndef CONFIG_XEN
784 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
785 #endif
786 mp_ioapics[idx].mpc_apicid = id;
787 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
789 /*
790 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
791 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
792 */
793 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
794 mp_ioapic_routing[idx].gsi_start = gsi_base;
795 mp_ioapic_routing[idx].gsi_end = gsi_base +
796 io_apic_get_redir_entries(idx);
798 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
799 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
800 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
801 mp_ioapic_routing[idx].gsi_start,
802 mp_ioapic_routing[idx].gsi_end);
804 return;
805 }
808 void __init mp_override_legacy_irq (
809 u8 bus_irq,
810 u8 polarity,
811 u8 trigger,
812 u32 gsi)
813 {
814 struct mpc_config_intsrc intsrc;
815 int ioapic = -1;
816 int pin = -1;
818 /*
819 * Convert 'gsi' to 'ioapic.pin'.
820 */
821 ioapic = mp_find_ioapic(gsi);
822 if (ioapic < 0)
823 return;
824 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
826 /*
827 * TBD: This check is for faulty timer entries, where the override
828 * erroneously sets the trigger to level, resulting in a HUGE
829 * increase of timer interrupts!
830 */
831 if ((bus_irq == 0) && (trigger == 3))
832 trigger = 1;
834 intsrc.mpc_type = MP_INTSRC;
835 intsrc.mpc_irqtype = mp_INT;
836 intsrc.mpc_irqflag = (trigger << 2) | polarity;
837 intsrc.mpc_srcbus = MP_ISA_BUS;
838 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
839 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
840 intsrc.mpc_dstirq = pin; /* INTIN# */
842 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
843 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
844 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
845 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
847 mp_irqs[mp_irq_entries] = intsrc;
848 if (++mp_irq_entries == MAX_IRQ_SOURCES)
849 panic("Max # of irq sources exceeded!\n");
851 return;
852 }
855 void __init mp_config_acpi_legacy_irqs (void)
856 {
857 struct mpc_config_intsrc intsrc;
858 int i = 0;
859 int ioapic = -1;
861 /*
862 * Fabricate the legacy ISA bus (bus #31).
863 */
864 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
865 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
867 /*
868 * Locate the IOAPIC that manages the ISA IRQs (0-15).
869 */
870 ioapic = mp_find_ioapic(0);
871 if (ioapic < 0)
872 return;
874 intsrc.mpc_type = MP_INTSRC;
875 intsrc.mpc_irqflag = 0; /* Conforming */
876 intsrc.mpc_srcbus = MP_ISA_BUS;
877 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
879 /*
880 * Use the default configuration for the IRQs 0-15. Unless
881 * overridden by (MADT) interrupt source override entries.
882 */
883 for (i = 0; i < 16; i++) {
884 int idx;
886 for (idx = 0; idx < mp_irq_entries; idx++) {
887 struct mpc_config_intsrc *irq = mp_irqs + idx;
889 /* Do we already have a mapping for this ISA IRQ? */
890 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
891 break;
893 /* Do we already have a mapping for this IOAPIC pin */
894 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
895 (irq->mpc_dstirq == i))
896 break;
897 }
899 if (idx != mp_irq_entries) {
900 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
901 continue; /* IRQ already used */
902 }
904 intsrc.mpc_irqtype = mp_INT;
905 intsrc.mpc_srcbusirq = i; /* Identity mapped */
906 intsrc.mpc_dstirq = i;
908 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
909 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
910 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
911 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
912 intsrc.mpc_dstirq);
914 mp_irqs[mp_irq_entries] = intsrc;
915 if (++mp_irq_entries == MAX_IRQ_SOURCES)
916 panic("Max # of irq sources exceeded!\n");
917 }
919 return;
920 }
922 #define MAX_GSI_NUM 4096
924 int mp_register_gsi(u32 gsi, int triggering, int polarity)
925 {
926 int ioapic = -1;
927 int ioapic_pin = 0;
928 int idx, bit = 0;
929 static int pci_irq = 16;
930 /*
931 * Mapping between Global System Interrupts, which
932 * represent all possible interrupts, to the IRQs
933 * assigned to actual devices.
934 */
935 static int gsi_to_irq[MAX_GSI_NUM];
937 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
938 return gsi;
940 /* Don't set up the ACPI SCI because it's already set up */
941 if (acpi_fadt.sci_int == gsi)
942 return gsi;
944 ioapic = mp_find_ioapic(gsi);
945 if (ioapic < 0) {
946 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
947 return gsi;
948 }
950 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
952 /*
953 * Avoid pin reprogramming. PRTs typically include entries
954 * with redundant pin->gsi mappings (but unique PCI devices);
955 * we only program the IOAPIC on the first.
956 */
957 bit = ioapic_pin % 32;
958 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
959 if (idx > 3) {
960 printk(KERN_ERR "Invalid reference to IOAPIC pin "
961 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
962 ioapic_pin);
963 return gsi;
964 }
965 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
966 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
967 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
968 return gsi_to_irq[gsi];
969 }
971 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
973 if (triggering == ACPI_LEVEL_SENSITIVE) {
974 /*
975 * For PCI devices assign IRQs in order, avoiding gaps
976 * due to unused I/O APIC pins.
977 */
978 int irq = gsi;
979 if (gsi < MAX_GSI_NUM) {
980 /*
981 * Retain the VIA chipset work-around (gsi > 15), but
982 * avoid a problem where the 8254 timer (IRQ0) is setup
983 * via an override (so it's not on pin 0 of the ioapic),
984 * and at the same time, the pin 0 interrupt is a PCI
985 * type. The gsi > 15 test could cause these two pins
986 * to be shared as IRQ0, and they are not shareable.
987 * So test for this condition, and if necessary, avoid
988 * the pin collision.
989 */
990 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
991 gsi = pci_irq++;
992 /*
993 * Don't assign IRQ used by ACPI SCI
994 */
995 if (gsi == acpi_fadt.sci_int)
996 gsi = pci_irq++;
997 gsi_to_irq[irq] = gsi;
998 } else {
999 printk(KERN_ERR "GSI %u is too high\n", gsi);
1000 return gsi;
1004 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1005 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1006 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1007 return gsi;
1010 #endif /*CONFIG_X86_IO_APIC*/
1011 #endif /*CONFIG_ACPI*/