ia64/xen-unstable

view xen/arch/x86/hvm/rtc.c @ 16603:4553bc1087d9

hvm: Reduce vpt.c dependencies on external timer details.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Dec 12 15:41:20 2007 +0000 (2007-12-12)
parents 86e4b37a06cc
children 9862217f3c34
line source
1 /*
2 * QEMU MC146818 RTC emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
25 #include <asm/mc146818rtc.h>
26 #include <asm/hvm/vpt.h>
27 #include <asm/hvm/io.h>
28 #include <asm/hvm/support.h>
29 #include <asm/current.h>
31 #define domain_vrtc(d) (&(d)->arch.hvm_domain.pl_time.vrtc)
32 #define vcpu_vrtc(vcpu) (domain_vrtc((vcpu)->domain))
33 #define vrtc_domain(rtc) (container_of((rtc), struct domain, \
34 arch.hvm_domain.pl_time.vrtc))
35 #define vrtc_vcpu(rtc) (vrtc_domain(rtc)->vcpu[0])
37 static void rtc_periodic_cb(struct vcpu *v, void *opaque)
38 {
39 RTCState *s = opaque;
40 spin_lock(&s->lock);
41 s->hw.cmos_data[RTC_REG_C] |= 0xc0;
42 spin_unlock(&s->lock);
43 }
45 /* Enable/configure/disable the periodic timer based on the RTC_PIE and
46 * RTC_RATE_SELECT settings */
47 static void rtc_timer_update(RTCState *s)
48 {
49 int period_code, period;
50 struct vcpu *v = vrtc_vcpu(s);
52 ASSERT(spin_is_locked(&s->lock));
54 period_code = s->hw.cmos_data[RTC_REG_A] & RTC_RATE_SELECT;
55 if ( (period_code != 0) && (s->hw.cmos_data[RTC_REG_B] & RTC_PIE) )
56 {
57 if ( period_code <= 2 )
58 period_code += 7;
60 period = 1 << (period_code - 1); /* period in 32 Khz cycles */
61 period = DIV_ROUND((period * 1000000000ULL), 32768); /* period in ns */
62 create_periodic_time(v, &s->pt, period, RTC_IRQ,
63 0, rtc_periodic_cb, s);
64 }
65 else
66 {
67 destroy_periodic_time(&s->pt);
68 }
69 }
71 static void rtc_set_time(RTCState *s);
73 static int rtc_ioport_write(void *opaque, uint32_t addr, uint32_t data)
74 {
75 RTCState *s = opaque;
77 spin_lock(&s->lock);
79 if ( (addr & 1) == 0 )
80 {
81 data &= 0x7f;
82 s->hw.cmos_index = data;
83 spin_unlock(&s->lock);
84 return (data < RTC_CMOS_SIZE);
85 }
87 if ( s->hw.cmos_index >= RTC_CMOS_SIZE )
88 {
89 spin_unlock(&s->lock);
90 return 0;
91 }
93 switch ( s->hw.cmos_index )
94 {
95 case RTC_SECONDS_ALARM:
96 case RTC_MINUTES_ALARM:
97 case RTC_HOURS_ALARM:
98 s->hw.cmos_data[s->hw.cmos_index] = data;
99 break;
100 case RTC_SECONDS:
101 case RTC_MINUTES:
102 case RTC_HOURS:
103 case RTC_DAY_OF_WEEK:
104 case RTC_DAY_OF_MONTH:
105 case RTC_MONTH:
106 case RTC_YEAR:
107 s->hw.cmos_data[s->hw.cmos_index] = data;
108 /* if in set mode, do not update the time */
109 if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
110 rtc_set_time(s);
111 break;
112 case RTC_REG_A:
113 /* UIP bit is read only */
114 s->hw.cmos_data[RTC_REG_A] = (data & ~RTC_UIP) |
115 (s->hw.cmos_data[RTC_REG_A] & RTC_UIP);
116 rtc_timer_update(s);
117 break;
118 case RTC_REG_B:
119 if ( data & RTC_SET )
120 {
121 /* set mode: reset UIP mode */
122 s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
123 }
124 else
125 {
126 /* if disabling set mode, update the time */
127 if ( s->hw.cmos_data[RTC_REG_B] & RTC_SET )
128 rtc_set_time(s);
129 }
130 s->hw.cmos_data[RTC_REG_B] = data;
131 rtc_timer_update(s);
132 break;
133 case RTC_REG_C:
134 case RTC_REG_D:
135 /* cannot write to them */
136 break;
137 }
139 spin_unlock(&s->lock);
141 return 1;
142 }
144 static inline int to_bcd(RTCState *s, int a)
145 {
146 if ( s->hw.cmos_data[RTC_REG_B] & 0x04 )
147 return a;
148 else
149 return ((a / 10) << 4) | (a % 10);
150 }
152 static inline int from_bcd(RTCState *s, int a)
153 {
154 if ( s->hw.cmos_data[RTC_REG_B] & 0x04 )
155 return a;
156 else
157 return ((a >> 4) * 10) + (a & 0x0f);
158 }
160 static void rtc_set_time(RTCState *s)
161 {
162 struct tm *tm = &s->current_tm;
163 unsigned long before, after; /* XXX s_time_t */
165 ASSERT(spin_is_locked(&s->lock));
167 before = mktime(tm->tm_year, tm->tm_mon, tm->tm_mday,
168 tm->tm_hour, tm->tm_min, tm->tm_sec);
170 tm->tm_sec = from_bcd(s, s->hw.cmos_data[RTC_SECONDS]);
171 tm->tm_min = from_bcd(s, s->hw.cmos_data[RTC_MINUTES]);
172 tm->tm_hour = from_bcd(s, s->hw.cmos_data[RTC_HOURS] & 0x7f);
173 if ( !(s->hw.cmos_data[RTC_REG_B] & 0x02) &&
174 (s->hw.cmos_data[RTC_HOURS] & 0x80) )
175 tm->tm_hour += 12;
176 tm->tm_wday = from_bcd(s, s->hw.cmos_data[RTC_DAY_OF_WEEK]);
177 tm->tm_mday = from_bcd(s, s->hw.cmos_data[RTC_DAY_OF_MONTH]);
178 tm->tm_mon = from_bcd(s, s->hw.cmos_data[RTC_MONTH]) - 1;
179 tm->tm_year = from_bcd(s, s->hw.cmos_data[RTC_YEAR]) + 100;
181 after = mktime(tm->tm_year, tm->tm_mon, tm->tm_mday,
182 tm->tm_hour, tm->tm_min, tm->tm_sec);
183 send_timeoffset_req(after - before);
184 }
186 static void rtc_copy_date(RTCState *s)
187 {
188 const struct tm *tm = &s->current_tm;
189 struct domain *d = vrtc_domain(s);
191 ASSERT(spin_is_locked(&s->lock));
193 if ( s->time_offset_seconds != d->time_offset_seconds )
194 {
195 s->current_tm = gmtime(get_localtime(d));
196 s->time_offset_seconds = d->time_offset_seconds;
197 }
199 s->hw.cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
200 s->hw.cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
201 if ( s->hw.cmos_data[RTC_REG_B] & RTC_24H )
202 {
203 /* 24 hour format */
204 s->hw.cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
205 }
206 else
207 {
208 /* 12 hour format */
209 s->hw.cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
210 if ( tm->tm_hour >= 12 )
211 s->hw.cmos_data[RTC_HOURS] |= 0x80;
212 }
213 s->hw.cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
214 s->hw.cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
215 s->hw.cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
216 s->hw.cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
217 }
219 /* month is between 0 and 11. */
220 static int get_days_in_month(int month, int year)
221 {
222 static const int days_tab[12] = {
223 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
224 };
225 int d;
226 if ( (unsigned)month >= 12 )
227 return 31;
228 d = days_tab[month];
229 if ( month == 1 )
230 if ( (year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0) )
231 d++;
232 return d;
233 }
235 /* update 'tm' to the next second */
236 static void rtc_next_second(RTCState *s)
237 {
238 struct tm *tm = &s->current_tm;
239 int days_in_month;
240 struct domain *d = vrtc_domain(s);
242 ASSERT(spin_is_locked(&s->lock));
244 if ( s->time_offset_seconds != d->time_offset_seconds )
245 {
246 s->current_tm = gmtime(get_localtime(d));
247 s->time_offset_seconds = d->time_offset_seconds;
248 }
250 tm->tm_sec++;
251 if ( (unsigned)tm->tm_sec >= 60 )
252 {
253 tm->tm_sec = 0;
254 tm->tm_min++;
255 if ( (unsigned)tm->tm_min >= 60 )
256 {
257 tm->tm_min = 0;
258 tm->tm_hour++;
259 if ( (unsigned)tm->tm_hour >= 24 )
260 {
261 tm->tm_hour = 0;
262 /* next day */
263 tm->tm_wday++;
264 if ( (unsigned)tm->tm_wday >= 7 )
265 tm->tm_wday = 0;
266 days_in_month = get_days_in_month(tm->tm_mon,
267 tm->tm_year + 1900);
268 tm->tm_mday++;
269 if ( tm->tm_mday < 1 )
270 {
271 tm->tm_mday = 1;
272 }
273 else if ( tm->tm_mday > days_in_month )
274 {
275 tm->tm_mday = 1;
276 tm->tm_mon++;
277 if ( tm->tm_mon >= 12 )
278 {
279 tm->tm_mon = 0;
280 tm->tm_year++;
281 }
282 }
283 }
284 }
285 }
286 }
288 static void rtc_update_second(void *opaque)
289 {
290 RTCState *s = opaque;
292 spin_lock(&s->lock);
294 /* if the oscillator is not in normal operation, we do not update */
295 if ( (s->hw.cmos_data[RTC_REG_A] & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ )
296 {
297 s->next_second_time += 1000000000ULL;
298 set_timer(&s->second_timer, s->next_second_time);
299 }
300 else
301 {
302 rtc_next_second(s);
304 if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
305 s->hw.cmos_data[RTC_REG_A] |= RTC_UIP;
307 /* Delay time before update cycle */
308 set_timer(&s->second_timer2, s->next_second_time + 244000);
309 }
311 spin_unlock(&s->lock);
312 }
314 static void rtc_update_second2(void *opaque)
315 {
316 RTCState *s = opaque;
317 struct domain *d = vrtc_domain(s);
319 spin_lock(&s->lock);
321 if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
322 rtc_copy_date(s);
324 /* check alarm */
325 if ( s->hw.cmos_data[RTC_REG_B] & RTC_AIE )
326 {
327 if ( ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
328 from_bcd(s, s->hw.cmos_data[RTC_SECONDS_ALARM]) ==
329 s->current_tm.tm_sec) &&
330 ((s->hw.cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
331 from_bcd(s, s->hw.cmos_data[RTC_MINUTES_ALARM]) ==
332 s->current_tm.tm_min) &&
333 ((s->hw.cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
334 from_bcd(s, s->hw.cmos_data[RTC_HOURS_ALARM]) ==
335 s->current_tm.tm_hour) )
336 {
337 s->hw.cmos_data[RTC_REG_C] |= 0xa0;
338 hvm_isa_irq_deassert(d, RTC_IRQ);
339 hvm_isa_irq_assert(d, RTC_IRQ);
340 }
341 }
343 /* update ended interrupt */
344 if ( (s->hw.cmos_data[RTC_REG_B] & (RTC_UIE|RTC_SET)) == RTC_UIE )
345 {
346 s->hw.cmos_data[RTC_REG_C] |= 0x90;
347 hvm_isa_irq_deassert(d, RTC_IRQ);
348 hvm_isa_irq_assert(d, RTC_IRQ);
349 }
351 /* clear update in progress bit */
352 s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
354 s->next_second_time += 1000000000ULL;
355 set_timer(&s->second_timer, s->next_second_time);
357 spin_unlock(&s->lock);
358 }
360 static uint32_t rtc_ioport_read(RTCState *s, uint32_t addr)
361 {
362 int ret;
364 if ( (addr & 1) == 0 )
365 return 0xff;
367 spin_lock(&s->lock);
369 switch ( s->hw.cmos_index )
370 {
371 case RTC_SECONDS:
372 case RTC_MINUTES:
373 case RTC_HOURS:
374 case RTC_DAY_OF_WEEK:
375 case RTC_DAY_OF_MONTH:
376 case RTC_MONTH:
377 case RTC_YEAR:
378 ret = s->hw.cmos_data[s->hw.cmos_index];
379 break;
380 case RTC_REG_A:
381 ret = s->hw.cmos_data[s->hw.cmos_index];
382 break;
383 case RTC_REG_C:
384 ret = s->hw.cmos_data[s->hw.cmos_index];
385 hvm_isa_irq_deassert(vrtc_domain(s), RTC_IRQ);
386 s->hw.cmos_data[RTC_REG_C] = 0x00;
387 break;
388 default:
389 ret = s->hw.cmos_data[s->hw.cmos_index];
390 break;
391 }
393 spin_unlock(&s->lock);
395 return ret;
396 }
398 static int handle_rtc_io(ioreq_t *p)
399 {
400 struct RTCState *vrtc = vcpu_vrtc(current);
402 if ( (p->size != 1) || p->data_is_ptr || (p->type != IOREQ_TYPE_PIO) )
403 {
404 gdprintk(XENLOG_WARNING, "HVM_RTC bas access\n");
405 return 1;
406 }
408 if ( p->dir == IOREQ_WRITE )
409 {
410 if ( rtc_ioport_write(vrtc, p->addr, p->data & 0xFF) )
411 return 1;
412 }
413 else if ( vrtc->hw.cmos_index < RTC_CMOS_SIZE )
414 {
415 p->data = rtc_ioport_read(vrtc, p->addr);
416 return 1;
417 }
419 return 0;
420 }
422 void rtc_migrate_timers(struct vcpu *v)
423 {
424 RTCState *s = vcpu_vrtc(v);
426 if ( v->vcpu_id == 0 )
427 {
428 migrate_timer(&s->second_timer, v->processor);
429 migrate_timer(&s->second_timer2, v->processor);
430 }
431 }
433 /* Save RTC hardware state */
434 static int rtc_save(struct domain *d, hvm_domain_context_t *h)
435 {
436 RTCState *s = domain_vrtc(d);
437 int rc;
438 spin_lock(&s->lock);
439 rc = hvm_save_entry(RTC, 0, h, &s->hw);
440 spin_unlock(&s->lock);
441 return rc;
442 }
444 /* Reload the hardware state from a saved domain */
445 static int rtc_load(struct domain *d, hvm_domain_context_t *h)
446 {
447 RTCState *s = domain_vrtc(d);
449 spin_lock(&s->lock);
451 /* Restore the registers */
452 if ( hvm_load_entry(RTC, h, &s->hw) != 0 )
453 {
454 spin_unlock(&s->lock);
455 return -EINVAL;
456 }
458 /* Reset the wall-clock time. In normal running, this runs with host
459 * time, so let's keep doing that. */
460 s->current_tm = gmtime(get_localtime(d));
461 rtc_copy_date(s);
462 s->next_second_time = NOW() + 1000000000ULL;
463 stop_timer(&s->second_timer);
464 set_timer(&s->second_timer2, s->next_second_time);
466 /* Reset the periodic interrupt timer based on the registers */
467 rtc_timer_update(s);
469 spin_unlock(&s->lock);
471 return 0;
472 }
474 HVM_REGISTER_SAVE_RESTORE(RTC, rtc_save, rtc_load, 1, HVMSR_PER_DOM);
477 void rtc_init(struct vcpu *v, int base)
478 {
479 RTCState *s = vcpu_vrtc(v);
481 spin_lock_init(&s->lock);
483 s->pt.source = PTSRC_isa;
485 s->hw.cmos_data[RTC_REG_A] = RTC_REF_CLCK_32KHZ | 6; /* ~1kHz */
486 s->hw.cmos_data[RTC_REG_B] = RTC_24H;
487 s->hw.cmos_data[RTC_REG_C] = 0;
488 s->hw.cmos_data[RTC_REG_D] = RTC_VRT;
490 s->current_tm = gmtime(get_localtime(v->domain));
492 spin_lock(&s->lock);
493 rtc_copy_date(s);
494 spin_unlock(&s->lock);
496 init_timer(&s->second_timer, rtc_update_second, s, v->processor);
497 init_timer(&s->second_timer2, rtc_update_second2, s, v->processor);
499 s->next_second_time = NOW() + 1000000000ULL;
500 set_timer(&s->second_timer2, s->next_second_time);
502 register_portio_handler(v->domain, base, 2, handle_rtc_io);
503 }
505 void rtc_deinit(struct domain *d)
506 {
507 RTCState *s = domain_vrtc(d);
509 destroy_periodic_time(&s->pt);
510 kill_timer(&s->second_timer);
511 kill_timer(&s->second_timer2);
512 }