ia64/xen-unstable

view linux-2.4.29-xen-sparse/include/asm-xen/smp.h @ 3887:4385894c52ae

bitkeeper revision 1.1230.2.4 (421a95cepOZORm0EbZfqBeZ6PZ8MwA)

Merge freefall.cl.cam.ac.uk:/auto/groups/xeno/users/cl349/BK/xen-unstable.bk
into freefall.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xen-unstable.bk
author iap10@freefall.cl.cam.ac.uk
date Tue Feb 22 02:15:42 2005 +0000 (2005-02-22)
parents 0a4b76b6b5a0
children
line source
1 #ifndef __ASM_SMP_H
2 #define __ASM_SMP_H
4 /*
5 * We need the APIC definitions automatically as part of 'smp.h'
6 */
7 #ifndef __ASSEMBLY__
8 #include <linux/config.h>
9 #include <linux/threads.h>
10 #include <linux/ptrace.h>
11 #endif
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #ifndef __ASSEMBLY__
15 #include <asm/bitops.h>
16 #include <asm/mpspec.h>
17 #ifdef CONFIG_X86_IO_APIC
18 #include <asm/io_apic.h>
19 #endif
20 #include <asm/apic.h>
21 #endif
22 #endif
24 #ifdef CONFIG_SMP
25 #ifndef __ASSEMBLY__
27 /*
28 * Private routines/data
29 */
31 extern void smp_alloc_memory(void);
32 extern unsigned long phys_cpu_present_map;
33 extern unsigned long cpu_online_map;
34 extern volatile unsigned long smp_invalidate_needed;
35 extern int pic_mode;
36 extern int smp_num_siblings;
37 extern int cpu_sibling_map[];
39 extern void smp_flush_tlb(void);
40 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
41 extern void fastcall smp_send_reschedule(int cpu);
42 extern void smp_invalidate_rcv(void); /* Process an NMI */
43 extern void (*mtrr_hook) (void);
44 extern void zap_low_mappings (void);
46 /*
47 * On x86 all CPUs are mapped 1:1 to the APIC space.
48 * This simplifies scheduling and IPI sending and
49 * compresses data structures.
50 */
51 static inline int cpu_logical_map(int cpu)
52 {
53 return cpu;
54 }
55 static inline int cpu_number_map(int cpu)
56 {
57 return cpu;
58 }
60 /*
61 * Some lowlevel functions might want to know about
62 * the real APIC ID <-> CPU # mapping.
63 */
64 #define MAX_APICID 256
65 extern volatile int cpu_to_physical_apicid[NR_CPUS];
66 extern volatile int physical_apicid_to_cpu[MAX_APICID];
67 extern volatile int cpu_to_logical_apicid[NR_CPUS];
68 extern volatile int logical_apicid_to_cpu[MAX_APICID];
70 /*
71 * General functions that each host system must provide.
72 */
74 extern void smp_boot_cpus(void);
75 extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */
77 /*
78 * This function is needed by all SMP systems. It must _always_ be valid
79 * from the initial startup. We map APIC_BASE very early in page_setup(),
80 * so this is correct in the x86 case.
81 */
83 #define smp_processor_id() (current->processor)
85 #endif /* !__ASSEMBLY__ */
87 #define NO_PROC_ID 0xFF /* No processor magic marker */
89 /*
90 * This magic constant controls our willingness to transfer
91 * a process across CPUs. Such a transfer incurs misses on the L1
92 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
93 * gut feeling is this will vary by board in value. For a board
94 * with separate L2 cache it probably depends also on the RSS, and
95 * for a board with shared L2 cache it ought to decay fast as other
96 * processes are run.
97 */
99 #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
101 #endif
102 #endif