ia64/xen-unstable

view xen/include/asm-x86/config.h @ 19697:42fe00c6f8b4

Enable pci mmcfg and ATS for x86_64

This patch enables PCI MMCONFIG in xen and turns on hooks for ATS.

Signed-off-by: Allen Kay <allen.m.kay@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Jun 02 11:49:34 2009 +0100 (2009-06-02)
parents 6705898f768d
children 2f9e1348aa98
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #else
13 # define CONFIG_PAGING_LEVELS 3
14 #endif
16 #define CONFIG_X86 1
17 #define CONFIG_X86_HT 1
18 #define CONFIG_PAGING_ASSISTANCE 1
19 #define CONFIG_SMP 1
20 #define CONFIG_X86_LOCAL_APIC 1
21 #define CONFIG_X86_GOOD_APIC 1
22 #define CONFIG_X86_IO_APIC 1
23 #define CONFIG_X86_PM_TIMER 1
24 #define CONFIG_HPET_TIMER 1
25 #define CONFIG_X86_MCE_THERMAL 1
26 #define CONFIG_NUMA 1
27 #define CONFIG_DISCONTIGMEM 1
28 #define CONFIG_NUMA_EMU 1
30 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
31 #define CONFIG_X86_L1_CACHE_SHIFT 7
33 #define CONFIG_ACPI 1
34 #define CONFIG_ACPI_BOOT 1
35 #define CONFIG_ACPI_SLEEP 1
36 #define CONFIG_ACPI_NUMA 1
37 #define CONFIG_ACPI_SRAT 1
38 #define CONFIG_ACPI_CSTATE 1
40 #define CONFIG_VGA 1
42 #define CONFIG_HOTPLUG 1
43 #define CONFIG_HOTPLUG_CPU 1
45 #define HZ 100
47 #define OPT_CONSOLE_STR "vga"
49 #ifdef MAX_PHYS_CPUS
50 #define NR_CPUS MAX_PHYS_CPUS
51 #else
52 #define NR_CPUS 32
53 #endif
55 #if defined(__i386__) && (NR_CPUS > 32)
56 #error "Maximum of 32 physical processors supported by Xen on x86_32"
57 #endif
59 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
60 # define supervisor_mode_kernel (1)
61 #else
62 # define supervisor_mode_kernel (0)
63 #endif
65 /* Linkage for x86 */
66 #define __ALIGN .align 16,0x90
67 #define __ALIGN_STR ".align 16,0x90"
68 #ifdef __ASSEMBLY__
69 #define ALIGN __ALIGN
70 #define ALIGN_STR __ALIGN_STR
71 #define ENTRY(name) \
72 .globl name; \
73 ALIGN; \
74 name:
75 #endif
77 #define NR_hypercalls 64
79 #ifndef NDEBUG
80 #define MEMORY_GUARD
81 #endif
83 #ifdef __i386__
84 #define STACK_ORDER 2
85 #else
86 #define STACK_ORDER 3
87 #endif
88 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
90 /* Primary stack is restricted to 8kB by guard pages. */
91 #define PRIMARY_STACK_SIZE 8192
93 #define BOOT_TRAMPOLINE 0x8c000
94 #define bootsym_phys(sym) \
95 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
96 #define bootsym(sym) \
97 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
98 BOOT_TRAMPOLINE-__pa(trampoline_start)))
99 #ifndef __ASSEMBLY__
100 extern char trampoline_start[], trampoline_end[];
101 extern char trampoline_realmode_entry[];
102 extern unsigned int trampoline_xen_phys_start;
103 extern unsigned char trampoline_cpu_started;
104 extern char wakeup_start[];
105 extern unsigned int video_mode, video_flags;
106 #endif
108 #if defined(__x86_64__)
110 #define CONFIG_X86_64 1
111 #define CONFIG_COMPAT 1
113 #define asmlinkage
115 #define PML4_ENTRY_BITS 39
116 #ifndef __ASSEMBLY__
117 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
118 #define PML4_ADDR(_slot) \
119 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
120 (_slot ## UL << PML4_ENTRY_BITS))
121 #else
122 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
123 #define PML4_ADDR(_slot) \
124 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
125 #endif
127 /*
128 * Memory layout:
129 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
130 * Guest-defined use (see below for compatibility mode guests).
131 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
132 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
133 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
134 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
135 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
136 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
137 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
138 * ioremap for PCI mmconfig space
139 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
140 * Guest linear page table.
141 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
142 * Shadow linear page table.
143 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
144 * Per-domain mappings (e.g., GDT, LDT).
145 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
146 * Machine-to-phys translation table.
147 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
148 * Page-frame information array.
149 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
150 * ioremap()/fixmap area.
151 * 0xffff828c00000000 - 0xffff828c3fffffff [1GB, 2^30 bytes, PML4:261]
152 * Compatibility machine-to-phys translation table.
153 * 0xffff828c40000000 - 0xffff828c7fffffff [1GB, 2^30 bytes, PML4:261]
154 * High read-only compatibility machine-to-phys translation table.
155 * 0xffff828c80000000 - 0xffff828cbfffffff [1GB, 2^30 bytes, PML4:261]
156 * Xen text, static data, bss.
157 * 0xffff828cc0000000 - 0xffff82ffffffffff [461GB, PML4:261]
158 * Reserved for future use.
159 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
160 * 1:1 direct mapping of all physical memory.
161 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
162 * Reserved for future use.
163 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
164 * Guest-defined use.
165 *
166 * Compatibility guest area layout:
167 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
168 * Guest-defined use.
169 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
170 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
171 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
172 * Unused.
173 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
174 * Hypercall argument translation area.
175 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
176 * Reserved for future use.
177 */
180 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
181 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
182 #define ROOT_PAGETABLE_XEN_SLOTS \
183 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
185 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
186 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
187 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
188 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
189 #define RO_MPT_VIRT_START (PML4_ADDR(256))
190 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
191 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB)
192 * - full 16-bit segment support needs 44 bits
193 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits)
194 */
195 #define PCI_MCFG_VIRT_START (PML4_ADDR(257))
196 #define PCI_MCFG_VIRT_END (RDWR_MPT_VIRT_START + PML4_ENTRY_BYTES)
197 /* Slot 258: linear page table (guest table). */
198 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
199 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
200 /* Slot 259: linear page table (shadow table). */
201 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
202 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
203 /* Slot 260: per-domain mappings. */
204 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
205 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
206 #define PERDOMAIN_MBYTES ((unsigned long)GDT_LDT_MBYTES)
207 /* Slot 261: machine-to-phys conversion table (16GB). */
208 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
209 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
210 /* Slot 261: page-frame information array (16GB). */
211 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
212 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
213 /* Slot 261: ioremap()/fixmap area (16GB). */
214 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
215 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
216 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
217 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
218 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + (1UL << 30))
219 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
220 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
221 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + (1UL << 30))
222 /* Slot 261: xen text, static data and bss (1GB). */
223 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
224 #define XEN_VIRT_END (XEN_VIRT_START + (1UL << 30))
225 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
226 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
227 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
229 #ifndef __ASSEMBLY__
231 /* This is not a fixed value, just a lower limit. */
232 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
233 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
234 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
235 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
236 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
237 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
239 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
240 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
241 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
242 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
243 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
245 #endif
247 #define PGT_base_page_table PGT_l4_page_table
249 #define __HYPERVISOR_CS64 0xe008
250 #define __HYPERVISOR_CS32 0xe038
251 #define __HYPERVISOR_CS __HYPERVISOR_CS64
252 #define __HYPERVISOR_DS64 0x0000
253 #define __HYPERVISOR_DS32 0xe010
254 #define __HYPERVISOR_DS __HYPERVISOR_DS64
256 /* For generic assembly code: use macros to define operation/operand sizes. */
257 #define __OS "q" /* Operation Suffix */
258 #define __OP "r" /* Operand Prefix */
259 #define __FIXUP_ALIGN ".align 8"
260 #define __FIXUP_WORD ".quad"
262 #elif defined(__i386__)
264 #define CONFIG_X86_32 1
265 #define CONFIG_DOMAIN_PAGE 1
267 #define asmlinkage __attribute__((regparm(0)))
269 /*
270 * Memory layout (high to low): PAE-SIZE
271 * ------
272 * I/O remapping area ( 4MB)
273 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
274 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
275 * Shadow linear pagetable ( 8MB)
276 * Guest linear pagetable ( 8MB)
277 * Machine-to-physical translation table [writable] (16MB)
278 * Frame-info table (96MB)
279 * * Start of guest inaccessible area
280 * Machine-to-physical translation table [read-only] (16MB)
281 * * Start of guest unmodifiable area
282 */
284 #define IOREMAP_MBYTES 4
285 #define DIRECTMAP_MBYTES 12
286 #define MAPCACHE_MBYTES 4
287 #define PERDOMAIN_MBYTES 8
289 #define LINEARPT_MBYTES 8
290 #define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
291 #define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
293 #define IOREMAP_VIRT_END 0UL
294 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
295 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
296 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
297 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
298 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
299 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
300 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
301 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
302 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
303 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
304 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
305 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
306 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
307 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
308 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
309 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
310 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
312 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
314 /* Maximum linear address accessible via guest memory segments. */
315 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
317 /* Hypervisor owns top 168MB of virtual address space. */
318 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
320 #define L2_PAGETABLE_FIRST_XEN_SLOT \
321 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
322 #define L2_PAGETABLE_LAST_XEN_SLOT \
323 (~0UL >> L2_PAGETABLE_SHIFT)
324 #define L2_PAGETABLE_XEN_SLOTS \
325 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
327 #define PGT_base_page_table PGT_l3_page_table
329 #define __HYPERVISOR_CS 0xe008
330 #define __HYPERVISOR_DS 0xe010
332 /* For generic assembly code: use macros to define operation/operand sizes. */
333 #define __OS "l" /* Operation Suffix */
334 #define __OP "e" /* Operand Prefix */
335 #define __FIXUP_ALIGN ".align 4"
336 #define __FIXUP_WORD ".long"
338 #endif /* __i386__ */
340 #ifndef __ASSEMBLY__
341 extern unsigned long xen_phys_start;
342 #if defined(__i386__)
343 extern unsigned long xenheap_phys_end;
344 #endif
345 #endif
347 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
348 #define GDT_LDT_VCPU_SHIFT 5
349 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
350 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
351 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
352 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
354 /* The address of a particular VCPU's GDT or LDT. */
355 #define GDT_VIRT_START(v) \
356 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
357 #define LDT_VIRT_START(v) \
358 (GDT_VIRT_START(v) + (64*1024))
360 #define PDPT_L1_ENTRIES \
361 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
362 #define PDPT_L2_ENTRIES \
363 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
365 #if defined(__x86_64__)
366 #define ELFSIZE 64
367 #else
368 #define ELFSIZE 32
369 #endif
371 #define ARCH_CRASH_SAVE_VMCOREINFO
373 #endif /* __X86_CONFIG_H__ */