ia64/xen-unstable

view xen/arch/x86/smpboot.c @ 10293:4122e88b6c75

Move idle-vcpu allocation logic to a common function.
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Fri Jun 02 09:31:35 2006 +0100 (2006-06-02)
parents 9f937ecc4f54
children 53f552ad4042
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <xen/config.h>
37 #include <xen/init.h>
38 #include <xen/kernel.h>
39 #include <xen/mm.h>
40 #include <xen/domain.h>
41 #include <xen/sched.h>
42 #include <xen/irq.h>
43 #include <xen/delay.h>
44 #include <xen/softirq.h>
45 #include <xen/serial.h>
46 #include <asm/current.h>
47 #include <asm/mc146818rtc.h>
48 #include <asm/desc.h>
49 #include <asm/div64.h>
50 #include <asm/flushtlb.h>
51 #include <asm/msr.h>
52 #include <mach_apic.h>
53 #include <mach_wakecpu.h>
54 #include <smpboot_hooks.h>
56 static inline int set_kernel_exec(unsigned long x, int y) { return 0; }
57 #define alloc_bootmem_low_pages(x) __va(0x90000) /* trampoline address */
59 /* Set if we find a B stepping CPU */
60 static int __devinitdata smp_b_stepping;
62 /* Number of siblings per CPU package */
63 int smp_num_siblings = 1;
64 #ifdef CONFIG_X86_HT
65 EXPORT_SYMBOL(smp_num_siblings);
66 #endif
68 /* Package ID of each logical CPU */
69 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
71 /* Core ID of each logical CPU */
72 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
74 /* representing HT siblings of each logical CPU */
75 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
76 EXPORT_SYMBOL(cpu_sibling_map);
78 /* representing HT and core siblings of each logical CPU */
79 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
80 EXPORT_SYMBOL(cpu_core_map);
82 /* bitmap of online cpus */
83 cpumask_t cpu_online_map __read_mostly;
84 EXPORT_SYMBOL(cpu_online_map);
86 cpumask_t cpu_callin_map;
87 cpumask_t cpu_callout_map;
88 EXPORT_SYMBOL(cpu_callout_map);
89 #ifdef CONFIG_HOTPLUG_CPU
90 cpumask_t cpu_possible_map = CPU_MASK_ALL;
91 #else
92 cpumask_t cpu_possible_map;
93 #endif
94 EXPORT_SYMBOL(cpu_possible_map);
95 static cpumask_t smp_commenced_mask;
97 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
98 * is no way to resync one AP against BP. TBD: for prescott and above, we
99 * should use IA64's algorithm
100 */
101 static int __devinitdata tsc_sync_disabled;
103 /* Per CPU bogomips and other parameters */
104 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
105 EXPORT_SYMBOL(cpu_data);
107 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
108 { [0 ... NR_CPUS-1] = 0xff };
109 EXPORT_SYMBOL(x86_cpu_to_apicid);
111 /*
112 * Trampoline 80x86 program as an array.
113 */
115 extern unsigned char trampoline_data [];
116 extern unsigned char trampoline_end [];
117 static unsigned char *trampoline_base;
118 static int trampoline_exec;
120 static void map_cpu_to_logical_apicid(void);
122 /* State of each CPU. */
123 /*DEFINE_PER_CPU(int, cpu_state) = { 0 };*/
125 /*
126 * Currently trivial. Write the real->protected mode
127 * bootstrap into the page concerned. The caller
128 * has made sure it's suitably aligned.
129 */
131 static unsigned long __devinit setup_trampoline(void)
132 {
133 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
134 return virt_to_maddr(trampoline_base);
135 }
137 /*
138 * We are called very early to get the low memory for the
139 * SMP bootup trampoline page.
140 */
141 void __init smp_alloc_memory(void)
142 {
143 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
144 /*
145 * Has to be in very low memory so we can execute
146 * real-mode AP code.
147 */
148 if (__pa(trampoline_base) >= 0x9F000)
149 BUG();
150 /*
151 * Make the SMP trampoline executable:
152 */
153 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
154 }
156 /*
157 * The bootstrap kernel entry code has set these up. Save them for
158 * a given CPU
159 */
161 static void __devinit smp_store_cpu_info(int id)
162 {
163 struct cpuinfo_x86 *c = cpu_data + id;
165 *c = boot_cpu_data;
166 if (id!=0)
167 identify_cpu(c);
168 /*
169 * Mask B, Pentium, but not Pentium MMX
170 */
171 if (c->x86_vendor == X86_VENDOR_INTEL &&
172 c->x86 == 5 &&
173 c->x86_mask >= 1 && c->x86_mask <= 4 &&
174 c->x86_model <= 3)
175 /*
176 * Remember we have B step Pentia with bugs
177 */
178 smp_b_stepping = 1;
180 /*
181 * Certain Athlons might work (for various values of 'work') in SMP
182 * but they are not certified as MP capable.
183 */
184 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
186 /* Athlon 660/661 is valid. */
187 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
188 goto valid_k7;
190 /* Duron 670 is valid */
191 if ((c->x86_model==7) && (c->x86_mask==0))
192 goto valid_k7;
194 /*
195 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
196 * It's worth noting that the A5 stepping (662) of some Athlon XP's
197 * have the MP bit set.
198 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
199 */
200 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
201 ((c->x86_model==7) && (c->x86_mask>=1)) ||
202 (c->x86_model> 7))
203 if (cpu_has_mp)
204 goto valid_k7;
206 /* If we get here, it's not a certified SMP capable AMD system. */
207 add_taint(TAINT_UNSAFE_SMP);
208 }
210 valid_k7:
211 ;
212 }
214 /*
215 * TSC synchronization.
216 *
217 * We first check whether all CPUs have their TSC's synchronized,
218 * then we print a warning if not, and always resync.
219 */
221 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
222 static atomic_t tsc_count_start = ATOMIC_INIT(0);
223 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
224 static unsigned long long tsc_values[NR_CPUS];
226 #define NR_LOOPS 5
228 static void __init synchronize_tsc_bp (void)
229 {
230 int i;
231 unsigned long long t0;
232 unsigned long long sum, avg;
233 long long delta;
234 unsigned int one_usec;
235 int buggy = 0;
237 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
239 /* convert from kcyc/sec to cyc/usec */
240 one_usec = cpu_khz / 1000;
242 atomic_set(&tsc_start_flag, 1);
243 wmb();
245 /*
246 * We loop a few times to get a primed instruction cache,
247 * then the last pass is more or less synchronized and
248 * the BP and APs set their cycle counters to zero all at
249 * once. This reduces the chance of having random offsets
250 * between the processors, and guarantees that the maximum
251 * delay between the cycle counters is never bigger than
252 * the latency of information-passing (cachelines) between
253 * two CPUs.
254 */
255 for (i = 0; i < NR_LOOPS; i++) {
256 /*
257 * all APs synchronize but they loop on '== num_cpus'
258 */
259 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
260 mb();
261 atomic_set(&tsc_count_stop, 0);
262 wmb();
263 /*
264 * this lets the APs save their current TSC:
265 */
266 atomic_inc(&tsc_count_start);
268 rdtscll(tsc_values[smp_processor_id()]);
269 /*
270 * We clear the TSC in the last loop:
271 */
272 if (i == NR_LOOPS-1)
273 write_tsc(0, 0);
275 /*
276 * Wait for all APs to leave the synchronization point:
277 */
278 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
279 mb();
280 atomic_set(&tsc_count_start, 0);
281 wmb();
282 atomic_inc(&tsc_count_stop);
283 }
285 sum = 0;
286 for (i = 0; i < NR_CPUS; i++) {
287 if (cpu_isset(i, cpu_callout_map)) {
288 t0 = tsc_values[i];
289 sum += t0;
290 }
291 }
292 avg = sum;
293 do_div(avg, num_booting_cpus());
295 sum = 0;
296 for (i = 0; i < NR_CPUS; i++) {
297 if (!cpu_isset(i, cpu_callout_map))
298 continue;
299 delta = tsc_values[i] - avg;
300 if (delta < 0)
301 delta = -delta;
302 /*
303 * We report bigger than 2 microseconds clock differences.
304 */
305 if (delta > 2*one_usec) {
306 long realdelta;
307 if (!buggy) {
308 buggy = 1;
309 printk("\n");
310 }
311 realdelta = delta;
312 do_div(realdelta, one_usec);
313 if (tsc_values[i] < avg)
314 realdelta = -realdelta;
316 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
317 }
319 sum += delta;
320 }
321 if (!buggy)
322 printk("passed.\n");
323 }
325 static void __init synchronize_tsc_ap (void)
326 {
327 int i;
329 /*
330 * Not every cpu is online at the time
331 * this gets called, so we first wait for the BP to
332 * finish SMP initialization:
333 */
334 while (!atomic_read(&tsc_start_flag)) mb();
336 for (i = 0; i < NR_LOOPS; i++) {
337 atomic_inc(&tsc_count_start);
338 while (atomic_read(&tsc_count_start) != num_booting_cpus())
339 mb();
341 rdtscll(tsc_values[smp_processor_id()]);
342 if (i == NR_LOOPS-1)
343 write_tsc(0, 0);
345 atomic_inc(&tsc_count_stop);
346 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
347 }
348 }
349 #undef NR_LOOPS
351 extern void calibrate_delay(void);
353 static atomic_t init_deasserted;
355 void __devinit smp_callin(void)
356 {
357 int cpuid, phys_id, i;
359 /*
360 * If waken up by an INIT in an 82489DX configuration
361 * we may get here before an INIT-deassert IPI reaches
362 * our local APIC. We have to wait for the IPI or we'll
363 * lock up on an APIC access.
364 */
365 wait_for_init_deassert(&init_deasserted);
367 /*
368 * (This works even if the APIC is not enabled.)
369 */
370 phys_id = GET_APIC_ID(apic_read(APIC_ID));
371 cpuid = smp_processor_id();
372 if (cpu_isset(cpuid, cpu_callin_map)) {
373 printk("huh, phys CPU#%d, CPU#%d already present??\n",
374 phys_id, cpuid);
375 BUG();
376 }
377 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
379 /*
380 * STARTUP IPIs are fragile beasts as they might sometimes
381 * trigger some glue motherboard logic. Complete APIC bus
382 * silence for 1 second, this overestimates the time the
383 * boot CPU is spending to send the up to 2 STARTUP IPIs
384 * by a factor of two. This should be enough.
385 */
387 /*
388 * Waiting 2s total for startup
389 */
390 for (i = 0; i < 200; i++) {
391 /*
392 * Has the boot CPU finished it's STARTUP sequence?
393 */
394 if (cpu_isset(cpuid, cpu_callout_map))
395 break;
396 rep_nop();
397 mdelay(10);
398 }
400 if (!cpu_isset(cpuid, cpu_callout_map)) {
401 printk("BUG: CPU%d started up but did not get a callout!\n",
402 cpuid);
403 BUG();
404 }
406 /*
407 * the boot CPU has finished the init stage and is spinning
408 * on callin_map until we finish. We are free to set up this
409 * CPU, first the APIC. (this is probably redundant on most
410 * boards)
411 */
413 Dprintk("CALLIN, before setup_local_APIC().\n");
414 smp_callin_clear_local_apic();
415 setup_local_APIC();
416 map_cpu_to_logical_apicid();
418 #if 0
419 /*
420 * Get our bogomips.
421 */
422 calibrate_delay();
423 Dprintk("Stack at about %p\n",&cpuid);
424 #endif
426 /*
427 * Save our processor parameters
428 */
429 smp_store_cpu_info(cpuid);
431 disable_APIC_timer();
433 /*
434 * Allow the master to continue.
435 */
436 cpu_set(cpuid, cpu_callin_map);
438 /*
439 * Synchronize the TSC with the BP
440 */
441 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
442 synchronize_tsc_ap();
443 calibrate_tsc_ap();
444 }
446 static int cpucount, booting_cpu;
448 /* representing cpus for which sibling maps can be computed */
449 static cpumask_t cpu_sibling_setup_map;
451 static inline void
452 set_cpu_sibling_map(int cpu)
453 {
454 int i;
455 struct cpuinfo_x86 *c = cpu_data;
457 cpu_set(cpu, cpu_sibling_setup_map);
459 if (smp_num_siblings > 1) {
460 for_each_cpu_mask(i, cpu_sibling_setup_map) {
461 if (phys_proc_id[cpu] == phys_proc_id[i] &&
462 cpu_core_id[cpu] == cpu_core_id[i]) {
463 cpu_set(i, cpu_sibling_map[cpu]);
464 cpu_set(cpu, cpu_sibling_map[i]);
465 cpu_set(i, cpu_core_map[cpu]);
466 cpu_set(cpu, cpu_core_map[i]);
467 }
468 }
469 } else {
470 cpu_set(cpu, cpu_sibling_map[cpu]);
471 }
473 if (current_cpu_data.x86_max_cores == 1) {
474 cpu_core_map[cpu] = cpu_sibling_map[cpu];
475 c[cpu].booted_cores = 1;
476 return;
477 }
479 for_each_cpu_mask(i, cpu_sibling_setup_map) {
480 if (phys_proc_id[cpu] == phys_proc_id[i]) {
481 cpu_set(i, cpu_core_map[cpu]);
482 cpu_set(cpu, cpu_core_map[i]);
483 /*
484 * Does this new cpu bringup a new core?
485 */
486 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
487 /*
488 * for each core in package, increment
489 * the booted_cores for this new cpu
490 */
491 if (first_cpu(cpu_sibling_map[i]) == i)
492 c[cpu].booted_cores++;
493 /*
494 * increment the core count for all
495 * the other cpus in this package
496 */
497 if (i != cpu)
498 c[i].booted_cores++;
499 } else if (i != cpu && !c[cpu].booted_cores)
500 c[cpu].booted_cores = c[i].booted_cores;
501 }
502 }
503 }
505 #ifdef CONFIG_X86_32
506 static void construct_percpu_idt(unsigned int cpu)
507 {
508 unsigned char idt_load[10];
510 idt_tables[cpu] = xmalloc_array(idt_entry_t, IDT_ENTRIES);
511 memcpy(idt_tables[cpu], idt_table, IDT_ENTRIES*sizeof(idt_entry_t));
513 *(unsigned short *)(&idt_load[0]) = (IDT_ENTRIES*sizeof(idt_entry_t))-1;
514 *(unsigned long *)(&idt_load[2]) = (unsigned long)idt_tables[cpu];
515 __asm__ __volatile__ ( "lidt %0" : "=m" (idt_load) );
516 }
517 #endif
519 /*
520 * Activate a secondary processor.
521 */
522 void __devinit start_secondary(void *unused)
523 {
524 /*
525 * Dont put anything before smp_callin(), SMP
526 * booting is too fragile that we want to limit the
527 * things done here to the most necessary things.
528 */
529 unsigned int cpu = booting_cpu;
531 extern void percpu_traps_init(void);
533 set_processor_id(cpu);
534 set_current(idle_vcpu[cpu]);
535 this_cpu(curr_vcpu) = idle_vcpu[cpu];
537 percpu_traps_init();
539 cpu_init();
540 /*preempt_disable();*/
541 smp_callin();
542 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
543 rep_nop();
545 #ifdef CONFIG_X86_32
546 /*
547 * At this point, boot CPU has fully initialised the IDT. It is
548 * now safe to make ourselves a private copy.
549 */
550 construct_percpu_idt(cpu);
551 #endif
553 setup_secondary_APIC_clock();
554 enable_APIC_timer();
555 /*
556 * low-memory mappings have been cleared, flush them from
557 * the local TLBs too.
558 */
559 local_flush_tlb();
561 /* This must be done before setting cpu_online_map */
562 set_cpu_sibling_map(raw_smp_processor_id());
563 wmb();
565 /*
566 * We need to hold call_lock, so there is no inconsistency
567 * between the time smp_call_function() determines number of
568 * IPI receipients, and the time when the determination is made
569 * for which cpus receive the IPI. Holding this
570 * lock helps us to not include this cpu in a currently in progress
571 * smp_call_function().
572 */
573 /*lock_ipi_call_lock();*/
574 cpu_set(smp_processor_id(), cpu_online_map);
575 /*unlock_ipi_call_lock();*/
576 /*per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;*/
578 /* We can take interrupts now: we're officially "up". */
579 local_irq_enable();
581 init_percpu_time();
583 wmb();
584 startup_cpu_idle_loop();
585 }
587 extern struct {
588 void * esp;
589 unsigned short ss;
590 } stack_start;
592 #ifdef CONFIG_NUMA
594 /* which logical CPUs are on which nodes */
595 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
596 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
597 /* which node each logical CPU is on */
598 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
599 EXPORT_SYMBOL(cpu_2_node);
601 /* set up a mapping between cpu and node. */
602 static inline void map_cpu_to_node(int cpu, int node)
603 {
604 printk("Mapping cpu %d to node %d\n", cpu, node);
605 cpu_set(cpu, node_2_cpu_mask[node]);
606 cpu_2_node[cpu] = node;
607 }
609 /* undo a mapping between cpu and node. */
610 static inline void unmap_cpu_to_node(int cpu)
611 {
612 int node;
614 printk("Unmapping cpu %d from all nodes\n", cpu);
615 for (node = 0; node < MAX_NUMNODES; node ++)
616 cpu_clear(cpu, node_2_cpu_mask[node]);
617 cpu_2_node[cpu] = 0;
618 }
619 #else /* !CONFIG_NUMA */
621 #define map_cpu_to_node(cpu, node) ({})
622 #define unmap_cpu_to_node(cpu) ({})
624 #endif /* CONFIG_NUMA */
626 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
628 static void map_cpu_to_logical_apicid(void)
629 {
630 int cpu = smp_processor_id();
631 int apicid = logical_smp_processor_id();
633 cpu_2_logical_apicid[cpu] = apicid;
634 map_cpu_to_node(cpu, apicid_to_node(apicid));
635 }
637 static void unmap_cpu_to_logical_apicid(int cpu)
638 {
639 cpu_2_logical_apicid[cpu] = BAD_APICID;
640 unmap_cpu_to_node(cpu);
641 }
643 #if APIC_DEBUG
644 static inline void __inquire_remote_apic(int apicid)
645 {
646 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
647 char *names[] = { "ID", "VERSION", "SPIV" };
648 int timeout, status;
650 printk("Inquiring remote APIC #%d...\n", apicid);
652 for (i = 0; i < ARRAY_SIZE(regs); i++) {
653 printk("... APIC #%d %s: ", apicid, names[i]);
655 /*
656 * Wait for idle.
657 */
658 apic_wait_icr_idle();
660 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
661 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
663 timeout = 0;
664 do {
665 udelay(100);
666 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
667 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
669 switch (status) {
670 case APIC_ICR_RR_VALID:
671 status = apic_read(APIC_RRR);
672 printk("%08x\n", status);
673 break;
674 default:
675 printk("failed\n");
676 }
677 }
678 }
679 #endif
681 #ifdef WAKE_SECONDARY_VIA_NMI
682 /*
683 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
684 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
685 * won't ... remember to clear down the APIC, etc later.
686 */
687 static int __devinit
688 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
689 {
690 unsigned long send_status = 0, accept_status = 0;
691 int timeout, maxlvt;
693 /* Target chip */
694 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
696 /* Boot on the stack */
697 /* Kick the second */
698 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
700 Dprintk("Waiting for send to finish...\n");
701 timeout = 0;
702 do {
703 Dprintk("+");
704 udelay(100);
705 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
706 } while (send_status && (timeout++ < 1000));
708 /*
709 * Give the other CPU some time to accept the IPI.
710 */
711 udelay(200);
712 /*
713 * Due to the Pentium erratum 3AP.
714 */
715 maxlvt = get_maxlvt();
716 if (maxlvt > 3) {
717 apic_read_around(APIC_SPIV);
718 apic_write(APIC_ESR, 0);
719 }
720 accept_status = (apic_read(APIC_ESR) & 0xEF);
721 Dprintk("NMI sent.\n");
723 if (send_status)
724 printk("APIC never delivered???\n");
725 if (accept_status)
726 printk("APIC delivery error (%lx).\n", accept_status);
728 return (send_status | accept_status);
729 }
730 #endif /* WAKE_SECONDARY_VIA_NMI */
732 #ifdef WAKE_SECONDARY_VIA_INIT
733 static int __devinit
734 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
735 {
736 unsigned long send_status = 0, accept_status = 0;
737 int maxlvt, timeout, num_starts, j;
739 /*
740 * Be paranoid about clearing APIC errors.
741 */
742 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
743 apic_read_around(APIC_SPIV);
744 apic_write(APIC_ESR, 0);
745 apic_read(APIC_ESR);
746 }
748 Dprintk("Asserting INIT.\n");
750 /*
751 * Turn INIT on target chip
752 */
753 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
755 /*
756 * Send IPI
757 */
758 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
759 | APIC_DM_INIT);
761 Dprintk("Waiting for send to finish...\n");
762 timeout = 0;
763 do {
764 Dprintk("+");
765 udelay(100);
766 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
767 } while (send_status && (timeout++ < 1000));
769 mdelay(10);
771 Dprintk("Deasserting INIT.\n");
773 /* Target chip */
774 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
776 /* Send IPI */
777 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
779 Dprintk("Waiting for send to finish...\n");
780 timeout = 0;
781 do {
782 Dprintk("+");
783 udelay(100);
784 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
785 } while (send_status && (timeout++ < 1000));
787 atomic_set(&init_deasserted, 1);
789 /*
790 * Should we send STARTUP IPIs ?
791 *
792 * Determine this based on the APIC version.
793 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
794 */
795 if (APIC_INTEGRATED(apic_version[phys_apicid]))
796 num_starts = 2;
797 else
798 num_starts = 0;
800 /*
801 * Run STARTUP IPI loop.
802 */
803 Dprintk("#startup loops: %d.\n", num_starts);
805 maxlvt = get_maxlvt();
807 for (j = 1; j <= num_starts; j++) {
808 Dprintk("Sending STARTUP #%d.\n",j);
809 apic_read_around(APIC_SPIV);
810 apic_write(APIC_ESR, 0);
811 apic_read(APIC_ESR);
812 Dprintk("After apic_write.\n");
814 /*
815 * STARTUP IPI
816 */
818 /* Target chip */
819 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
821 /* Boot on the stack */
822 /* Kick the second */
823 apic_write_around(APIC_ICR, APIC_DM_STARTUP
824 | (start_eip >> 12));
826 /*
827 * Give the other CPU some time to accept the IPI.
828 */
829 udelay(300);
831 Dprintk("Startup point 1.\n");
833 Dprintk("Waiting for send to finish...\n");
834 timeout = 0;
835 do {
836 Dprintk("+");
837 udelay(100);
838 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
839 } while (send_status && (timeout++ < 1000));
841 /*
842 * Give the other CPU some time to accept the IPI.
843 */
844 udelay(200);
845 /*
846 * Due to the Pentium erratum 3AP.
847 */
848 if (maxlvt > 3) {
849 apic_read_around(APIC_SPIV);
850 apic_write(APIC_ESR, 0);
851 }
852 accept_status = (apic_read(APIC_ESR) & 0xEF);
853 if (send_status || accept_status)
854 break;
855 }
856 Dprintk("After Startup.\n");
858 if (send_status)
859 printk("APIC never delivered???\n");
860 if (accept_status)
861 printk("APIC delivery error (%lx).\n", accept_status);
863 return (send_status | accept_status);
864 }
865 #endif /* WAKE_SECONDARY_VIA_INIT */
867 extern cpumask_t cpu_initialized;
868 static inline int alloc_cpu_id(void)
869 {
870 cpumask_t tmp_map;
871 int cpu;
872 cpus_complement(tmp_map, cpu_present_map);
873 cpu = first_cpu(tmp_map);
874 if (cpu >= NR_CPUS)
875 return -ENODEV;
876 return cpu;
877 }
879 static int __devinit do_boot_cpu(int apicid, int cpu)
880 /*
881 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
882 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
883 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
884 */
885 {
886 unsigned long boot_error;
887 int timeout;
888 unsigned long start_eip;
889 unsigned short nmi_high = 0, nmi_low = 0;
890 struct vcpu *v;
892 ++cpucount;
894 booting_cpu = cpu;
896 v = alloc_idle_vcpu(cpu);
897 BUG_ON(v == NULL);
899 v->arch.monitor_table = pagetable_from_paddr(__pa(idle_pg_table));
901 /* start_eip had better be page-aligned! */
902 start_eip = setup_trampoline();
904 /* So we see what's up */
905 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
907 stack_start.esp = alloc_xenheap_pages(STACK_ORDER);
909 /* Debug build: detect stack overflow by setting up a guard page. */
910 memguard_guard_stack(stack_start.esp);
912 /*
913 * This grunge runs the startup process for
914 * the targeted processor.
915 */
917 atomic_set(&init_deasserted, 0);
919 Dprintk("Setting warm reset code and vector.\n");
921 store_NMI_vector(&nmi_high, &nmi_low);
923 smpboot_setup_warm_reset_vector(start_eip);
925 /*
926 * Starting actual IPI sequence...
927 */
928 boot_error = wakeup_secondary_cpu(apicid, start_eip);
930 if (!boot_error) {
931 /*
932 * allow APs to start initializing.
933 */
934 Dprintk("Before Callout %d.\n", cpu);
935 cpu_set(cpu, cpu_callout_map);
936 Dprintk("After Callout %d.\n", cpu);
938 /*
939 * Wait 5s total for a response
940 */
941 for (timeout = 0; timeout < 50000; timeout++) {
942 if (cpu_isset(cpu, cpu_callin_map))
943 break; /* It has booted */
944 udelay(100);
945 }
947 if (cpu_isset(cpu, cpu_callin_map)) {
948 /* number CPUs logically, starting from 1 (BSP is 0) */
949 Dprintk("OK.\n");
950 printk("CPU%d: ", cpu);
951 print_cpu_info(&cpu_data[cpu]);
952 Dprintk("CPU has booted.\n");
953 } else {
954 boot_error= 1;
955 if (*((volatile unsigned char *)trampoline_base)
956 == 0xA5)
957 /* trampoline started but...? */
958 printk("Stuck ??\n");
959 else
960 /* trampoline code not run */
961 printk("Not responding.\n");
962 inquire_remote_apic(apicid);
963 }
964 }
966 if (boot_error) {
967 /* Try to put things back the way they were before ... */
968 unmap_cpu_to_logical_apicid(cpu);
969 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
970 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
971 cpucount--;
972 } else {
973 x86_cpu_to_apicid[cpu] = apicid;
974 cpu_set(cpu, cpu_present_map);
975 }
977 /* mark "stuck" area as not stuck */
978 *((volatile unsigned long *)trampoline_base) = 0;
980 return boot_error;
981 }
983 /*
984 * Cycle through the processors sending APIC IPIs to boot each.
985 */
987 static int boot_cpu_logical_apicid;
988 /* Where the IO area was mapped on multiquad, always 0 otherwise */
989 void *xquad_portio;
990 #ifdef CONFIG_X86_NUMAQ
991 EXPORT_SYMBOL(xquad_portio);
992 #endif
994 static void __init smp_boot_cpus(unsigned int max_cpus)
995 {
996 int apicid, cpu, bit, kicked;
997 #ifdef BOGOMIPS
998 unsigned long bogosum = 0;
999 #endif
1001 /*
1002 * Setup boot CPU information
1003 */
1004 smp_store_cpu_info(0); /* Final full version of the data */
1005 printk("CPU%d: ", 0);
1006 print_cpu_info(&cpu_data[0]);
1008 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1009 boot_cpu_logical_apicid = logical_smp_processor_id();
1010 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1012 /*current_thread_info()->cpu = 0;*/
1013 /*smp_tune_scheduling();*/
1015 set_cpu_sibling_map(0);
1017 /*
1018 * If we couldn't find an SMP configuration at boot time,
1019 * get out of here now!
1020 */
1021 if (!smp_found_config && !acpi_lapic) {
1022 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1023 init_uniprocessor:
1024 phys_cpu_present_map = physid_mask_of_physid(0);
1025 if (APIC_init_uniprocessor())
1026 printk(KERN_NOTICE "Local APIC not detected."
1027 " Using dummy APIC emulation.\n");
1028 map_cpu_to_logical_apicid();
1029 cpu_set(0, cpu_sibling_map[0]);
1030 cpu_set(0, cpu_core_map[0]);
1031 return;
1034 /*
1035 * Should not be necessary because the MP table should list the boot
1036 * CPU too, but we do it for the sake of robustness anyway.
1037 * Makes no sense to do this check in clustered apic mode, so skip it
1038 */
1039 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1040 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1041 boot_cpu_physical_apicid);
1042 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1045 /*
1046 * If we couldn't find a local APIC, then get out of here now!
1047 */
1048 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1049 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1050 boot_cpu_physical_apicid);
1051 goto init_uniprocessor;
1054 verify_local_APIC();
1056 /*
1057 * If SMP should be disabled, then really disable it!
1058 */
1059 if (!max_cpus)
1060 goto init_uniprocessor;
1062 connect_bsp_APIC();
1063 setup_local_APIC();
1064 map_cpu_to_logical_apicid();
1067 setup_portio_remap();
1069 /*
1070 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1072 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1073 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1074 * clustered apic ID.
1075 */
1076 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1078 kicked = 1;
1079 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1080 apicid = cpu_present_to_apicid(bit);
1081 /*
1082 * Don't even attempt to start the boot CPU!
1083 */
1084 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1085 continue;
1087 if (!check_apicid_present(apicid))
1088 continue;
1089 if (max_cpus <= cpucount+1)
1090 continue;
1092 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1093 printk("CPU #%d not responding - cannot use it.\n",
1094 apicid);
1095 else
1096 ++kicked;
1099 /*
1100 * Cleanup possible dangling ends...
1101 */
1102 smpboot_restore_warm_reset_vector();
1104 #ifdef BOGOMIPS
1105 /*
1106 * Allow the user to impress friends.
1107 */
1108 Dprintk("Before bogomips.\n");
1109 for (cpu = 0; cpu < NR_CPUS; cpu++)
1110 if (cpu_isset(cpu, cpu_callout_map))
1111 bogosum += cpu_data[cpu].loops_per_jiffy;
1112 printk(KERN_INFO
1113 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1114 cpucount+1,
1115 bogosum/(500000/HZ),
1116 (bogosum/(5000/HZ))%100);
1117 #else
1118 printk("Total of %d processors activated.\n", cpucount+1);
1119 #endif
1121 Dprintk("Before bogocount - setting activated=1.\n");
1123 if (smp_b_stepping)
1124 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1126 /*
1127 * Don't taint if we are running SMP kernel on a single non-MP
1128 * approved Athlon
1129 */
1130 if (tainted & TAINT_UNSAFE_SMP) {
1131 if (cpucount)
1132 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1133 else
1134 tainted &= ~TAINT_UNSAFE_SMP;
1137 Dprintk("Boot done.\n");
1139 /*
1140 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1141 * efficiently.
1142 */
1143 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1144 cpus_clear(cpu_sibling_map[cpu]);
1145 cpus_clear(cpu_core_map[cpu]);
1148 cpu_set(0, cpu_sibling_map[0]);
1149 cpu_set(0, cpu_core_map[0]);
1151 if (nmi_watchdog == NMI_LOCAL_APIC)
1152 check_nmi_watchdog();
1154 smpboot_setup_io_apic();
1156 setup_boot_APIC_clock();
1158 /*
1159 * Synchronize the TSC with the AP
1160 */
1161 if (cpu_has_tsc && cpucount && cpu_khz)
1162 synchronize_tsc_bp();
1163 calibrate_tsc_bp();
1166 /* These are wrappers to interface to the new boot process. Someone
1167 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1168 void __init smp_prepare_cpus(unsigned int max_cpus)
1170 smp_commenced_mask = cpumask_of_cpu(0);
1171 cpu_callin_map = cpumask_of_cpu(0);
1172 mb();
1173 smp_boot_cpus(max_cpus);
1176 void __devinit smp_prepare_boot_cpu(void)
1178 cpu_set(smp_processor_id(), cpu_online_map);
1179 cpu_set(smp_processor_id(), cpu_callout_map);
1180 cpu_set(smp_processor_id(), cpu_present_map);
1181 cpu_set(smp_processor_id(), cpu_possible_map);
1182 /*per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;*/
1185 int __devinit __cpu_up(unsigned int cpu)
1187 /* In case one didn't come up */
1188 if (!cpu_isset(cpu, cpu_callin_map)) {
1189 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1190 local_irq_enable();
1191 return -EIO;
1194 local_irq_enable();
1195 /*per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;*/
1196 /* Unleash the CPU! */
1197 cpu_set(cpu, smp_commenced_mask);
1198 while (!cpu_isset(cpu, cpu_online_map)) {
1199 mb();
1200 if (softirq_pending(0))
1201 do_softirq();
1203 return 0;
1206 void __init smp_cpus_done(unsigned int max_cpus)
1208 #ifdef CONFIG_X86_IO_APIC
1209 setup_ioapic_dest();
1210 #endif
1211 #ifdef CONFIG_X86_64
1212 zap_low_mappings();
1213 #endif
1214 #ifndef CONFIG_HOTPLUG_CPU
1215 /*
1216 * Disable executability of the SMP trampoline:
1217 */
1218 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1219 #endif
1222 void __init smp_intr_init(void)
1224 int irq, seridx;
1226 /*
1227 * IRQ0 must be given a fixed assignment and initialized,
1228 * because it's used before the IO-APIC is set up.
1229 */
1230 irq_vector[0] = FIRST_HIPRIORITY_VECTOR;
1231 vector_irq[FIRST_HIPRIORITY_VECTOR] = 0;
1233 /*
1234 * Also ensure serial interrupts are high priority. We do not
1235 * want them to be blocked by unacknowledged guest-bound interrupts.
1236 */
1237 for (seridx = 0; seridx < 2; seridx++) {
1238 if ((irq = serial_irq(seridx)) < 0)
1239 continue;
1240 irq_vector[irq] = FIRST_HIPRIORITY_VECTOR + seridx + 1;
1241 vector_irq[FIRST_HIPRIORITY_VECTOR + seridx + 1] = irq;
1244 /* IPI for event checking. */
1245 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
1247 /* IPI for invalidation */
1248 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1250 /* IPI for generic function call */
1251 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);