ia64/xen-unstable

view tools/ioemu/hw/rtl8139.c @ 17422:40c0dda6eae6

ioemu: Fix rtl8139 emulation so that reboot works correctly in 64-bit
Windows VMs. Return an error if the guest OS tries to transmit a
packet with the transmitter disabled, so that it doesn't spin forever
waiting for it to complete.

Signed-off-by: Steven Smith <Steven.Smith@eu.citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Apr 09 16:03:40 2008 +0100 (2008-04-09)
parents e6cf98edf0c5
children
line source
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 */
46 #include "vl.h"
48 /* debug RTL8139 card */
49 //#define DEBUG_RTL8139 1
51 #define PCI_FREQUENCY 33000000L
53 /* debug RTL8139 card C+ mode only */
54 //#define DEBUG_RTL8139CP 1
56 /* Calculate CRCs propoerly on Rx packets */
57 #define RTL8139_CALCULATE_RXCRC 1
59 /* Uncomment to enable on-board timer interrupts */
60 //#define RTL8139_ONBOARD_TIMER 1
62 #if defined(RTL8139_CALCULATE_RXCRC)
63 /* For crc32 */
64 #include <zlib.h>
65 #endif
67 #define SET_MASKED(input, mask, curr) \
68 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70 /* arg % size for size which is a power of 2 */
71 #define MOD2(input, size) \
72 ( ( input ) & ( size - 1 ) )
74 #if defined (DEBUG_RTL8139)
75 # define DEBUG_PRINT(x) do { printf x ; } while (0)
76 #else
77 # define DEBUG_PRINT(x)
78 #endif
80 /* Symbolic offsets to registers. */
81 enum RTL8139_registers {
82 MAC0 = 0, /* Ethernet hardware address. */
83 MAR0 = 8, /* Multicast filter. */
84 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
85 /* Dump Tally Conter control register(64bit). C+ mode only */
86 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
87 RxBuf = 0x30,
88 ChipCmd = 0x37,
89 RxBufPtr = 0x38,
90 RxBufAddr = 0x3A,
91 IntrMask = 0x3C,
92 IntrStatus = 0x3E,
93 TxConfig = 0x40,
94 RxConfig = 0x44,
95 Timer = 0x48, /* A general-purpose counter. */
96 RxMissed = 0x4C, /* 24 bits valid, write clears. */
97 Cfg9346 = 0x50,
98 Config0 = 0x51,
99 Config1 = 0x52,
100 FlashReg = 0x54,
101 MediaStatus = 0x58,
102 Config3 = 0x59,
103 Config4 = 0x5A, /* absent on RTL-8139A */
104 HltClk = 0x5B,
105 MultiIntr = 0x5C,
106 PCIRevisionID = 0x5E,
107 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
108 BasicModeCtrl = 0x62,
109 BasicModeStatus = 0x64,
110 NWayAdvert = 0x66,
111 NWayLPAR = 0x68,
112 NWayExpansion = 0x6A,
113 /* Undocumented registers, but required for proper operation. */
114 FIFOTMS = 0x70, /* FIFO Control and test. */
115 CSCR = 0x74, /* Chip Status and Configuration Register. */
116 PARA78 = 0x78,
117 PARA7c = 0x7c, /* Magic transceiver parameter register. */
118 Config5 = 0xD8, /* absent on RTL-8139A */
119 /* C+ mode */
120 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
121 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
122 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
123 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
124 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
125 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
126 TxThresh = 0xEC, /* Early Tx threshold */
127 };
129 enum ClearBitMasks {
130 MultiIntrClear = 0xF000,
131 ChipCmdClear = 0xE2,
132 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
133 };
135 enum ChipCmdBits {
136 CmdReset = 0x10,
137 CmdRxEnb = 0x08,
138 CmdTxEnb = 0x04,
139 RxBufEmpty = 0x01,
140 };
142 /* C+ mode */
143 enum CplusCmdBits {
144 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
145 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
146 CPlusRxEnb = 0x0002,
147 CPlusTxEnb = 0x0001,
148 };
150 /* Interrupt register bits, using my own meaningful names. */
151 enum IntrStatusBits {
152 PCIErr = 0x8000,
153 PCSTimeout = 0x4000,
154 RxFIFOOver = 0x40,
155 RxUnderrun = 0x20,
156 RxOverflow = 0x10,
157 TxErr = 0x08,
158 TxOK = 0x04,
159 RxErr = 0x02,
160 RxOK = 0x01,
162 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
163 };
165 enum TxStatusBits {
166 TxHostOwns = 0x2000,
167 TxUnderrun = 0x4000,
168 TxStatOK = 0x8000,
169 TxOutOfWindow = 0x20000000,
170 TxAborted = 0x40000000,
171 TxCarrierLost = 0x80000000,
172 };
173 enum RxStatusBits {
174 RxMulticast = 0x8000,
175 RxPhysical = 0x4000,
176 RxBroadcast = 0x2000,
177 RxBadSymbol = 0x0020,
178 RxRunt = 0x0010,
179 RxTooLong = 0x0008,
180 RxCRCErr = 0x0004,
181 RxBadAlign = 0x0002,
182 RxStatusOK = 0x0001,
183 };
185 /* Bits in RxConfig. */
186 enum rx_mode_bits {
187 AcceptErr = 0x20,
188 AcceptRunt = 0x10,
189 AcceptBroadcast = 0x08,
190 AcceptMulticast = 0x04,
191 AcceptMyPhys = 0x02,
192 AcceptAllPhys = 0x01,
193 };
195 /* Bits in TxConfig. */
196 enum tx_config_bits {
198 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
199 TxIFGShift = 24,
200 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
201 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
202 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
203 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
205 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
206 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
207 TxClearAbt = (1 << 0), /* Clear abort (WO) */
208 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
209 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
211 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
212 };
215 /* Transmit Status of All Descriptors (TSAD) Register */
216 enum TSAD_bits {
217 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
218 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
219 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
220 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
221 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
222 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
223 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
224 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
225 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
226 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
227 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
228 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
229 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
230 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
231 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
232 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
233 };
236 /* Bits in Config1 */
237 enum Config1Bits {
238 Cfg1_PM_Enable = 0x01,
239 Cfg1_VPD_Enable = 0x02,
240 Cfg1_PIO = 0x04,
241 Cfg1_MMIO = 0x08,
242 LWAKE = 0x10, /* not on 8139, 8139A */
243 Cfg1_Driver_Load = 0x20,
244 Cfg1_LED0 = 0x40,
245 Cfg1_LED1 = 0x80,
246 SLEEP = (1 << 1), /* only on 8139, 8139A */
247 PWRDN = (1 << 0), /* only on 8139, 8139A */
248 };
250 /* Bits in Config3 */
251 enum Config3Bits {
252 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
253 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
254 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
255 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
256 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
257 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
258 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
259 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
260 };
262 /* Bits in Config4 */
263 enum Config4Bits {
264 LWPTN = (1 << 2), /* not on 8139, 8139A */
265 };
267 /* Bits in Config5 */
268 enum Config5Bits {
269 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
270 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
271 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
272 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
273 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
274 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
275 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
276 };
278 enum RxConfigBits {
279 /* rx fifo threshold */
280 RxCfgFIFOShift = 13,
281 RxCfgFIFONone = (7 << RxCfgFIFOShift),
283 /* Max DMA burst */
284 RxCfgDMAShift = 8,
285 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
287 /* rx ring buffer length */
288 RxCfgRcv8K = 0,
289 RxCfgRcv16K = (1 << 11),
290 RxCfgRcv32K = (1 << 12),
291 RxCfgRcv64K = (1 << 11) | (1 << 12),
293 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
294 RxNoWrap = (1 << 7),
295 };
297 /* Twister tuning parameters from RealTek.
298 Completely undocumented, but required to tune bad links on some boards. */
299 /*
300 enum CSCRBits {
301 CSCR_LinkOKBit = 0x0400,
302 CSCR_LinkChangeBit = 0x0800,
303 CSCR_LinkStatusBits = 0x0f000,
304 CSCR_LinkDownOffCmd = 0x003c0,
305 CSCR_LinkDownCmd = 0x0f3c0,
306 */
307 enum CSCRBits {
308 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
309 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
310 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
311 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
312 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
313 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
314 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
315 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
316 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
317 };
319 enum Cfg9346Bits {
320 Cfg9346_Lock = 0x00,
321 Cfg9346_Unlock = 0xC0,
322 };
324 typedef enum {
325 CH_8139 = 0,
326 CH_8139_K,
327 CH_8139A,
328 CH_8139A_G,
329 CH_8139B,
330 CH_8130,
331 CH_8139C,
332 CH_8100,
333 CH_8100B_8139D,
334 CH_8101,
335 } chip_t;
337 enum chip_flags {
338 HasHltClk = (1 << 0),
339 HasLWake = (1 << 1),
340 };
342 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
343 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
344 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
346 #define RTL8139_PCI_REVID_8139 0x10
347 #define RTL8139_PCI_REVID_8139CPLUS 0x20
349 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
351 /* Size is 64 * 16bit words */
352 #define EEPROM_9346_ADDR_BITS 6
353 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
354 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
356 enum Chip9346Operation
357 {
358 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
359 Chip9346_op_read = 0x80, /* 10 AAAAAA */
360 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
361 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
362 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
363 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
364 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
365 };
367 enum Chip9346Mode
368 {
369 Chip9346_none = 0,
370 Chip9346_enter_command_mode,
371 Chip9346_read_command,
372 Chip9346_data_read, /* from output register */
373 Chip9346_data_write, /* to input register, then to contents at specified address */
374 Chip9346_data_write_all, /* to input register, then filling contents */
375 };
377 typedef struct EEprom9346
378 {
379 uint16_t contents[EEPROM_9346_SIZE];
380 int mode;
381 uint32_t tick;
382 uint8_t address;
383 uint16_t input;
384 uint16_t output;
386 uint8_t eecs;
387 uint8_t eesk;
388 uint8_t eedi;
389 uint8_t eedo;
390 } EEprom9346;
392 typedef struct RTL8139TallyCounters
393 {
394 /* Tally counters */
395 uint64_t TxOk;
396 uint64_t RxOk;
397 uint64_t TxERR;
398 uint32_t RxERR;
399 uint16_t MissPkt;
400 uint16_t FAE;
401 uint32_t Tx1Col;
402 uint32_t TxMCol;
403 uint64_t RxOkPhy;
404 uint64_t RxOkBrd;
405 uint32_t RxOkMul;
406 uint16_t TxAbt;
407 uint16_t TxUndrn;
408 } RTL8139TallyCounters;
410 /* Clears all tally counters */
411 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
413 /* Writes tally counters to specified physical memory address */
414 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
416 /* Loads values of tally counters from VM state file */
417 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
419 /* Saves values of tally counters to VM state file */
420 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
422 typedef struct RTL8139State {
423 uint8_t phys[8]; /* mac address */
424 uint8_t mult[8]; /* multicast mask array */
426 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
427 uint32_t TxAddr[4]; /* TxAddr0 */
428 uint32_t RxBuf; /* Receive buffer */
429 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
430 uint32_t RxBufPtr;
431 uint32_t RxBufAddr;
433 uint16_t IntrStatus;
434 uint16_t IntrMask;
436 uint32_t TxConfig;
437 uint32_t RxConfig;
438 uint32_t RxMissed;
440 uint16_t CSCR;
442 uint8_t Cfg9346;
443 uint8_t Config0;
444 uint8_t Config1;
445 uint8_t Config3;
446 uint8_t Config4;
447 uint8_t Config5;
449 uint8_t clock_enabled;
450 uint8_t bChipCmdState;
452 uint16_t MultiIntr;
454 uint16_t BasicModeCtrl;
455 uint16_t BasicModeStatus;
456 uint16_t NWayAdvert;
457 uint16_t NWayLPAR;
458 uint16_t NWayExpansion;
460 uint16_t CpCmd;
461 uint8_t TxThresh;
463 int irq;
464 PCIDevice *pci_dev;
465 VLANClientState *vc;
466 uint8_t macaddr[6];
467 int rtl8139_mmio_io_addr;
469 /* C ring mode */
470 uint32_t currTxDesc;
472 /* C+ mode */
473 uint32_t currCPlusRxDesc;
474 uint32_t currCPlusTxDesc;
476 uint32_t RxRingAddrLO;
477 uint32_t RxRingAddrHI;
479 EEprom9346 eeprom;
481 uint32_t TCTR;
482 uint32_t TimerInt;
483 int64_t TCTR_base;
485 /* Tally counters */
486 RTL8139TallyCounters tally_counters;
488 /* Non-persistent data */
489 uint8_t *cplus_txbuffer;
490 int cplus_txbuffer_len;
491 int cplus_txbuffer_offset;
493 /* PCI interrupt timer */
494 QEMUTimer *timer;
496 } RTL8139State;
498 void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
499 {
500 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
502 switch (command & Chip9346_op_mask)
503 {
504 case Chip9346_op_read:
505 {
506 eeprom->address = command & EEPROM_9346_ADDR_MASK;
507 eeprom->output = eeprom->contents[eeprom->address];
508 eeprom->eedo = 0;
509 eeprom->tick = 0;
510 eeprom->mode = Chip9346_data_read;
511 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
512 eeprom->address, eeprom->output));
513 }
514 break;
516 case Chip9346_op_write:
517 {
518 eeprom->address = command & EEPROM_9346_ADDR_MASK;
519 eeprom->input = 0;
520 eeprom->tick = 0;
521 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
522 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
523 eeprom->address));
524 }
525 break;
526 default:
527 eeprom->mode = Chip9346_none;
528 switch (command & Chip9346_op_ext_mask)
529 {
530 case Chip9346_op_write_enable:
531 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
532 break;
533 case Chip9346_op_write_all:
534 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
535 break;
536 case Chip9346_op_write_disable:
537 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
538 break;
539 }
540 break;
541 }
542 }
544 void prom9346_shift_clock(EEprom9346 *eeprom)
545 {
546 int bit = eeprom->eedi?1:0;
548 ++ eeprom->tick;
550 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
552 switch (eeprom->mode)
553 {
554 case Chip9346_enter_command_mode:
555 if (bit)
556 {
557 eeprom->mode = Chip9346_read_command;
558 eeprom->tick = 0;
559 eeprom->input = 0;
560 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
561 }
562 break;
564 case Chip9346_read_command:
565 eeprom->input = (eeprom->input << 1) | (bit & 1);
566 if (eeprom->tick == 8)
567 {
568 prom9346_decode_command(eeprom, eeprom->input & 0xff);
569 }
570 break;
572 case Chip9346_data_read:
573 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
574 eeprom->output <<= 1;
575 if (eeprom->tick == 16)
576 {
577 #if 1
578 // the FreeBSD drivers (rl and re) don't explicitly toggle
579 // CS between reads (or does setting Cfg9346 to 0 count too?),
580 // so we need to enter wait-for-command state here
581 eeprom->mode = Chip9346_enter_command_mode;
582 eeprom->input = 0;
583 eeprom->tick = 0;
585 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
586 #else
587 // original behaviour
588 ++eeprom->address;
589 eeprom->address &= EEPROM_9346_ADDR_MASK;
590 eeprom->output = eeprom->contents[eeprom->address];
591 eeprom->tick = 0;
593 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
594 eeprom->address, eeprom->output));
595 #endif
596 }
597 break;
599 case Chip9346_data_write:
600 eeprom->input = (eeprom->input << 1) | (bit & 1);
601 if (eeprom->tick == 16)
602 {
603 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
604 eeprom->address, eeprom->input));
606 eeprom->contents[eeprom->address] = eeprom->input;
607 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
608 eeprom->tick = 0;
609 eeprom->input = 0;
610 }
611 break;
613 case Chip9346_data_write_all:
614 eeprom->input = (eeprom->input << 1) | (bit & 1);
615 if (eeprom->tick == 16)
616 {
617 int i;
618 for (i = 0; i < EEPROM_9346_SIZE; i++)
619 {
620 eeprom->contents[i] = eeprom->input;
621 }
622 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
623 eeprom->input));
625 eeprom->mode = Chip9346_enter_command_mode;
626 eeprom->tick = 0;
627 eeprom->input = 0;
628 }
629 break;
631 default:
632 break;
633 }
634 }
636 int prom9346_get_wire(RTL8139State *s)
637 {
638 EEprom9346 *eeprom = &s->eeprom;
639 if (!eeprom->eecs)
640 return 0;
642 return eeprom->eedo;
643 }
645 void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
646 {
647 EEprom9346 *eeprom = &s->eeprom;
648 uint8_t old_eecs = eeprom->eecs;
649 uint8_t old_eesk = eeprom->eesk;
651 eeprom->eecs = eecs;
652 eeprom->eesk = eesk;
653 eeprom->eedi = eedi;
655 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
656 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
658 if (!old_eecs && eecs)
659 {
660 /* Synchronize start */
661 eeprom->tick = 0;
662 eeprom->input = 0;
663 eeprom->output = 0;
664 eeprom->mode = Chip9346_enter_command_mode;
666 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
667 }
669 if (!eecs)
670 {
671 DEBUG_PRINT(("=== eeprom: end access\n"));
672 return;
673 }
675 if (!old_eesk && eesk)
676 {
677 /* SK front rules */
678 prom9346_shift_clock(eeprom);
679 }
680 }
682 static void rtl8139_update_irq(RTL8139State *s)
683 {
684 int isr;
685 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
687 DEBUG_PRINT(("RTL8139: Set IRQ line %d to %d (%04x %04x)\n",
688 s->irq, isr ? 1 : 0, s->IntrStatus, s->IntrMask));
690 if (s->irq == 16) {
691 /* PCI irq */
692 pci_set_irq(s->pci_dev, 0, (isr != 0));
693 } else {
694 /* ISA irq */
695 pic_set_irq(s->irq, (isr != 0));
696 }
697 }
699 #define POLYNOMIAL 0x04c11db6
701 /* From FreeBSD */
702 /* XXX: optimize */
703 static int compute_mcast_idx(const uint8_t *ep)
704 {
705 uint32_t crc;
706 int carry, i, j;
707 uint8_t b;
709 crc = 0xffffffff;
710 for (i = 0; i < 6; i++) {
711 b = *ep++;
712 for (j = 0; j < 8; j++) {
713 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
714 crc <<= 1;
715 b >>= 1;
716 if (carry)
717 crc = ((crc ^ POLYNOMIAL) | carry);
718 }
719 }
720 return (crc >> 26);
721 }
723 static int rtl8139_RxWrap(RTL8139State *s)
724 {
725 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
726 return (s->RxConfig & (1 << 7));
727 }
729 static int rtl8139_receiver_enabled(RTL8139State *s)
730 {
731 return s->bChipCmdState & CmdRxEnb;
732 }
734 static int rtl8139_transmitter_enabled(RTL8139State *s)
735 {
736 return s->bChipCmdState & CmdTxEnb;
737 }
739 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
740 {
741 return s->CpCmd & CPlusRxEnb;
742 }
744 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
745 {
746 return s->CpCmd & CPlusTxEnb;
747 }
749 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
750 {
751 if (s->RxBufAddr + size > s->RxBufferSize)
752 {
753 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
755 /* write packet data */
756 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
757 {
758 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
760 if (size > wrapped)
761 {
762 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
763 buf, size-wrapped );
764 }
766 /* reset buffer pointer */
767 s->RxBufAddr = 0;
769 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
770 buf + (size-wrapped), wrapped );
772 s->RxBufAddr = wrapped;
774 return;
775 }
776 }
778 /* non-wrapping path or overwrapping enabled */
779 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
781 s->RxBufAddr += size;
782 }
784 #define MIN_BUF_SIZE 60
785 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
786 {
787 #if TARGET_PHYS_ADDR_BITS > 32
788 return low | ((target_phys_addr_t)high << 32);
789 #else
790 return low;
791 #endif
792 }
794 static int rtl8139_can_receive(void *opaque)
795 {
796 RTL8139State *s = opaque;
797 int avail;
799 /* Recieve (drop) packets if card is disabled. */
800 if (!s->clock_enabled)
801 return 1;
802 if (!rtl8139_receiver_enabled(s))
803 return 1;
805 if (rtl8139_cp_receiver_enabled(s)) {
806 /* ??? Flow control not implemented in c+ mode.
807 This is a hack to work around slirp deficiencies anyway. */
808 return 1;
809 } else {
810 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
811 s->RxBufferSize);
812 return (avail == 0 || avail >= 1514);
813 }
814 }
816 static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
817 {
818 RTL8139State *s = opaque;
820 uint32_t packet_header = 0;
822 uint8_t buf1[60];
823 static const uint8_t broadcast_macaddr[6] =
824 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
826 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
828 /* test if board clock is stopped */
829 if (!s->clock_enabled)
830 {
831 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
832 return;
833 }
835 /* first check if receiver is enabled */
837 if (!rtl8139_receiver_enabled(s))
838 {
839 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
840 return;
841 }
843 /* XXX: check this */
844 if (s->RxConfig & AcceptAllPhys) {
845 /* promiscuous: receive all */
846 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
848 } else {
849 if (!memcmp(buf, broadcast_macaddr, 6)) {
850 /* broadcast address */
851 if (!(s->RxConfig & AcceptBroadcast))
852 {
853 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
855 /* update tally counter */
856 ++s->tally_counters.RxERR;
858 return;
859 }
861 packet_header |= RxBroadcast;
863 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
865 /* update tally counter */
866 ++s->tally_counters.RxOkBrd;
868 } else if (buf[0] & 0x01) {
869 /* multicast */
870 if (!(s->RxConfig & AcceptMulticast))
871 {
872 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
874 /* update tally counter */
875 ++s->tally_counters.RxERR;
877 return;
878 }
880 int mcast_idx = compute_mcast_idx(buf);
882 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
883 {
884 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
886 /* update tally counter */
887 ++s->tally_counters.RxERR;
889 return;
890 }
892 packet_header |= RxMulticast;
894 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
896 /* update tally counter */
897 ++s->tally_counters.RxOkMul;
899 } else if (s->phys[0] == buf[0] &&
900 s->phys[1] == buf[1] &&
901 s->phys[2] == buf[2] &&
902 s->phys[3] == buf[3] &&
903 s->phys[4] == buf[4] &&
904 s->phys[5] == buf[5]) {
905 /* match */
906 if (!(s->RxConfig & AcceptMyPhys))
907 {
908 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
910 /* update tally counter */
911 ++s->tally_counters.RxERR;
913 return;
914 }
916 packet_header |= RxPhysical;
918 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
920 /* update tally counter */
921 ++s->tally_counters.RxOkPhy;
923 } else {
925 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
927 /* update tally counter */
928 ++s->tally_counters.RxERR;
930 return;
931 }
932 }
934 /* if too small buffer, then expand it */
935 if (size < MIN_BUF_SIZE) {
936 memcpy(buf1, buf, size);
937 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
938 buf = buf1;
939 size = MIN_BUF_SIZE;
940 }
942 if (rtl8139_cp_receiver_enabled(s))
943 {
944 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
946 /* begin C+ receiver mode */
948 /* w0 ownership flag */
949 #define CP_RX_OWN (1<<31)
950 /* w0 end of ring flag */
951 #define CP_RX_EOR (1<<30)
952 /* w0 bits 0...12 : buffer size */
953 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
954 /* w1 tag available flag */
955 #define CP_RX_TAVA (1<<16)
956 /* w1 bits 0...15 : VLAN tag */
957 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
958 /* w2 low 32bit of Rx buffer ptr */
959 /* w3 high 32bit of Rx buffer ptr */
961 int descriptor = s->currCPlusRxDesc;
962 target_phys_addr_t cplus_rx_ring_desc;
964 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
965 cplus_rx_ring_desc += 16 * descriptor;
967 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
968 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
970 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
972 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
973 rxdw0 = le32_to_cpu(val);
974 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
975 rxdw1 = le32_to_cpu(val);
976 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
977 rxbufLO = le32_to_cpu(val);
978 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
979 rxbufHI = le32_to_cpu(val);
981 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
982 descriptor,
983 rxdw0, rxdw1, rxbufLO, rxbufHI));
985 if (!(rxdw0 & CP_RX_OWN))
986 {
987 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
989 s->IntrStatus |= RxOverflow;
990 ++s->RxMissed;
992 /* update tally counter */
993 ++s->tally_counters.RxERR;
994 ++s->tally_counters.MissPkt;
996 rtl8139_update_irq(s);
997 return;
998 }
1000 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1002 /* TODO: scatter the packet over available receive ring descriptors space */
1004 if (size+4 > rx_space)
1006 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1007 descriptor, rx_space, size));
1009 s->IntrStatus |= RxOverflow;
1010 ++s->RxMissed;
1012 /* update tally counter */
1013 ++s->tally_counters.RxERR;
1014 ++s->tally_counters.MissPkt;
1016 rtl8139_update_irq(s);
1017 return;
1020 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1022 /* receive/copy to target memory */
1023 cpu_physical_memory_write( rx_addr, buf, size );
1025 if (s->CpCmd & CPlusRxChkSum)
1027 /* do some packet checksumming */
1030 /* write checksum */
1031 #if defined (RTL8139_CALCULATE_RXCRC)
1032 val = cpu_to_le32(crc32(0, buf, size));
1033 #else
1034 val = 0;
1035 #endif
1036 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1038 /* first segment of received packet flag */
1039 #define CP_RX_STATUS_FS (1<<29)
1040 /* last segment of received packet flag */
1041 #define CP_RX_STATUS_LS (1<<28)
1042 /* multicast packet flag */
1043 #define CP_RX_STATUS_MAR (1<<26)
1044 /* physical-matching packet flag */
1045 #define CP_RX_STATUS_PAM (1<<25)
1046 /* broadcast packet flag */
1047 #define CP_RX_STATUS_BAR (1<<24)
1048 /* runt packet flag */
1049 #define CP_RX_STATUS_RUNT (1<<19)
1050 /* crc error flag */
1051 #define CP_RX_STATUS_CRC (1<<18)
1052 /* IP checksum error flag */
1053 #define CP_RX_STATUS_IPF (1<<15)
1054 /* UDP checksum error flag */
1055 #define CP_RX_STATUS_UDPF (1<<14)
1056 /* TCP checksum error flag */
1057 #define CP_RX_STATUS_TCPF (1<<13)
1059 /* transfer ownership to target */
1060 rxdw0 &= ~CP_RX_OWN;
1062 /* set first segment bit */
1063 rxdw0 |= CP_RX_STATUS_FS;
1065 /* set last segment bit */
1066 rxdw0 |= CP_RX_STATUS_LS;
1068 /* set received packet type flags */
1069 if (packet_header & RxBroadcast)
1070 rxdw0 |= CP_RX_STATUS_BAR;
1071 if (packet_header & RxMulticast)
1072 rxdw0 |= CP_RX_STATUS_MAR;
1073 if (packet_header & RxPhysical)
1074 rxdw0 |= CP_RX_STATUS_PAM;
1076 /* set received size */
1077 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1078 rxdw0 |= (size+4);
1080 /* reset VLAN tag flag */
1081 rxdw1 &= ~CP_RX_TAVA;
1083 /* update ring data */
1084 val = cpu_to_le32(rxdw0);
1085 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1086 val = cpu_to_le32(rxdw1);
1087 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1089 /* update tally counter */
1090 ++s->tally_counters.RxOk;
1092 /* seek to next Rx descriptor */
1093 if (rxdw0 & CP_RX_EOR)
1095 s->currCPlusRxDesc = 0;
1097 else
1099 ++s->currCPlusRxDesc;
1102 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1105 else
1107 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1109 /* begin ring receiver mode */
1110 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1112 /* if receiver buffer is empty then avail == 0 */
1114 if (avail != 0 && size + 8 >= avail)
1116 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1117 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1119 s->IntrStatus |= RxOverflow;
1120 ++s->RxMissed;
1121 rtl8139_update_irq(s);
1122 return;
1125 packet_header |= RxStatusOK;
1127 packet_header |= (((size+4) << 16) & 0xffff0000);
1129 /* write header */
1130 uint32_t val = cpu_to_le32(packet_header);
1132 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1134 rtl8139_write_buffer(s, buf, size);
1136 /* write checksum */
1137 #if defined (RTL8139_CALCULATE_RXCRC)
1138 val = cpu_to_le32(crc32(0, buf, size));
1139 #else
1140 val = 0;
1141 #endif
1143 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1145 /* correct buffer write pointer */
1146 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1148 /* now we can signal we have received something */
1150 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1151 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1154 s->IntrStatus |= RxOK;
1156 if (do_interrupt)
1158 rtl8139_update_irq(s);
1162 static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1164 rtl8139_do_receive(opaque, buf, size, 1);
1167 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1169 s->RxBufferSize = bufferSize;
1170 s->RxBufPtr = 0;
1171 s->RxBufAddr = 0;
1174 static void rtl8139_reset(RTL8139State *s)
1176 int i;
1178 /* restore MAC address */
1179 memcpy(s->phys, s->macaddr, 6);
1181 /* reset interrupt mask */
1182 s->IntrStatus = 0;
1183 s->IntrMask = 0;
1185 rtl8139_update_irq(s);
1187 /* prepare eeprom */
1188 s->eeprom.contents[0] = 0x8129;
1189 #if 1
1190 // PCI vendor and device ID should be mirrored here
1191 s->eeprom.contents[1] = 0x10ec;
1192 s->eeprom.contents[2] = 0x8139;
1193 #endif
1194 memcpy(&s->eeprom.contents[7], s->macaddr, 6);
1196 /* mark all status registers as owned by host */
1197 for (i = 0; i < 4; ++i)
1199 s->TxStatus[i] = TxHostOwns;
1202 s->currTxDesc = 0;
1203 s->currCPlusRxDesc = 0;
1204 s->currCPlusTxDesc = 0;
1206 s->RxRingAddrLO = 0;
1207 s->RxRingAddrHI = 0;
1209 s->RxBuf = 0;
1211 rtl8139_reset_rxring(s, 8192);
1213 /* ACK the reset */
1214 s->TxConfig = 0;
1216 #if 0
1217 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1218 s->clock_enabled = 0;
1219 #else
1220 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1221 s->clock_enabled = 1;
1222 #endif
1224 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1226 /* set initial state data */
1227 s->Config0 = 0x0; /* No boot ROM */
1228 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1229 s->Config3 = 0x1; /* fast back-to-back compatible */
1230 s->Config5 = 0x0;
1232 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1234 s->CpCmd = 0x0; /* reset C+ mode */
1236 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1237 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1238 s->BasicModeCtrl = 0x1000; // autonegotiation
1240 s->BasicModeStatus = 0x7809;
1241 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1242 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1243 s->BasicModeStatus |= 0x0004; /* link is up */
1245 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1246 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1247 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1249 /* also reset timer and disable timer interrupt */
1250 s->TCTR = 0;
1251 s->TimerInt = 0;
1252 s->TCTR_base = 0;
1254 /* reset tally counters */
1255 RTL8139TallyCounters_clear(&s->tally_counters);
1258 void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1260 counters->TxOk = 0;
1261 counters->RxOk = 0;
1262 counters->TxERR = 0;
1263 counters->RxERR = 0;
1264 counters->MissPkt = 0;
1265 counters->FAE = 0;
1266 counters->Tx1Col = 0;
1267 counters->TxMCol = 0;
1268 counters->RxOkPhy = 0;
1269 counters->RxOkBrd = 0;
1270 counters->RxOkMul = 0;
1271 counters->TxAbt = 0;
1272 counters->TxUndrn = 0;
1275 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1277 uint16_t val16;
1278 uint32_t val32;
1279 uint64_t val64;
1281 val64 = cpu_to_le64(tally_counters->TxOk);
1282 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1284 val64 = cpu_to_le64(tally_counters->RxOk);
1285 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1287 val64 = cpu_to_le64(tally_counters->TxERR);
1288 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1290 val32 = cpu_to_le32(tally_counters->RxERR);
1291 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1293 val16 = cpu_to_le16(tally_counters->MissPkt);
1294 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1296 val16 = cpu_to_le16(tally_counters->FAE);
1297 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1299 val32 = cpu_to_le32(tally_counters->Tx1Col);
1300 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1302 val32 = cpu_to_le32(tally_counters->TxMCol);
1303 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1305 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1306 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1308 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1309 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1311 val32 = cpu_to_le32(tally_counters->RxOkMul);
1312 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1314 val16 = cpu_to_le16(tally_counters->TxAbt);
1315 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1317 val16 = cpu_to_le16(tally_counters->TxUndrn);
1318 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1321 /* Loads values of tally counters from VM state file */
1322 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1324 qemu_get_be64s(f, &tally_counters->TxOk);
1325 qemu_get_be64s(f, &tally_counters->RxOk);
1326 qemu_get_be64s(f, &tally_counters->TxERR);
1327 qemu_get_be32s(f, &tally_counters->RxERR);
1328 qemu_get_be16s(f, &tally_counters->MissPkt);
1329 qemu_get_be16s(f, &tally_counters->FAE);
1330 qemu_get_be32s(f, &tally_counters->Tx1Col);
1331 qemu_get_be32s(f, &tally_counters->TxMCol);
1332 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1333 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1334 qemu_get_be32s(f, &tally_counters->RxOkMul);
1335 qemu_get_be16s(f, &tally_counters->TxAbt);
1336 qemu_get_be16s(f, &tally_counters->TxUndrn);
1339 /* Saves values of tally counters to VM state file */
1340 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1342 qemu_put_be64s(f, &tally_counters->TxOk);
1343 qemu_put_be64s(f, &tally_counters->RxOk);
1344 qemu_put_be64s(f, &tally_counters->TxERR);
1345 qemu_put_be32s(f, &tally_counters->RxERR);
1346 qemu_put_be16s(f, &tally_counters->MissPkt);
1347 qemu_put_be16s(f, &tally_counters->FAE);
1348 qemu_put_be32s(f, &tally_counters->Tx1Col);
1349 qemu_put_be32s(f, &tally_counters->TxMCol);
1350 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1351 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1352 qemu_put_be32s(f, &tally_counters->RxOkMul);
1353 qemu_put_be16s(f, &tally_counters->TxAbt);
1354 qemu_put_be16s(f, &tally_counters->TxUndrn);
1357 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1359 val &= 0xff;
1361 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1363 if (val & CmdReset)
1365 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1366 rtl8139_reset(s);
1368 if (val & CmdRxEnb)
1370 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1372 s->currCPlusRxDesc = 0;
1374 if (val & CmdTxEnb)
1376 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1378 s->currCPlusTxDesc = 0;
1381 /* mask unwriteable bits */
1382 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1384 /* Deassert reset pin before next read */
1385 val &= ~CmdReset;
1387 s->bChipCmdState = val;
1390 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1392 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1394 if (unread != 0)
1396 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1397 return 0;
1400 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1402 return 1;
1405 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1407 uint32_t ret = s->bChipCmdState;
1409 if (rtl8139_RxBufferEmpty(s))
1410 ret |= RxBufEmpty;
1412 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1414 return ret;
1417 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1419 int i;
1421 val &= 0xffff;
1423 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1425 /* mask unwriteable bits */
1426 val = SET_MASKED(val, 0xff84, s->CpCmd);
1428 if ( (s->CpCmd & CPlusTxEnb) &&
1429 !(val & CPlusTxEnb) )
1431 /* Reset TX status when the transmitter drops from C+ to
1432 non-C+ mode. Windows has a habit of turning off C+ and
1433 then waiting for the TX requests to clear as part of shut
1434 down, and you get stuck forever if there are old DTCRs in
1435 the registers. */
1436 for (i = 0; i < 4; i++)
1438 s->TxStatus[i] = TxHostOwns;
1442 s->CpCmd = val;
1445 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1447 uint32_t ret = s->CpCmd;
1449 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1451 return ret;
1454 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1456 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1459 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1461 uint32_t ret = 0;
1463 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1465 return ret;
1468 int rtl8139_config_writeable(RTL8139State *s)
1470 if (s->Cfg9346 & Cfg9346_Unlock)
1472 return 1;
1475 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1477 return 0;
1480 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1482 val &= 0xffff;
1484 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1486 /* mask unwriteable bits */
1487 uint32_t mask = 0x4cff;
1489 if (1 || !rtl8139_config_writeable(s))
1491 /* Speed setting and autonegotiation enable bits are read-only */
1492 mask |= 0x3000;
1493 /* Duplex mode setting is read-only */
1494 mask |= 0x0100;
1497 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1499 s->BasicModeCtrl = val;
1502 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1504 uint32_t ret = s->BasicModeCtrl;
1506 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1508 return ret;
1511 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1513 val &= 0xffff;
1515 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1517 /* mask unwriteable bits */
1518 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1520 s->BasicModeStatus = val;
1523 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1525 uint32_t ret = s->BasicModeStatus;
1527 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1529 return ret;
1532 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1534 val &= 0xff;
1536 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1538 /* mask unwriteable bits */
1539 val = SET_MASKED(val, 0x31, s->Cfg9346);
1541 uint32_t opmode = val & 0xc0;
1542 uint32_t eeprom_val = val & 0xf;
1544 if (opmode == 0x80) {
1545 /* eeprom access */
1546 int eecs = (eeprom_val & 0x08)?1:0;
1547 int eesk = (eeprom_val & 0x04)?1:0;
1548 int eedi = (eeprom_val & 0x02)?1:0;
1549 prom9346_set_wire(s, eecs, eesk, eedi);
1550 } else if (opmode == 0x40) {
1551 /* Reset. */
1552 val = 0;
1553 rtl8139_reset(s);
1556 s->Cfg9346 = val;
1559 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1561 uint32_t ret = s->Cfg9346;
1563 uint32_t opmode = ret & 0xc0;
1565 if (opmode == 0x80)
1567 /* eeprom access */
1568 int eedo = prom9346_get_wire(s);
1569 if (eedo)
1571 ret |= 0x01;
1573 else
1575 ret &= ~0x01;
1579 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1581 return ret;
1584 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1586 val &= 0xff;
1588 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1590 if (!rtl8139_config_writeable(s))
1591 return;
1593 /* mask unwriteable bits */
1594 val = SET_MASKED(val, 0xf8, s->Config0);
1596 s->Config0 = val;
1599 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1601 uint32_t ret = s->Config0;
1603 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1605 return ret;
1608 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1610 val &= 0xff;
1612 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1614 if (!rtl8139_config_writeable(s))
1615 return;
1617 /* mask unwriteable bits */
1618 val = SET_MASKED(val, 0xC, s->Config1);
1620 s->Config1 = val;
1623 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1625 uint32_t ret = s->Config1;
1627 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1629 return ret;
1632 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1634 val &= 0xff;
1636 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1638 if (!rtl8139_config_writeable(s))
1639 return;
1641 /* mask unwriteable bits */
1642 val = SET_MASKED(val, 0x8F, s->Config3);
1644 s->Config3 = val;
1647 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1649 uint32_t ret = s->Config3;
1651 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1653 return ret;
1656 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1658 val &= 0xff;
1660 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1662 if (!rtl8139_config_writeable(s))
1663 return;
1665 /* mask unwriteable bits */
1666 val = SET_MASKED(val, 0x0a, s->Config4);
1668 s->Config4 = val;
1671 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1673 uint32_t ret = s->Config4;
1675 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1677 return ret;
1680 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1682 val &= 0xff;
1684 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1686 /* mask unwriteable bits */
1687 val = SET_MASKED(val, 0x80, s->Config5);
1689 s->Config5 = val;
1692 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1694 uint32_t ret = s->Config5;
1696 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1698 return ret;
1701 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1703 if (!rtl8139_transmitter_enabled(s))
1705 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1706 return;
1709 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1711 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1713 s->TxConfig = val;
1716 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1718 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1720 uint32_t tc = s->TxConfig;
1721 tc &= 0xFFFFFF00;
1722 tc |= (val & 0x000000FF);
1723 rtl8139_TxConfig_write(s, tc);
1726 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1728 uint32_t ret = s->TxConfig;
1730 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1732 return ret;
1735 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1737 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1739 /* mask unwriteable bits */
1740 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1742 s->RxConfig = val;
1744 /* reset buffer size and read/write pointers */
1745 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1747 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1750 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1752 uint32_t ret = s->RxConfig;
1754 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1756 return ret;
1759 static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1761 if (!size)
1763 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1764 return;
1767 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1769 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1770 rtl8139_do_receive(s, buf, size, do_interrupt);
1772 else
1774 qemu_send_packet(s->vc, buf, size);
1778 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1780 if (!rtl8139_transmitter_enabled(s))
1782 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1783 descriptor));
1784 s->TxStatus[descriptor] = TxAborted | TxHostOwns;
1785 return 0;
1788 if (s->TxStatus[descriptor] & TxHostOwns)
1790 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1791 descriptor, s->TxStatus[descriptor]));
1792 s->TxStatus[descriptor] = TxAborted | TxHostOwns;
1793 return 0;
1796 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1798 int txsize = s->TxStatus[descriptor] & 0x1fff;
1799 uint8_t txbuffer[0x2000];
1801 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1802 txsize, s->TxAddr[descriptor]));
1804 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1806 /* Mark descriptor as transferred */
1807 s->TxStatus[descriptor] |= TxHostOwns;
1808 s->TxStatus[descriptor] |= TxStatOK;
1810 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1812 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1814 /* update interrupt */
1815 s->IntrStatus |= TxOK;
1816 rtl8139_update_irq(s);
1818 return 1;
1821 /* structures and macros for task offloading */
1822 typedef struct ip_header
1824 uint8_t ip_ver_len; /* version and header length */
1825 uint8_t ip_tos; /* type of service */
1826 uint16_t ip_len; /* total length */
1827 uint16_t ip_id; /* identification */
1828 uint16_t ip_off; /* fragment offset field */
1829 uint8_t ip_ttl; /* time to live */
1830 uint8_t ip_p; /* protocol */
1831 uint16_t ip_sum; /* checksum */
1832 uint32_t ip_src,ip_dst; /* source and dest address */
1833 } ip_header;
1835 #define IP_HEADER_VERSION_4 4
1836 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1837 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1839 typedef struct tcp_header
1841 uint16_t th_sport; /* source port */
1842 uint16_t th_dport; /* destination port */
1843 uint32_t th_seq; /* sequence number */
1844 uint32_t th_ack; /* acknowledgement number */
1845 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1846 uint16_t th_win; /* window */
1847 uint16_t th_sum; /* checksum */
1848 uint16_t th_urp; /* urgent pointer */
1849 } tcp_header;
1851 typedef struct udp_header
1853 uint16_t uh_sport; /* source port */
1854 uint16_t uh_dport; /* destination port */
1855 uint16_t uh_ulen; /* udp length */
1856 uint16_t uh_sum; /* udp checksum */
1857 } udp_header;
1859 typedef struct ip_pseudo_header
1861 uint32_t ip_src;
1862 uint32_t ip_dst;
1863 uint8_t zeros;
1864 uint8_t ip_proto;
1865 uint16_t ip_payload;
1866 } ip_pseudo_header;
1868 #define IP_PROTO_TCP 6
1869 #define IP_PROTO_UDP 17
1871 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1872 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1873 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1875 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1877 #define TCP_FLAG_FIN 0x01
1878 #define TCP_FLAG_PUSH 0x08
1880 /* produces ones' complement sum of data */
1881 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1883 uint32_t result = 0;
1885 for (; len > 1; data+=2, len-=2)
1887 result += *(uint16_t*)data;
1890 /* add the remainder byte */
1891 if (len)
1893 uint8_t odd[2] = {*data, 0};
1894 result += *(uint16_t*)odd;
1897 while (result>>16)
1898 result = (result & 0xffff) + (result >> 16);
1900 return result;
1903 static uint16_t ip_checksum(void *data, size_t len)
1905 return ~ones_complement_sum((uint8_t*)data, len);
1908 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1910 if (!rtl8139_transmitter_enabled(s))
1912 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1913 return 0;
1916 if (!rtl8139_cp_transmitter_enabled(s))
1918 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1919 return 0 ;
1922 int descriptor = s->currCPlusTxDesc;
1924 target_phys_addr_t cplus_tx_ring_desc =
1925 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1927 /* Normal priority ring */
1928 cplus_tx_ring_desc += 16 * descriptor;
1930 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1931 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1933 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1935 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1936 txdw0 = le32_to_cpu(val);
1937 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1938 txdw1 = le32_to_cpu(val);
1939 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1940 txbufLO = le32_to_cpu(val);
1941 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1942 txbufHI = le32_to_cpu(val);
1944 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1945 descriptor,
1946 txdw0, txdw1, txbufLO, txbufHI));
1948 /* w0 ownership flag */
1949 #define CP_TX_OWN (1<<31)
1950 /* w0 end of ring flag */
1951 #define CP_TX_EOR (1<<30)
1952 /* first segment of received packet flag */
1953 #define CP_TX_FS (1<<29)
1954 /* last segment of received packet flag */
1955 #define CP_TX_LS (1<<28)
1956 /* large send packet flag */
1957 #define CP_TX_LGSEN (1<<27)
1958 /* large send MSS mask, bits 16...25 */
1959 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1961 /* IP checksum offload flag */
1962 #define CP_TX_IPCS (1<<18)
1963 /* UDP checksum offload flag */
1964 #define CP_TX_UDPCS (1<<17)
1965 /* TCP checksum offload flag */
1966 #define CP_TX_TCPCS (1<<16)
1968 /* w0 bits 0...15 : buffer size */
1969 #define CP_TX_BUFFER_SIZE (1<<16)
1970 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1971 /* w1 tag available flag */
1972 #define CP_RX_TAGC (1<<17)
1973 /* w1 bits 0...15 : VLAN tag */
1974 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1975 /* w2 low 32bit of Rx buffer ptr */
1976 /* w3 high 32bit of Rx buffer ptr */
1978 /* set after transmission */
1979 /* FIFO underrun flag */
1980 #define CP_TX_STATUS_UNF (1<<25)
1981 /* transmit error summary flag, valid if set any of three below */
1982 #define CP_TX_STATUS_TES (1<<23)
1983 /* out-of-window collision flag */
1984 #define CP_TX_STATUS_OWC (1<<22)
1985 /* link failure flag */
1986 #define CP_TX_STATUS_LNKF (1<<21)
1987 /* excessive collisions flag */
1988 #define CP_TX_STATUS_EXC (1<<20)
1990 if (!(txdw0 & CP_TX_OWN))
1992 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1993 return 0 ;
1996 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1998 if (txdw0 & CP_TX_FS)
2000 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
2002 /* reset internal buffer offset */
2003 s->cplus_txbuffer_offset = 0;
2006 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2007 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2009 /* make sure we have enough space to assemble the packet */
2010 if (!s->cplus_txbuffer)
2012 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2013 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
2014 s->cplus_txbuffer_offset = 0;
2016 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
2019 if (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2021 free(s->cplus_txbuffer);
2022 s->cplus_txbuffer = NULL;
2024 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space exceeded: %d\n", s->cplus_txbuffer_offset + txsize));
2027 if (!s->cplus_txbuffer)
2029 /* out of memory */
2031 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2033 /* update tally counter */
2034 ++s->tally_counters.TxERR;
2035 ++s->tally_counters.TxAbt;
2037 return 0;
2040 /* append more data to the packet */
2042 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2043 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2045 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2046 s->cplus_txbuffer_offset += txsize;
2048 /* seek to next Rx descriptor */
2049 if (txdw0 & CP_TX_EOR)
2051 s->currCPlusTxDesc = 0;
2053 else
2055 ++s->currCPlusTxDesc;
2056 if (s->currCPlusTxDesc >= 64)
2057 s->currCPlusTxDesc = 0;
2060 /* transfer ownership to target */
2061 txdw0 &= ~CP_RX_OWN;
2063 /* reset error indicator bits */
2064 txdw0 &= ~CP_TX_STATUS_UNF;
2065 txdw0 &= ~CP_TX_STATUS_TES;
2066 txdw0 &= ~CP_TX_STATUS_OWC;
2067 txdw0 &= ~CP_TX_STATUS_LNKF;
2068 txdw0 &= ~CP_TX_STATUS_EXC;
2070 /* update ring data */
2071 val = cpu_to_le32(txdw0);
2072 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2073 // val = cpu_to_le32(txdw1);
2074 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2076 /* Now decide if descriptor being processed is holding the last segment of packet */
2077 if (txdw0 & CP_TX_LS)
2079 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2081 /* can transfer fully assembled packet */
2083 uint8_t *saved_buffer = s->cplus_txbuffer;
2084 int saved_size = s->cplus_txbuffer_offset;
2085 int saved_buffer_len = s->cplus_txbuffer_len;
2087 /* reset the card space to protect from recursive call */
2088 s->cplus_txbuffer = NULL;
2089 s->cplus_txbuffer_offset = 0;
2090 s->cplus_txbuffer_len = 0;
2092 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2094 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2096 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2097 #define ETH_HLEN 14
2098 #define ETH_MTU 1500
2100 /* ip packet header */
2101 ip_header *ip = 0;
2102 int hlen = 0;
2103 uint8_t ip_protocol = 0;
2104 uint16_t ip_data_len = 0;
2106 uint8_t *eth_payload_data = 0;
2107 size_t eth_payload_len = 0;
2109 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2110 if (proto == ETH_P_IP)
2112 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2114 /* not aligned */
2115 eth_payload_data = saved_buffer + ETH_HLEN;
2116 eth_payload_len = saved_size - ETH_HLEN;
2118 ip = (ip_header*)eth_payload_data;
2120 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2121 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2122 ip = NULL;
2123 } else {
2124 hlen = IP_HEADER_LENGTH(ip);
2125 ip_protocol = ip->ip_p;
2126 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2130 if (ip)
2132 if (txdw0 & CP_TX_IPCS)
2134 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2136 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2137 /* bad packet header len */
2138 /* or packet too short */
2140 else
2142 ip->ip_sum = 0;
2143 ip->ip_sum = ip_checksum(ip, hlen);
2144 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2148 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2150 #if defined (DEBUG_RTL8139)
2151 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2152 #endif
2153 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2154 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2156 int tcp_send_offset = 0;
2157 int send_count = 0;
2159 /* maximum IP header length is 60 bytes */
2160 uint8_t saved_ip_header[60];
2162 /* save IP header template; data area is used in tcp checksum calculation */
2163 memcpy(saved_ip_header, eth_payload_data, hlen);
2165 /* a placeholder for checksum calculation routine in tcp case */
2166 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2167 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2169 /* pointer to TCP header */
2170 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2172 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2174 /* ETH_MTU = ip header len + tcp header len + payload */
2175 int tcp_data_len = ip_data_len - tcp_hlen;
2176 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2178 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2179 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2181 /* note the cycle below overwrites IP header data,
2182 but restores it from saved_ip_header before sending packet */
2184 int is_last_frame = 0;
2186 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2188 uint16_t chunk_size = tcp_chunk_size;
2190 /* check if this is the last frame */
2191 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2193 is_last_frame = 1;
2194 chunk_size = tcp_data_len - tcp_send_offset;
2197 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2199 /* add 4 TCP pseudoheader fields */
2200 /* copy IP source and destination fields */
2201 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2203 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2205 if (tcp_send_offset)
2207 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2210 /* keep PUSH and FIN flags only for the last frame */
2211 if (!is_last_frame)
2213 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2216 /* recalculate TCP checksum */
2217 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2218 p_tcpip_hdr->zeros = 0;
2219 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2220 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2222 p_tcp_hdr->th_sum = 0;
2224 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2225 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2227 p_tcp_hdr->th_sum = tcp_checksum;
2229 /* restore IP header */
2230 memcpy(eth_payload_data, saved_ip_header, hlen);
2232 /* set IP data length and recalculate IP checksum */
2233 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2235 /* increment IP id for subsequent frames */
2236 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2238 ip->ip_sum = 0;
2239 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2240 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2242 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2243 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2244 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2246 /* add transferred count to TCP sequence number */
2247 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2248 ++send_count;
2251 /* Stop sending this frame */
2252 saved_size = 0;
2254 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2256 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2258 /* maximum IP header length is 60 bytes */
2259 uint8_t saved_ip_header[60];
2260 memcpy(saved_ip_header, eth_payload_data, hlen);
2262 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2263 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2265 /* add 4 TCP pseudoheader fields */
2266 /* copy IP source and destination fields */
2267 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2269 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2271 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2273 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2274 p_tcpip_hdr->zeros = 0;
2275 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2276 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2278 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2280 p_tcp_hdr->th_sum = 0;
2282 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2283 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2285 p_tcp_hdr->th_sum = tcp_checksum;
2287 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2289 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2291 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2292 p_udpip_hdr->zeros = 0;
2293 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2294 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2296 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2298 p_udp_hdr->uh_sum = 0;
2300 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2301 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2303 p_udp_hdr->uh_sum = udp_checksum;
2306 /* restore IP header */
2307 memcpy(eth_payload_data, saved_ip_header, hlen);
2312 /* update tally counter */
2313 ++s->tally_counters.TxOk;
2315 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2317 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2319 /* restore card space if there was no recursion and reset offset */
2320 if (!s->cplus_txbuffer)
2322 s->cplus_txbuffer = saved_buffer;
2323 s->cplus_txbuffer_len = saved_buffer_len;
2324 s->cplus_txbuffer_offset = 0;
2326 else
2328 free(saved_buffer);
2331 else
2333 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2336 return 1;
2339 static void rtl8139_cplus_transmit(RTL8139State *s)
2341 int txcount = 0;
2343 while (rtl8139_cplus_transmit_one(s))
2345 ++txcount;
2348 /* Mark transfer completed */
2349 if (!txcount)
2351 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2352 s->currCPlusTxDesc));
2354 else
2356 /* update interrupt status */
2357 s->IntrStatus |= TxOK;
2358 rtl8139_update_irq(s);
2362 static void rtl8139_transmit(RTL8139State *s)
2364 int descriptor = s->currTxDesc, txcount = 0;
2366 /*while*/
2367 if (rtl8139_transmit_one(s, descriptor))
2369 ++s->currTxDesc;
2370 s->currTxDesc %= 4;
2371 ++txcount;
2374 /* Mark transfer completed */
2375 if (!txcount)
2377 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2381 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2384 int descriptor = txRegOffset/4;
2386 /* handle C+ transmit mode register configuration */
2388 if (rtl8139_cp_transmitter_enabled(s))
2390 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2392 /* handle Dump Tally Counters command */
2393 s->TxStatus[descriptor] = val;
2395 if (descriptor == 0 && (val & 0x8))
2397 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2399 /* dump tally counters to specified memory location */
2400 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2402 /* mark dump completed */
2403 s->TxStatus[0] &= ~0x8;
2406 return;
2409 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2411 /* mask only reserved bits */
2412 val &= ~0xff00c000; /* these bits are reset on write */
2413 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2415 s->TxStatus[descriptor] = val;
2417 /* attempt to start transmission */
2418 rtl8139_transmit(s);
2421 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2423 uint32_t ret = s->TxStatus[txRegOffset/4];
2425 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2427 return ret;
2430 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2432 uint16_t ret = 0;
2434 /* Simulate TSAD, it is read only anyway */
2436 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2437 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2438 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2439 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2441 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2442 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2443 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2444 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2446 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2447 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2448 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2449 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2451 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2452 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2453 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2454 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2457 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2459 return ret;
2462 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2464 uint16_t ret = s->CSCR;
2466 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2468 return ret;
2471 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2473 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2475 s->TxAddr[txAddrOffset/4] = le32_to_cpu(val);
2478 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2480 uint32_t ret = cpu_to_le32(s->TxAddr[txAddrOffset/4]);
2482 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2484 return ret;
2487 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2489 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2491 /* this value is off by 16 */
2492 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2494 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2495 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2498 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2500 /* this value is off by 16 */
2501 uint32_t ret = s->RxBufPtr - 0x10;
2503 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2505 return ret;
2508 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2510 /* this value is NOT off by 16 */
2511 uint32_t ret = s->RxBufAddr;
2513 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2515 return ret;
2518 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2520 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2522 s->RxBuf = val;
2524 /* may need to reset rxring here */
2527 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2529 uint32_t ret = s->RxBuf;
2531 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2533 return ret;
2536 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2538 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2540 /* mask unwriteable bits */
2541 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2543 s->IntrMask = val;
2545 rtl8139_update_irq(s);
2548 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2550 uint32_t ret = s->IntrMask;
2552 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2554 return ret;
2557 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2559 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2561 #if 0
2563 /* writing to ISR has no effect */
2565 return;
2567 #else
2568 uint16_t newStatus = s->IntrStatus & ~val;
2570 /* mask unwriteable bits */
2571 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2573 /* writing 1 to interrupt status register bit clears it */
2574 s->IntrStatus = 0;
2575 rtl8139_update_irq(s);
2577 s->IntrStatus = newStatus;
2578 rtl8139_update_irq(s);
2579 #endif
2582 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2584 uint32_t ret = s->IntrStatus;
2586 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2588 #if 0
2590 /* reading ISR clears all interrupts */
2591 s->IntrStatus = 0;
2593 rtl8139_update_irq(s);
2595 #endif
2597 return ret;
2600 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2602 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2604 /* mask unwriteable bits */
2605 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2607 s->MultiIntr = val;
2610 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2612 uint32_t ret = s->MultiIntr;
2614 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2616 return ret;
2619 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2621 RTL8139State *s = opaque;
2623 addr &= 0xff;
2625 switch (addr)
2627 case MAC0 ... MAC0+5:
2628 s->phys[addr - MAC0] = val;
2629 break;
2630 case MAC0+6 ... MAC0+7:
2631 /* reserved */
2632 break;
2633 case MAR0 ... MAR0+7:
2634 s->mult[addr - MAR0] = val;
2635 break;
2636 case ChipCmd:
2637 rtl8139_ChipCmd_write(s, val);
2638 break;
2639 case Cfg9346:
2640 rtl8139_Cfg9346_write(s, val);
2641 break;
2642 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2643 rtl8139_TxConfig_writeb(s, val);
2644 break;
2645 case Config0:
2646 rtl8139_Config0_write(s, val);
2647 break;
2648 case Config1:
2649 rtl8139_Config1_write(s, val);
2650 break;
2651 case Config3:
2652 rtl8139_Config3_write(s, val);
2653 break;
2654 case Config4:
2655 rtl8139_Config4_write(s, val);
2656 break;
2657 case Config5:
2658 rtl8139_Config5_write(s, val);
2659 break;
2660 case MediaStatus:
2661 /* ignore */
2662 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2663 break;
2665 case HltClk:
2666 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2667 if (val == 'R')
2669 s->clock_enabled = 1;
2671 else if (val == 'H')
2673 s->clock_enabled = 0;
2675 break;
2677 case TxThresh:
2678 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2679 s->TxThresh = val;
2680 break;
2682 case TxPoll:
2683 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2684 if (val & (1 << 7))
2686 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2687 //rtl8139_cplus_transmit(s);
2689 if (val & (1 << 6))
2691 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2692 rtl8139_cplus_transmit(s);
2695 break;
2697 default:
2698 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2699 break;
2703 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2705 RTL8139State *s = opaque;
2707 addr &= 0xfe;
2709 switch (addr)
2711 case IntrMask:
2712 rtl8139_IntrMask_write(s, val);
2713 break;
2715 case IntrStatus:
2716 rtl8139_IntrStatus_write(s, val);
2717 break;
2719 case MultiIntr:
2720 rtl8139_MultiIntr_write(s, val);
2721 break;
2723 case RxBufPtr:
2724 rtl8139_RxBufPtr_write(s, val);
2725 break;
2727 case BasicModeCtrl:
2728 rtl8139_BasicModeCtrl_write(s, val);
2729 break;
2730 case BasicModeStatus:
2731 rtl8139_BasicModeStatus_write(s, val);
2732 break;
2733 case NWayAdvert:
2734 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2735 s->NWayAdvert = val;
2736 break;
2737 case NWayLPAR:
2738 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2739 break;
2740 case NWayExpansion:
2741 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2742 s->NWayExpansion = val;
2743 break;
2745 case CpCmd:
2746 rtl8139_CpCmd_write(s, val);
2747 break;
2749 case IntrMitigate:
2750 rtl8139_IntrMitigate_write(s, val);
2751 break;
2753 default:
2754 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2756 #ifdef TARGET_WORDS_BIGENDIAN
2757 rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff);
2758 rtl8139_io_writeb(opaque, addr + 1, val & 0xff);
2759 #else
2760 rtl8139_io_writeb(opaque, addr, val & 0xff);
2761 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2762 #endif
2763 break;
2767 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2769 RTL8139State *s = opaque;
2771 addr &= 0xfc;
2773 switch (addr)
2775 case RxMissed:
2776 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2777 s->RxMissed = 0;
2778 break;
2780 case TxConfig:
2781 rtl8139_TxConfig_write(s, val);
2782 break;
2784 case RxConfig:
2785 rtl8139_RxConfig_write(s, val);
2786 break;
2788 case TxStatus0 ... TxStatus0+4*4-1:
2789 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2790 break;
2792 case TxAddr0 ... TxAddr0+4*4-1:
2793 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2794 break;
2796 case RxBuf:
2797 rtl8139_RxBuf_write(s, val);
2798 break;
2800 case RxRingAddrLO:
2801 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2802 s->RxRingAddrLO = val;
2803 break;
2805 case RxRingAddrHI:
2806 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2807 s->RxRingAddrHI = val;
2808 break;
2810 case Timer:
2811 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2812 s->TCTR = 0;
2813 s->TCTR_base = qemu_get_clock(vm_clock);
2814 break;
2816 case FlashReg:
2817 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2818 s->TimerInt = val;
2819 break;
2821 default:
2822 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2823 #ifdef TARGET_WORDS_BIGENDIAN
2824 rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff);
2825 rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2826 rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2827 rtl8139_io_writeb(opaque, addr + 3, val & 0xff);
2828 #else
2829 rtl8139_io_writeb(opaque, addr, val & 0xff);
2830 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2831 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2832 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2833 #endif
2834 break;
2838 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2840 RTL8139State *s = opaque;
2841 int ret;
2843 addr &= 0xff;
2845 switch (addr)
2847 case MAC0 ... MAC0+5:
2848 ret = s->phys[addr - MAC0];
2849 break;
2850 case MAC0+6 ... MAC0+7:
2851 ret = 0;
2852 break;
2853 case MAR0 ... MAR0+7:
2854 ret = s->mult[addr - MAR0];
2855 break;
2856 case ChipCmd:
2857 ret = rtl8139_ChipCmd_read(s);
2858 break;
2859 case Cfg9346:
2860 ret = rtl8139_Cfg9346_read(s);
2861 break;
2862 case Config0:
2863 ret = rtl8139_Config0_read(s);
2864 break;
2865 case Config1:
2866 ret = rtl8139_Config1_read(s);
2867 break;
2868 case Config3:
2869 ret = rtl8139_Config3_read(s);
2870 break;
2871 case Config4:
2872 ret = rtl8139_Config4_read(s);
2873 break;
2874 case Config5:
2875 ret = rtl8139_Config5_read(s);
2876 break;
2878 case MediaStatus:
2879 ret = 0xd0;
2880 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2881 break;
2883 case HltClk:
2884 ret = s->clock_enabled;
2885 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2886 break;
2888 case PCIRevisionID:
2889 ret = RTL8139_PCI_REVID;
2890 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2891 break;
2893 case TxThresh:
2894 ret = s->TxThresh;
2895 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2896 break;
2898 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2899 ret = s->TxConfig >> 24;
2900 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2901 break;
2903 default:
2904 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2905 ret = 0;
2906 break;
2909 return ret;
2912 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2914 RTL8139State *s = opaque;
2915 uint32_t ret;
2917 addr &= 0xfe; /* mask lower bit */
2919 switch (addr)
2921 case IntrMask:
2922 ret = rtl8139_IntrMask_read(s);
2923 break;
2925 case IntrStatus:
2926 ret = rtl8139_IntrStatus_read(s);
2927 break;
2929 case MultiIntr:
2930 ret = rtl8139_MultiIntr_read(s);
2931 break;
2933 case RxBufPtr:
2934 ret = rtl8139_RxBufPtr_read(s);
2935 break;
2937 case RxBufAddr:
2938 ret = rtl8139_RxBufAddr_read(s);
2939 break;
2941 case BasicModeCtrl:
2942 ret = rtl8139_BasicModeCtrl_read(s);
2943 break;
2944 case BasicModeStatus:
2945 ret = rtl8139_BasicModeStatus_read(s);
2946 break;
2947 case NWayAdvert:
2948 ret = s->NWayAdvert;
2949 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2950 break;
2951 case NWayLPAR:
2952 ret = s->NWayLPAR;
2953 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2954 break;
2955 case NWayExpansion:
2956 ret = s->NWayExpansion;
2957 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2958 break;
2960 case CpCmd:
2961 ret = rtl8139_CpCmd_read(s);
2962 break;
2964 case IntrMitigate:
2965 ret = rtl8139_IntrMitigate_read(s);
2966 break;
2968 case TxSummary:
2969 ret = rtl8139_TSAD_read(s);
2970 break;
2972 case CSCR:
2973 ret = rtl8139_CSCR_read(s);
2974 break;
2976 default:
2977 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2979 #ifdef TARGET_WORDS_BIGENDIAN
2980 ret = rtl8139_io_readb(opaque, addr) << 8;
2981 ret |= rtl8139_io_readb(opaque, addr + 1);
2982 #else
2983 ret = rtl8139_io_readb(opaque, addr);
2984 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2985 #endif
2987 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
2988 break;
2991 return ret;
2994 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2996 RTL8139State *s = opaque;
2997 uint32_t ret;
2999 addr &= 0xfc; /* also mask low 2 bits */
3001 switch (addr)
3003 case RxMissed:
3004 ret = s->RxMissed;
3006 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
3007 break;
3009 case TxConfig:
3010 ret = rtl8139_TxConfig_read(s);
3011 break;
3013 case RxConfig:
3014 ret = rtl8139_RxConfig_read(s);
3015 break;
3017 case TxStatus0 ... TxStatus0+4*4-1:
3018 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3019 break;
3021 case TxAddr0 ... TxAddr0+4*4-1:
3022 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3023 break;
3025 case RxBuf:
3026 ret = rtl8139_RxBuf_read(s);
3027 break;
3029 case RxRingAddrLO:
3030 ret = s->RxRingAddrLO;
3031 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3032 break;
3034 case RxRingAddrHI:
3035 ret = s->RxRingAddrHI;
3036 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3037 break;
3039 case Timer:
3040 ret = s->TCTR;
3041 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3042 break;
3044 case FlashReg:
3045 ret = s->TimerInt;
3046 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3047 break;
3049 default:
3050 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3052 #ifdef TARGET_WORDS_BIGENDIAN
3053 ret = rtl8139_io_readb(opaque, addr) << 24;
3054 ret |= rtl8139_io_readb(opaque, addr + 1) << 16;
3055 ret |= rtl8139_io_readb(opaque, addr + 2) << 8;
3056 ret |= rtl8139_io_readb(opaque, addr + 3);
3057 #else
3058 ret = rtl8139_io_readb(opaque, addr);
3059 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3060 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3061 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3062 #endif
3064 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3065 break;
3068 return ret;
3071 /* */
3073 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3075 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3078 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3080 rtl8139_io_writew(opaque, addr & 0xFF, val);
3083 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3085 rtl8139_io_writel(opaque, addr & 0xFF, val);
3088 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3090 return rtl8139_io_readb(opaque, addr & 0xFF);
3093 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3095 return rtl8139_io_readw(opaque, addr & 0xFF);
3098 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3100 return rtl8139_io_readl(opaque, addr & 0xFF);
3103 /* */
3105 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3107 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3110 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3112 rtl8139_io_writew(opaque, addr & 0xFF, val);
3115 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3117 rtl8139_io_writel(opaque, addr & 0xFF, val);
3120 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3122 return rtl8139_io_readb(opaque, addr & 0xFF);
3125 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3127 return rtl8139_io_readw(opaque, addr & 0xFF);
3130 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3132 return rtl8139_io_readl(opaque, addr & 0xFF);
3135 /* */
3137 static void rtl8139_save(QEMUFile* f,void* opaque)
3139 RTL8139State* s=(RTL8139State*)opaque;
3140 int i;
3142 pci_device_save(s->pci_dev, f);
3144 qemu_put_buffer(f, s->phys, 6);
3145 qemu_put_buffer(f, s->mult, 8);
3147 for (i=0; i<4; ++i)
3149 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3151 for (i=0; i<4; ++i)
3153 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3156 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3157 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3158 qemu_put_be32s(f, &s->RxBufPtr);
3159 qemu_put_be32s(f, &s->RxBufAddr);
3161 qemu_put_be16s(f, &s->IntrStatus);
3162 qemu_put_be16s(f, &s->IntrMask);
3164 qemu_put_be32s(f, &s->TxConfig);
3165 qemu_put_be32s(f, &s->RxConfig);
3166 qemu_put_be32s(f, &s->RxMissed);
3167 qemu_put_be16s(f, &s->CSCR);
3169 qemu_put_8s(f, &s->Cfg9346);
3170 qemu_put_8s(f, &s->Config0);
3171 qemu_put_8s(f, &s->Config1);
3172 qemu_put_8s(f, &s->Config3);
3173 qemu_put_8s(f, &s->Config4);
3174 qemu_put_8s(f, &s->Config5);
3176 qemu_put_8s(f, &s->clock_enabled);
3177 qemu_put_8s(f, &s->bChipCmdState);
3179 qemu_put_be16s(f, &s->MultiIntr);
3181 qemu_put_be16s(f, &s->BasicModeCtrl);
3182 qemu_put_be16s(f, &s->BasicModeStatus);
3183 qemu_put_be16s(f, &s->NWayAdvert);
3184 qemu_put_be16s(f, &s->NWayLPAR);
3185 qemu_put_be16s(f, &s->NWayExpansion);
3187 qemu_put_be16s(f, &s->CpCmd);
3188 qemu_put_8s(f, &s->TxThresh);
3190 qemu_put_be32s(f, &s->irq);
3191 qemu_put_buffer(f, s->macaddr, 6);
3192 qemu_put_be32s(f, &s->rtl8139_mmio_io_addr);
3194 qemu_put_be32s(f, &s->currTxDesc);
3195 qemu_put_be32s(f, &s->currCPlusRxDesc);
3196 qemu_put_be32s(f, &s->currCPlusTxDesc);
3197 qemu_put_be32s(f, &s->RxRingAddrLO);
3198 qemu_put_be32s(f, &s->RxRingAddrHI);
3200 for (i=0; i<EEPROM_9346_SIZE; ++i)
3202 qemu_put_be16s(f, &s->eeprom.contents[i]);
3204 qemu_put_be32s(f, &s->eeprom.mode);
3205 qemu_put_be32s(f, &s->eeprom.tick);
3206 qemu_put_8s(f, &s->eeprom.address);
3207 qemu_put_be16s(f, &s->eeprom.input);
3208 qemu_put_be16s(f, &s->eeprom.output);
3210 qemu_put_8s(f, &s->eeprom.eecs);
3211 qemu_put_8s(f, &s->eeprom.eesk);
3212 qemu_put_8s(f, &s->eeprom.eedi);
3213 qemu_put_8s(f, &s->eeprom.eedo);
3215 qemu_put_be32s(f, &s->TCTR);
3216 qemu_put_be32s(f, &s->TimerInt);
3217 qemu_put_be64s(f, &s->TCTR_base);
3219 RTL8139TallyCounters_save(f, &s->tally_counters);
3222 static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3224 RTL8139State* s=(RTL8139State*)opaque;
3225 int i, ret;
3227 /* just 2 versions for now */
3228 if (version_id > 3)
3229 return -EINVAL;
3231 if (version_id >= 3) {
3232 ret = pci_device_load(s->pci_dev, f);
3233 if (ret < 0)
3234 return ret;
3237 /* saved since version 1 */
3238 qemu_get_buffer(f, s->phys, 6);
3239 qemu_get_buffer(f, s->mult, 8);
3241 for (i=0; i<4; ++i)
3243 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3245 for (i=0; i<4; ++i)
3247 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3250 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3251 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3252 qemu_get_be32s(f, &s->RxBufPtr);
3253 qemu_get_be32s(f, &s->RxBufAddr);
3255 qemu_get_be16s(f, &s->IntrStatus);
3256 qemu_get_be16s(f, &s->IntrMask);
3258 qemu_get_be32s(f, &s->TxConfig);
3259 qemu_get_be32s(f, &s->RxConfig);
3260 qemu_get_be32s(f, &s->RxMissed);
3261 qemu_get_be16s(f, &s->CSCR);
3263 qemu_get_8s(f, &s->Cfg9346);
3264 qemu_get_8s(f, &s->Config0);
3265 qemu_get_8s(f, &s->Config1);
3266 qemu_get_8s(f, &s->Config3);
3267 qemu_get_8s(f, &s->Config4);
3268 qemu_get_8s(f, &s->Config5);
3270 qemu_get_8s(f, &s->clock_enabled);
3271 qemu_get_8s(f, &s->bChipCmdState);
3273 qemu_get_be16s(f, &s->MultiIntr);
3275 qemu_get_be16s(f, &s->BasicModeCtrl);
3276 qemu_get_be16s(f, &s->BasicModeStatus);
3277 qemu_get_be16s(f, &s->NWayAdvert);
3278 qemu_get_be16s(f, &s->NWayLPAR);
3279 qemu_get_be16s(f, &s->NWayExpansion);
3281 qemu_get_be16s(f, &s->CpCmd);
3282 qemu_get_8s(f, &s->TxThresh);
3284 qemu_get_be32s(f, &s->irq);
3285 qemu_get_buffer(f, s->macaddr, 6);
3286 qemu_get_be32s(f, &s->rtl8139_mmio_io_addr);
3288 qemu_get_be32s(f, &s->currTxDesc);
3289 qemu_get_be32s(f, &s->currCPlusRxDesc);
3290 qemu_get_be32s(f, &s->currCPlusTxDesc);
3291 qemu_get_be32s(f, &s->RxRingAddrLO);
3292 qemu_get_be32s(f, &s->RxRingAddrHI);
3294 for (i=0; i<EEPROM_9346_SIZE; ++i)
3296 qemu_get_be16s(f, &s->eeprom.contents[i]);
3298 qemu_get_be32s(f, &s->eeprom.mode);
3299 qemu_get_be32s(f, &s->eeprom.tick);
3300 qemu_get_8s(f, &s->eeprom.address);
3301 qemu_get_be16s(f, &s->eeprom.input);
3302 qemu_get_be16s(f, &s->eeprom.output);
3304 qemu_get_8s(f, &s->eeprom.eecs);
3305 qemu_get_8s(f, &s->eeprom.eesk);
3306 qemu_get_8s(f, &s->eeprom.eedi);
3307 qemu_get_8s(f, &s->eeprom.eedo);
3309 /* saved since version 2 */
3310 if (version_id >= 2)
3312 qemu_get_be32s(f, &s->TCTR);
3313 qemu_get_be32s(f, &s->TimerInt);
3314 qemu_get_be64s(f, &s->TCTR_base);
3316 RTL8139TallyCounters_load(f, &s->tally_counters);
3318 else
3320 /* not saved, use default */
3321 s->TCTR = 0;
3322 s->TimerInt = 0;
3323 s->TCTR_base = 0;
3325 RTL8139TallyCounters_clear(&s->tally_counters);
3328 return 0;
3331 /***********************************************************/
3332 /* PCI RTL8139 definitions */
3334 typedef struct PCIRTL8139State {
3335 PCIDevice dev;
3336 RTL8139State rtl8139;
3337 } PCIRTL8139State;
3339 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3340 uint32_t addr, uint32_t size, int type)
3342 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3343 RTL8139State *s = &d->rtl8139;
3345 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3348 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3349 uint32_t addr, uint32_t size, int type)
3351 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3352 RTL8139State *s = &d->rtl8139;
3354 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3355 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3357 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3358 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3360 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3361 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3364 static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3365 rtl8139_mmio_readb,
3366 rtl8139_mmio_readw,
3367 rtl8139_mmio_readl,
3368 };
3370 static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3371 rtl8139_mmio_writeb,
3372 rtl8139_mmio_writew,
3373 rtl8139_mmio_writel,
3374 };
3376 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3378 int64_t next_time = current_time +
3379 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3380 if (next_time <= current_time)
3381 next_time = current_time + 1;
3382 return next_time;
3385 #if RTL8139_ONBOARD_TIMER
3386 static void rtl8139_timer(void *opaque)
3388 RTL8139State *s = opaque;
3390 int is_timeout = 0;
3392 int64_t curr_time;
3393 uint32_t curr_tick;
3395 if (!s->clock_enabled)
3397 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3398 return;
3401 curr_time = qemu_get_clock(vm_clock);
3403 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3405 if (s->TimerInt && curr_tick >= s->TimerInt)
3407 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3409 is_timeout = 1;
3413 s->TCTR = curr_tick;
3415 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3417 if (is_timeout)
3419 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3420 s->IntrStatus |= PCSTimeout;
3421 rtl8139_update_irq(s);
3424 qemu_mod_timer(s->timer,
3425 rtl8139_get_next_tctr_time(s,curr_time));
3427 #endif /* RTL8139_ONBOARD_TIMER */
3429 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
3431 PCIRTL8139State *d;
3432 RTL8139State *s;
3433 uint8_t *pci_conf;
3434 int instance;
3436 d = (PCIRTL8139State *)pci_register_device(bus,
3437 "RTL8139", sizeof(PCIRTL8139State),
3438 devfn,
3439 NULL, NULL);
3440 pci_conf = d->dev.config;
3441 pci_conf[0x00] = 0xec; /* Realtek 8139 */
3442 pci_conf[0x01] = 0x10;
3443 pci_conf[0x02] = 0x39;
3444 pci_conf[0x03] = 0x81;
3445 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3446 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3447 pci_conf[0x0a] = 0x00; /* ethernet network controller */
3448 pci_conf[0x0b] = 0x02;
3449 pci_conf[0x0e] = 0x00; /* header_type */
3450 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3451 pci_conf[0x34] = 0xdc;
3452 pci_conf[0x2c] = 0x53; /* subsystem vendor: XenSource */
3453 pci_conf[0x2d] = 0x58;
3454 pci_conf[0x2e] = 0x01; /* subsystem device */
3455 pci_conf[0x2f] = 0x00;
3457 s = &d->rtl8139;
3459 /* I/O handler for memory-mapped I/O */
3460 s->rtl8139_mmio_io_addr =
3461 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3463 pci_register_io_region(&d->dev, 0, 0x100,
3464 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3466 pci_register_io_region(&d->dev, 1, 0x100,
3467 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3469 s->irq = 16; /* PCI interrupt */
3470 s->pci_dev = (PCIDevice *)d;
3471 memcpy(s->macaddr, nd->macaddr, 6);
3472 rtl8139_reset(s);
3473 s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive,
3474 rtl8139_can_receive, s);
3476 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
3477 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3478 s->macaddr[0],
3479 s->macaddr[1],
3480 s->macaddr[2],
3481 s->macaddr[3],
3482 s->macaddr[4],
3483 s->macaddr[5]);
3485 s->cplus_txbuffer = NULL;
3486 s->cplus_txbuffer_len = 0;
3487 s->cplus_txbuffer_offset = 0;
3489 instance = pci_bus_num(bus) << 8 | s->pci_dev->devfn;
3490 register_savevm("rtl8139", instance, 3, rtl8139_save, rtl8139_load, s);
3492 #if RTL8139_ONBOARD_TIMER
3493 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3495 qemu_mod_timer(s->timer,
3496 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3497 #endif /* RTL8139_ONBOARD_TIMER */