ia64/xen-unstable

view linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h @ 4768:3fd85cfa1932

bitkeeper revision 1.1389.7.3 (42792bb0bqVz6IEYKWbCD7d63K-6ew)

fixmap.h, boot.c, tables.c, io_apic.h:
Cleanup whitespace.
Signed-off-by: Christian Limpach <Christian.Limpach@cl.cam.ac.uk>
author cl349@firebug.cl.cam.ac.uk
date Wed May 04 20:08:16 2005 +0000 (2005-05-04)
parents d8a9ad9290ac
children 86c325c8937a
line source
1 #ifndef __ASM_IO_APIC_H
2 #define __ASM_IO_APIC_H
4 #include <linux/config.h>
5 #include <asm/types.h>
6 #include <asm/mpspec.h>
8 #include <asm-xen/xen-public/xen.h>
9 #include <asm-xen/xen-public/physdev.h>
11 /*
12 * Intel IO-APIC support for SMP and UP systems.
13 *
14 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
15 */
17 #ifdef CONFIG_X86_IO_APIC
19 #ifdef CONFIG_PCI_MSI
20 static inline int use_pci_vector(void) {return 1;}
21 static inline void disable_edge_ioapic_vector(unsigned int vector) { }
22 static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
23 static inline void end_edge_ioapic_vector (unsigned int vector) { }
24 #define startup_level_ioapic startup_level_ioapic_vector
25 #define shutdown_level_ioapic mask_IO_APIC_vector
26 #define enable_level_ioapic unmask_IO_APIC_vector
27 #define disable_level_ioapic mask_IO_APIC_vector
28 #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
29 #define end_level_ioapic end_level_ioapic_vector
30 #define set_ioapic_affinity set_ioapic_affinity_vector
32 #define startup_edge_ioapic startup_edge_ioapic_vector
33 #define shutdown_edge_ioapic disable_edge_ioapic_vector
34 #define enable_edge_ioapic unmask_IO_APIC_vector
35 #define disable_edge_ioapic disable_edge_ioapic_vector
36 #define ack_edge_ioapic ack_edge_ioapic_vector
37 #define end_edge_ioapic end_edge_ioapic_vector
38 #else
39 static inline int use_pci_vector(void) {return 0;}
40 static inline void disable_edge_ioapic_irq(unsigned int irq) { }
41 static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
42 static inline void end_edge_ioapic_irq (unsigned int irq) { }
43 #define startup_level_ioapic startup_level_ioapic_irq
44 #define shutdown_level_ioapic mask_IO_APIC_irq
45 #define enable_level_ioapic unmask_IO_APIC_irq
46 #define disable_level_ioapic mask_IO_APIC_irq
47 #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
48 #define end_level_ioapic end_level_ioapic_irq
49 #define set_ioapic_affinity set_ioapic_affinity_irq
51 #define startup_edge_ioapic startup_edge_ioapic_irq
52 #define shutdown_edge_ioapic disable_edge_ioapic_irq
53 #define enable_edge_ioapic unmask_IO_APIC_irq
54 #define disable_edge_ioapic disable_edge_ioapic_irq
55 #define ack_edge_ioapic ack_edge_ioapic_irq
56 #define end_edge_ioapic end_edge_ioapic_irq
57 #endif
59 #define IO_APIC_BASE(idx) \
60 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
61 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
63 /*
64 * The structure of the IO-APIC:
65 */
66 union IO_APIC_reg_00 {
67 u32 raw;
68 struct {
69 u32 __reserved_2 : 14,
70 LTS : 1,
71 delivery_type : 1,
72 __reserved_1 : 8,
73 ID : 8;
74 } __attribute__ ((packed)) bits;
75 };
77 union IO_APIC_reg_01 {
78 u32 raw;
79 struct {
80 u32 version : 8,
81 __reserved_2 : 7,
82 PRQ : 1,
83 entries : 8,
84 __reserved_1 : 8;
85 } __attribute__ ((packed)) bits;
86 };
88 union IO_APIC_reg_02 {
89 u32 raw;
90 struct {
91 u32 __reserved_2 : 24,
92 arbitration : 4,
93 __reserved_1 : 4;
94 } __attribute__ ((packed)) bits;
95 };
97 union IO_APIC_reg_03 {
98 u32 raw;
99 struct {
100 u32 boot_DT : 1,
101 __reserved_1 : 31;
102 } __attribute__ ((packed)) bits;
103 };
105 /*
106 * # of IO-APICs and # of IRQ routing registers
107 */
108 extern int nr_ioapics;
109 extern int nr_ioapic_registers[MAX_IO_APICS];
111 enum ioapic_irq_destination_types {
112 dest_Fixed = 0,
113 dest_LowestPrio = 1,
114 dest_SMI = 2,
115 dest__reserved_1 = 3,
116 dest_NMI = 4,
117 dest_INIT = 5,
118 dest__reserved_2 = 6,
119 dest_ExtINT = 7
120 };
122 struct IO_APIC_route_entry {
123 __u32 vector : 8,
124 delivery_mode : 3, /* 000: FIXED
125 * 001: lowest prio
126 * 111: ExtINT
127 */
128 dest_mode : 1, /* 0: physical, 1: logical */
129 delivery_status : 1,
130 polarity : 1,
131 irr : 1,
132 trigger : 1, /* 0: edge, 1: level */
133 mask : 1, /* 0: enabled, 1: disabled */
134 __reserved_2 : 15;
136 union { struct { __u32
137 __reserved_1 : 24,
138 physical_dest : 4,
139 __reserved_2 : 4;
140 } physical;
142 struct { __u32
143 __reserved_1 : 24,
144 logical_dest : 8;
145 } logical;
146 } dest;
148 } __attribute__ ((packed));
150 /*
151 * MP-BIOS irq configuration table structures:
152 */
154 /* I/O APIC entries */
155 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
157 /* # of MP IRQ source entries */
158 extern int mp_irq_entries;
160 /* MP IRQ source entries */
161 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
163 /* non-0 if default (table-less) MP configuration */
164 extern int mpc_default_type;
166 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
167 {
168 physdev_op_t op;
169 int ret;
171 op.cmd = PHYSDEVOP_APIC_READ;
172 op.u.apic_op.apic = apic;
173 op.u.apic_op.offset = reg;
174 ret = HYPERVISOR_physdev_op(&op);
175 if (ret)
176 return ret;
177 return op.u.apic_op.value;
178 }
180 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
181 {
182 physdev_op_t op;
184 op.cmd = PHYSDEVOP_APIC_WRITE;
185 op.u.apic_op.apic = apic;
186 op.u.apic_op.offset = reg;
187 op.u.apic_op.value = value;
188 HYPERVISOR_physdev_op(&op);
189 }
191 /*
192 * Re-write a value: to be used for read-modify-write
193 * cycles where the read already set up the index register.
194 *
195 * Older SiS APIC requires we rewrite the index regiser
196 */
197 extern int sis_apic_bug;
198 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
199 {
200 if (sis_apic_bug)
201 *IO_APIC_BASE(apic) = reg;
202 *(IO_APIC_BASE(apic)+4) = value;
203 }
205 /* 1 if "noapic" boot option passed */
206 extern int skip_ioapic_setup;
208 /*
209 * If we use the IO-APIC for IRQ routing, disable automatic
210 * assignment of PCI IRQ's.
211 */
212 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
214 #ifdef CONFIG_ACPI_BOOT
215 extern int io_apic_get_unique_id (int ioapic, int apic_id);
216 extern int io_apic_get_version (int ioapic);
217 extern int io_apic_get_redir_entries (int ioapic);
218 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
219 #endif /*CONFIG_ACPI_BOOT*/
221 extern int (*ioapic_renumber_irq)(int ioapic, int irq);
223 #else /* !CONFIG_X86_IO_APIC */
224 #define io_apic_assign_pci_irqs 0
225 #endif
227 extern int assign_irq_vector(int irq);
229 #endif