ia64/xen-unstable

view xen/arch/x86/hvm/vlapic.c @ 16617:3ee37b6279b7

hvm: Remove guest-triggerable assertions from vlapic emulation.

Currently our VLAPIC will happily deliver interrupts on vectors <
16. This could be emulated better, but probably does not matter.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Dec 14 10:48:18 2007 +0000 (2007-12-14)
parents 4553bc1087d9
children 966a6d3b7408
line source
1 /*
2 * vlapic.c: virtualize LAPIC for HVM vcpus.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 * Copyright (c) 2006 Keir Fraser, XenSource Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 */
21 #include <xen/config.h>
22 #include <xen/types.h>
23 #include <xen/mm.h>
24 #include <xen/xmalloc.h>
25 #include <xen/domain_page.h>
26 #include <asm/page.h>
27 #include <xen/event.h>
28 #include <xen/trace.h>
29 #include <asm/hvm/hvm.h>
30 #include <asm/hvm/io.h>
31 #include <asm/hvm/support.h>
32 #include <xen/lib.h>
33 #include <xen/sched.h>
34 #include <asm/current.h>
35 #include <asm/hvm/vmx/vmx.h>
36 #include <public/hvm/ioreq.h>
37 #include <public/hvm/params.h>
39 #define VLAPIC_VERSION 0x00050014
40 #define VLAPIC_LVT_NUM 6
42 /* vlapic's frequence is 100 MHz */
43 #define APIC_BUS_CYCLE_NS 10
45 #define LVT_MASK \
46 APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK
48 #define LINT_MASK \
49 LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY |\
50 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER
52 static unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
53 {
54 /* LVTT */
55 LVT_MASK | APIC_LVT_TIMER_PERIODIC,
56 /* LVTTHMR */
57 LVT_MASK | APIC_MODE_MASK,
58 /* LVTPC */
59 LVT_MASK | APIC_MODE_MASK,
60 /* LVT0-1 */
61 LINT_MASK, LINT_MASK,
62 /* LVTERR */
63 LVT_MASK
64 };
66 /* Following could belong in apicdef.h */
67 #define APIC_SHORT_MASK 0xc0000
68 #define APIC_DEST_NOSHORT 0x0
69 #define APIC_DEST_MASK 0x800
71 #define vlapic_lvt_vector(vlapic, lvt_type) \
72 (vlapic_get_reg(vlapic, lvt_type) & APIC_VECTOR_MASK)
74 #define vlapic_lvt_dm(vlapic, lvt_type) \
75 (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
77 #define vlapic_lvtt_period(vlapic) \
78 (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
81 /*
82 * Generic APIC bitmap vector update & search routines.
83 */
85 #define VEC_POS(v) ((v)%32)
86 #define REG_POS(v) (((v)/32)* 0x10)
87 #define vlapic_test_and_set_vector(vec, bitmap) \
88 test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
89 #define vlapic_test_and_clear_vector(vec, bitmap) \
90 test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
91 #define vlapic_set_vector(vec, bitmap) \
92 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
93 #define vlapic_clear_vector(vec, bitmap) \
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
96 static int vlapic_find_highest_vector(void *bitmap)
97 {
98 uint32_t *word = bitmap;
99 int word_offset = MAX_VECTOR / 32;
101 /* Work backwards through the bitmap (first 32-bit word in every four). */
102 while ( (word_offset != 0) && (word[(--word_offset)*4] == 0) )
103 continue;
105 return (fls(word[word_offset*4]) - 1) + (word_offset * 32);
106 }
109 /*
110 * IRR-specific bitmap update & search routines.
111 */
113 static int vlapic_test_and_set_irr(int vector, struct vlapic *vlapic)
114 {
115 return vlapic_test_and_set_vector(vector, &vlapic->regs->data[APIC_IRR]);
116 }
118 static void vlapic_clear_irr(int vector, struct vlapic *vlapic)
119 {
120 vlapic_clear_vector(vector, &vlapic->regs->data[APIC_IRR]);
121 }
123 static int vlapic_find_highest_irr(struct vlapic *vlapic)
124 {
125 return vlapic_find_highest_vector(&vlapic->regs->data[APIC_IRR]);
126 }
128 int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
129 {
130 int ret;
132 ret = !vlapic_test_and_set_irr(vec, vlapic);
133 if ( trig )
134 vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
136 /* We may need to wake up target vcpu, besides set pending bit here */
137 return ret;
138 }
140 static int vlapic_find_highest_isr(struct vlapic *vlapic)
141 {
142 return vlapic_find_highest_vector(&vlapic->regs->data[APIC_ISR]);
143 }
145 uint32_t vlapic_get_ppr(struct vlapic *vlapic)
146 {
147 uint32_t tpr, isrv, ppr;
148 int isr;
150 tpr = vlapic_get_reg(vlapic, APIC_TASKPRI);
151 isr = vlapic_find_highest_isr(vlapic);
152 isrv = (isr != -1) ? isr : 0;
154 if ( (tpr & 0xf0) >= (isrv & 0xf0) )
155 ppr = tpr & 0xff;
156 else
157 ppr = isrv & 0xf0;
159 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_INTERRUPT,
160 "vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
161 vlapic, ppr, isr, isrv);
163 return ppr;
164 }
166 int vlapic_match_logical_addr(struct vlapic *vlapic, uint8_t mda)
167 {
168 int result = 0;
169 uint8_t logical_id;
171 logical_id = GET_APIC_LOGICAL_ID(vlapic_get_reg(vlapic, APIC_LDR));
173 switch ( vlapic_get_reg(vlapic, APIC_DFR) )
174 {
175 case APIC_DFR_FLAT:
176 if ( logical_id & mda )
177 result = 1;
178 break;
179 case APIC_DFR_CLUSTER:
180 if ( ((logical_id >> 4) == (mda >> 0x4)) && (logical_id & mda & 0xf) )
181 result = 1;
182 break;
183 default:
184 gdprintk(XENLOG_WARNING, "Bad DFR value for lapic of vcpu %d: %08x\n",
185 vlapic_vcpu(vlapic)->vcpu_id,
186 vlapic_get_reg(vlapic, APIC_DFR));
187 break;
188 }
190 return result;
191 }
193 static int vlapic_match_dest(struct vcpu *v, struct vlapic *source,
194 int short_hand, int dest, int dest_mode)
195 {
196 int result = 0;
197 struct vlapic *target = vcpu_vlapic(v);
199 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "target %p, source %p, dest 0x%x, "
200 "dest_mode 0x%x, short_hand 0x%x",
201 target, source, dest, dest_mode, short_hand);
203 switch ( short_hand )
204 {
205 case APIC_DEST_NOSHORT:
206 if ( dest_mode == 0 )
207 {
208 /* Physical mode. */
209 if ( (dest == 0xFF) || (dest == VLAPIC_ID(target)) )
210 result = 1;
211 }
212 else
213 {
214 /* Logical mode. */
215 result = vlapic_match_logical_addr(target, dest);
216 }
217 break;
219 case APIC_DEST_SELF:
220 if ( target == source )
221 result = 1;
222 break;
224 case APIC_DEST_ALLINC:
225 result = 1;
226 break;
228 case APIC_DEST_ALLBUT:
229 if ( target != source )
230 result = 1;
231 break;
233 default:
234 gdprintk(XENLOG_WARNING, "Bad dest shorthand value %x\n", short_hand);
235 break;
236 }
238 return result;
239 }
241 /* Add a pending IRQ into lapic. */
242 static int vlapic_accept_irq(struct vcpu *v, int delivery_mode,
243 int vector, int level, int trig_mode)
244 {
245 int result = 0;
246 struct vlapic *vlapic = vcpu_vlapic(v);
248 switch ( delivery_mode )
249 {
250 case APIC_DM_FIXED:
251 case APIC_DM_LOWEST:
252 /* FIXME add logic for vcpu on reset */
253 if ( unlikely(!vlapic_enabled(vlapic)) )
254 break;
256 if ( vlapic_test_and_set_irr(vector, vlapic) && trig_mode )
257 {
258 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
259 "level trig mode repeatedly for vector %d", vector);
260 break;
261 }
263 if ( trig_mode )
264 {
265 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
266 "level trig mode for vector %d", vector);
267 vlapic_set_vector(vector, &vlapic->regs->data[APIC_TMR]);
268 }
270 vcpu_kick(v);
272 result = 1;
273 break;
275 case APIC_DM_REMRD:
276 gdprintk(XENLOG_WARNING, "Ignoring delivery mode 3\n");
277 break;
279 case APIC_DM_SMI:
280 gdprintk(XENLOG_WARNING, "Ignoring guest SMI\n");
281 break;
283 case APIC_DM_NMI:
284 if ( !test_and_set_bool(v->nmi_pending) )
285 vcpu_kick(v);
286 break;
288 case APIC_DM_INIT:
289 /* No work on INIT de-assert for P4-type APIC. */
290 if ( trig_mode && !(level & APIC_INT_ASSERT) )
291 break;
292 /* FIXME How to check the situation after vcpu reset? */
293 if ( v->is_initialised )
294 hvm_vcpu_reset(v);
295 v->arch.hvm_vcpu.init_sipi_sipi_state =
296 HVM_VCPU_INIT_SIPI_SIPI_STATE_WAIT_SIPI;
297 result = 1;
298 break;
300 case APIC_DM_STARTUP:
301 if ( v->arch.hvm_vcpu.init_sipi_sipi_state ==
302 HVM_VCPU_INIT_SIPI_SIPI_STATE_NORM )
303 break;
305 v->arch.hvm_vcpu.init_sipi_sipi_state =
306 HVM_VCPU_INIT_SIPI_SIPI_STATE_NORM;
308 if ( v->is_initialised )
309 {
310 gdprintk(XENLOG_ERR, "SIPI for initialized vcpu %x\n", v->vcpu_id);
311 goto exit_and_crash;
312 }
314 if ( hvm_bringup_ap(v->vcpu_id, vector) != 0 )
315 result = 0;
316 break;
318 default:
319 gdprintk(XENLOG_ERR, "TODO: unsupported delivery mode %x\n",
320 delivery_mode);
321 goto exit_and_crash;
322 }
324 return result;
326 exit_and_crash:
327 domain_crash(v->domain);
328 return 0;
329 }
331 /* This function is used by both ioapic and lapic.The bitmap is for vcpu_id. */
332 struct vlapic *apic_round_robin(
333 struct domain *d, uint8_t vector, uint32_t bitmap)
334 {
335 int next, old;
336 struct vlapic *target = NULL;
338 old = next = d->arch.hvm_domain.irq.round_robin_prev_vcpu;
340 do {
341 if ( ++next == MAX_VIRT_CPUS )
342 next = 0;
343 if ( (d->vcpu[next] == NULL) || !test_bit(next, &bitmap) )
344 continue;
345 target = vcpu_vlapic(d->vcpu[next]);
346 if ( vlapic_enabled(target) )
347 break;
348 target = NULL;
349 } while ( next != old );
351 d->arch.hvm_domain.irq.round_robin_prev_vcpu = next;
353 return target;
354 }
356 void vlapic_EOI_set(struct vlapic *vlapic)
357 {
358 int vector = vlapic_find_highest_isr(vlapic);
360 /* Some EOI writes may not have a matching to an in-service interrupt. */
361 if ( vector == -1 )
362 return;
364 vlapic_clear_vector(vector, &vlapic->regs->data[APIC_ISR]);
366 if ( vlapic_test_and_clear_vector(vector, &vlapic->regs->data[APIC_TMR]) )
367 vioapic_update_EOI(vlapic_domain(vlapic), vector);
368 }
370 static void vlapic_ipi(struct vlapic *vlapic)
371 {
372 uint32_t icr_low = vlapic_get_reg(vlapic, APIC_ICR);
373 uint32_t icr_high = vlapic_get_reg(vlapic, APIC_ICR2);
375 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
376 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
377 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
378 unsigned int level = icr_low & APIC_INT_ASSERT;
379 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
380 unsigned int delivery_mode =icr_low & APIC_MODE_MASK;
381 unsigned int vector = icr_low & APIC_VECTOR_MASK;
383 struct vlapic *target;
384 struct vcpu *v;
385 uint32_t lpr_map = 0;
387 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "icr_high 0x%x, icr_low 0x%x, "
388 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
389 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x",
390 icr_high, icr_low, short_hand, dest,
391 trig_mode, level, dest_mode, delivery_mode, vector);
393 for_each_vcpu ( vlapic_domain(vlapic), v )
394 {
395 if ( vlapic_match_dest(v, vlapic, short_hand, dest, dest_mode) )
396 {
397 if ( delivery_mode == APIC_DM_LOWEST )
398 __set_bit(v->vcpu_id, &lpr_map);
399 else
400 vlapic_accept_irq(v, delivery_mode,
401 vector, level, trig_mode);
402 }
403 }
405 if ( delivery_mode == APIC_DM_LOWEST )
406 {
407 target = apic_round_robin(vlapic_domain(v), vector, lpr_map);
408 if ( target != NULL )
409 vlapic_accept_irq(vlapic_vcpu(target), delivery_mode,
410 vector, level, trig_mode);
411 }
412 }
414 static uint32_t vlapic_get_tmcct(struct vlapic *vlapic)
415 {
416 struct vcpu *v = current;
417 uint32_t tmcct, tmict = vlapic_get_reg(vlapic, APIC_TMICT);
418 uint64_t counter_passed;
420 counter_passed = ((hvm_get_guest_time(v) - vlapic->timer_last_update)
421 * 1000000000ULL / ticks_per_sec(v)
422 / APIC_BUS_CYCLE_NS / vlapic->hw.timer_divisor);
423 tmcct = tmict - counter_passed;
425 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
426 "timer initial count %d, timer current count %d, "
427 "offset %"PRId64,
428 tmict, tmcct, counter_passed);
430 return tmcct;
431 }
433 static void vlapic_set_tdcr(struct vlapic *vlapic, unsigned int val)
434 {
435 /* Only bits 0, 1 and 3 are settable; others are MBZ. */
436 val &= 0xb;
437 vlapic_set_reg(vlapic, APIC_TDCR, val);
439 /* Update the demangled hw.timer_divisor. */
440 val = ((val & 3) | ((val & 8) >> 1)) + 1;
441 vlapic->hw.timer_divisor = 1 << (val & 7);
443 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
444 "timer_divisor: %d", vlapic->hw.timer_divisor);
445 }
447 static void vlapic_read_aligned(
448 struct vlapic *vlapic, unsigned int offset, unsigned int *result)
449 {
450 switch ( offset )
451 {
452 case APIC_PROCPRI:
453 *result = vlapic_get_ppr(vlapic);
454 break;
456 case APIC_TMCCT: /* Timer CCR */
457 *result = vlapic_get_tmcct(vlapic);
458 break;
460 default:
461 *result = vlapic_get_reg(vlapic, offset);
462 break;
463 }
464 }
466 static unsigned long vlapic_read(struct vcpu *v, unsigned long address,
467 unsigned long len)
468 {
469 unsigned int alignment;
470 unsigned int tmp;
471 unsigned long result;
472 struct vlapic *vlapic = vcpu_vlapic(v);
473 unsigned int offset = address - vlapic_base_address(vlapic);
475 if ( offset > APIC_TDCR )
476 return 0;
478 alignment = offset & 0x3;
480 vlapic_read_aligned(vlapic, offset & ~0x3, &tmp);
481 switch ( len )
482 {
483 case 1:
484 result = *((unsigned char *)&tmp + alignment);
485 break;
487 case 2:
488 if ( alignment == 3 )
489 goto unaligned_exit_and_crash;
490 result = *(unsigned short *)((unsigned char *)&tmp + alignment);
491 break;
493 case 4:
494 if ( alignment != 0 )
495 goto unaligned_exit_and_crash;
496 result = *(unsigned int *)((unsigned char *)&tmp + alignment);
497 break;
499 default:
500 gdprintk(XENLOG_ERR, "Local APIC read with len=0x%lx, "
501 "should be 4 instead.\n", len);
502 goto exit_and_crash;
503 }
505 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "offset 0x%x with length 0x%lx, "
506 "and the result is 0x%lx", offset, len, result);
508 return result;
510 unaligned_exit_and_crash:
511 gdprintk(XENLOG_ERR, "Unaligned LAPIC read len=0x%lx at offset=0x%x.\n",
512 len, offset);
513 exit_and_crash:
514 domain_crash(v->domain);
515 return 0;
516 }
518 void vlapic_pt_cb(struct vcpu *v, void *data)
519 {
520 *(s_time_t *)data = hvm_get_guest_time(v);
521 }
523 static void vlapic_write(struct vcpu *v, unsigned long address,
524 unsigned long len, unsigned long val)
525 {
526 struct vlapic *vlapic = vcpu_vlapic(v);
527 unsigned int offset = address - vlapic_base_address(vlapic);
529 if ( offset != 0xb0 )
530 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
531 "offset 0x%x with length 0x%lx, and value is 0x%lx",
532 offset, len, val);
534 /*
535 * According to the IA32 Manual, all accesses should be 32 bits.
536 * Some OSes do 8- or 16-byte accesses, however.
537 */
538 val &= 0xffffffff;
539 if ( len != 4 )
540 {
541 unsigned int tmp;
542 unsigned char alignment;
544 gdprintk(XENLOG_INFO, "Notice: Local APIC write with len = %lx\n",len);
546 alignment = offset & 0x3;
547 tmp = vlapic_read(v, offset & ~0x3, 4);
549 switch ( len )
550 {
551 case 1:
552 val = (tmp & ~(0xff << (8*alignment))) |
553 ((val & 0xff) << (8*alignment));
554 break;
556 case 2:
557 if ( alignment & 1 )
558 {
559 gdprintk(XENLOG_ERR, "Uneven alignment error for "
560 "2-byte vlapic access\n");
561 goto exit_and_crash;
562 }
564 val = (tmp & ~(0xffff << (8*alignment))) |
565 ((val & 0xffff) << (8*alignment));
566 break;
568 default:
569 gdprintk(XENLOG_ERR, "Local APIC write with len = %lx, "
570 "should be 4 instead\n", len);
571 exit_and_crash:
572 domain_crash(v->domain);
573 return;
574 }
575 }
577 offset &= 0xff0;
579 switch ( offset )
580 {
581 case APIC_TASKPRI:
582 vlapic_set_reg(vlapic, APIC_TASKPRI, val & 0xff);
583 hvm_update_vtpr(v, (val >> 4) & 0x0f);
584 break;
586 case APIC_EOI:
587 vlapic_EOI_set(vlapic);
588 break;
590 case APIC_LDR:
591 vlapic_set_reg(vlapic, APIC_LDR, val & APIC_LDR_MASK);
592 break;
594 case APIC_DFR:
595 vlapic_set_reg(vlapic, APIC_DFR, val | 0x0FFFFFFF);
596 break;
598 case APIC_SPIV:
599 vlapic_set_reg(vlapic, APIC_SPIV, val & 0x3ff);
601 if ( !(val & APIC_SPIV_APIC_ENABLED) )
602 {
603 int i;
604 uint32_t lvt_val;
606 vlapic->hw.disabled |= VLAPIC_SW_DISABLED;
608 for ( i = 0; i < VLAPIC_LVT_NUM; i++ )
609 {
610 lvt_val = vlapic_get_reg(vlapic, APIC_LVTT + 0x10 * i);
611 vlapic_set_reg(vlapic, APIC_LVTT + 0x10 * i,
612 lvt_val | APIC_LVT_MASKED);
613 }
614 }
615 else
616 vlapic->hw.disabled &= ~VLAPIC_SW_DISABLED;
617 break;
619 case APIC_ESR:
620 /* Nothing to do. */
621 break;
623 case APIC_ICR:
624 /* No delay here, so we always clear the pending bit*/
625 vlapic_set_reg(vlapic, APIC_ICR, val & ~(1 << 12));
626 vlapic_ipi(vlapic);
627 break;
629 case APIC_ICR2:
630 vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000);
631 break;
633 case APIC_LVTT: /* LVT Timer Reg */
634 vlapic->pt.irq = val & APIC_VECTOR_MASK;
635 case APIC_LVTTHMR: /* LVT Thermal Monitor */
636 case APIC_LVTPC: /* LVT Performance Counter */
637 case APIC_LVT0: /* LVT LINT0 Reg */
638 case APIC_LVT1: /* LVT Lint1 Reg */
639 case APIC_LVTERR: /* LVT Error Reg */
640 if ( vlapic_sw_disabled(vlapic) )
641 val |= APIC_LVT_MASKED;
642 val &= vlapic_lvt_mask[(offset - APIC_LVTT) >> 4];
643 vlapic_set_reg(vlapic, offset, val);
644 break;
646 case APIC_TMICT:
647 {
648 uint64_t period = (uint64_t)APIC_BUS_CYCLE_NS *
649 (uint32_t)val * vlapic->hw.timer_divisor;
651 vlapic_set_reg(vlapic, APIC_TMICT, val);
652 create_periodic_time(current, &vlapic->pt, period, vlapic->pt.irq,
653 !vlapic_lvtt_period(vlapic), vlapic_pt_cb,
654 &vlapic->timer_last_update);
655 vlapic->timer_last_update = vlapic->pt.last_plt_gtime;
657 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
658 "bus cycle is %uns, "
659 "initial count %lu, period %"PRIu64"ns",
660 APIC_BUS_CYCLE_NS, val, period);
661 }
662 break;
664 case APIC_TDCR:
665 vlapic_set_tdcr(vlapic, val & 0xb);
666 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "timer divisor is 0x%x",
667 vlapic->hw.timer_divisor);
668 break;
670 default:
671 gdprintk(XENLOG_DEBUG,
672 "Local APIC Write to read-only register 0x%x\n", offset);
673 break;
674 }
675 }
677 static int vlapic_range(struct vcpu *v, unsigned long addr)
678 {
679 struct vlapic *vlapic = vcpu_vlapic(v);
680 unsigned long offset = addr - vlapic_base_address(vlapic);
681 return (!vlapic_hw_disabled(vlapic) && (offset < PAGE_SIZE));
682 }
684 struct hvm_mmio_handler vlapic_mmio_handler = {
685 .check_handler = vlapic_range,
686 .read_handler = vlapic_read,
687 .write_handler = vlapic_write
688 };
690 void vlapic_msr_set(struct vlapic *vlapic, uint64_t value)
691 {
692 if ( (vlapic->hw.apic_base_msr ^ value) & MSR_IA32_APICBASE_ENABLE )
693 {
694 if ( value & MSR_IA32_APICBASE_ENABLE )
695 {
696 vlapic_reset(vlapic);
697 vlapic->hw.disabled &= ~VLAPIC_HW_DISABLED;
698 }
699 else
700 {
701 vlapic->hw.disabled |= VLAPIC_HW_DISABLED;
702 }
703 }
705 vlapic->hw.apic_base_msr = value;
707 vmx_vlapic_msr_changed(vlapic_vcpu(vlapic));
709 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
710 "apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr);
711 }
713 int vlapic_accept_pic_intr(struct vcpu *v)
714 {
715 struct vlapic *vlapic = vcpu_vlapic(v);
716 uint32_t lvt0 = vlapic_get_reg(vlapic, APIC_LVT0);
718 /*
719 * Only CPU0 is wired to the 8259A. INTA cycles occur if LINT0 is set up
720 * accept ExtInts, or if the LAPIC is disabled (so LINT0 behaves as INTR).
721 */
722 return ((v->vcpu_id == 0) &&
723 (((lvt0 & (APIC_MODE_MASK|APIC_LVT_MASKED)) == APIC_DM_EXTINT) ||
724 vlapic_hw_disabled(vlapic)));
725 }
727 int vlapic_has_pending_irq(struct vcpu *v)
728 {
729 struct vlapic *vlapic = vcpu_vlapic(v);
730 int irr, isr;
732 if ( !vlapic_enabled(vlapic) )
733 return -1;
735 irr = vlapic_find_highest_irr(vlapic);
736 if ( irr == -1 )
737 return -1;
739 isr = vlapic_find_highest_isr(vlapic);
740 isr = (isr != -1) ? isr : 0;
741 if ( (isr & 0xf0) >= (irr & 0xf0) )
742 return -1;
744 return irr;
745 }
747 int vlapic_ack_pending_irq(struct vcpu *v, int vector)
748 {
749 struct vlapic *vlapic = vcpu_vlapic(v);
751 vlapic_set_vector(vector, &vlapic->regs->data[APIC_ISR]);
752 vlapic_clear_irr(vector, vlapic);
754 return 1;
755 }
757 /* Reset the VLPAIC back to its power-on/reset state. */
758 void vlapic_reset(struct vlapic *vlapic)
759 {
760 struct vcpu *v = vlapic_vcpu(vlapic);
761 int i;
763 vlapic_set_reg(vlapic, APIC_ID, (v->vcpu_id * 2) << 24);
764 vlapic_set_reg(vlapic, APIC_LVR, VLAPIC_VERSION);
766 for ( i = 0; i < 8; i++ )
767 {
768 vlapic_set_reg(vlapic, APIC_IRR + 0x10 * i, 0);
769 vlapic_set_reg(vlapic, APIC_ISR + 0x10 * i, 0);
770 vlapic_set_reg(vlapic, APIC_TMR + 0x10 * i, 0);
771 }
772 vlapic_set_reg(vlapic, APIC_ICR, 0);
773 vlapic_set_reg(vlapic, APIC_ICR2, 0);
774 vlapic_set_reg(vlapic, APIC_LDR, 0);
775 vlapic_set_reg(vlapic, APIC_TASKPRI, 0);
776 vlapic_set_reg(vlapic, APIC_TMICT, 0);
777 vlapic_set_reg(vlapic, APIC_TMCCT, 0);
778 vlapic_set_tdcr(vlapic, 0);
780 vlapic_set_reg(vlapic, APIC_DFR, 0xffffffffU);
782 for ( i = 0; i < VLAPIC_LVT_NUM; i++ )
783 vlapic_set_reg(vlapic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
785 vlapic_set_reg(vlapic, APIC_SPIV, 0xff);
786 vlapic->hw.disabled |= VLAPIC_SW_DISABLED;
787 }
789 #ifdef HVM_DEBUG_SUSPEND
790 static void lapic_info(struct vlapic *s)
791 {
792 printk("*****lapic state:*****\n");
793 printk("lapic 0x%"PRIx64".\n", s->hw.apic_base_msr);
794 printk("lapic 0x%x.\n", s->hw.disabled);
795 printk("lapic 0x%x.\n", s->hw.timer_divisor);
796 }
797 #else
798 static void lapic_info(struct vlapic *s)
799 {
800 }
801 #endif
803 /* rearm the actimer if needed, after a HVM restore */
804 static void lapic_rearm(struct vlapic *s)
805 {
806 unsigned long tmict;
808 tmict = vlapic_get_reg(s, APIC_TMICT);
809 if ( tmict > 0 )
810 {
811 uint64_t period = (uint64_t)APIC_BUS_CYCLE_NS *
812 (uint32_t)tmict * s->hw.timer_divisor;
813 uint32_t lvtt = vlapic_get_reg(s, APIC_LVTT);
815 s->pt.irq = lvtt & APIC_VECTOR_MASK;
816 create_periodic_time(vlapic_vcpu(s), &s->pt, period, s->pt.irq,
817 !vlapic_lvtt_period(s), vlapic_pt_cb,
818 &s->timer_last_update);
819 s->timer_last_update = s->pt.last_plt_gtime;
821 printk("lapic_load to rearm the actimer:"
822 "bus cycle is %uns, "
823 "saved tmict count %lu, period %"PRIu64"ns, irq=%"PRIu8"\n",
824 APIC_BUS_CYCLE_NS, tmict, period, s->pt.irq);
825 }
827 lapic_info(s);
828 }
830 static int lapic_save_hidden(struct domain *d, hvm_domain_context_t *h)
831 {
832 struct vcpu *v;
833 struct vlapic *s;
835 for_each_vcpu(d, v)
836 {
837 s = vcpu_vlapic(v);
838 lapic_info(s);
840 if ( hvm_save_entry(LAPIC, v->vcpu_id, h, &s->hw) != 0 )
841 return 1;
842 }
843 return 0;
844 }
846 static int lapic_save_regs(struct domain *d, hvm_domain_context_t *h)
847 {
848 struct vcpu *v;
849 struct vlapic *s;
851 for_each_vcpu(d, v)
852 {
853 s = vcpu_vlapic(v);
854 if ( hvm_save_entry(LAPIC_REGS, v->vcpu_id, h, s->regs) != 0 )
855 return 1;
856 }
857 return 0;
858 }
860 static int lapic_load_hidden(struct domain *d, hvm_domain_context_t *h)
861 {
862 uint16_t vcpuid;
863 struct vcpu *v;
864 struct vlapic *s;
866 /* Which vlapic to load? */
867 vcpuid = hvm_load_instance(h);
868 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
869 {
870 gdprintk(XENLOG_ERR, "HVM restore: domain has no vlapic %u\n", vcpuid);
871 return -EINVAL;
872 }
873 s = vcpu_vlapic(v);
875 if ( hvm_load_entry(LAPIC, h, &s->hw) != 0 )
876 return -EINVAL;
878 lapic_info(s);
880 vmx_vlapic_msr_changed(v);
882 return 0;
883 }
885 static int lapic_load_regs(struct domain *d, hvm_domain_context_t *h)
886 {
887 uint16_t vcpuid;
888 struct vcpu *v;
889 struct vlapic *s;
891 /* Which vlapic to load? */
892 vcpuid = hvm_load_instance(h);
893 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
894 {
895 gdprintk(XENLOG_ERR, "HVM restore: domain has no vlapic %u\n", vcpuid);
896 return -EINVAL;
897 }
898 s = vcpu_vlapic(v);
900 if ( hvm_load_entry(LAPIC_REGS, h, s->regs) != 0 )
901 return -EINVAL;
903 lapic_rearm(s);
904 return 0;
905 }
907 HVM_REGISTER_SAVE_RESTORE(LAPIC, lapic_save_hidden, lapic_load_hidden,
908 1, HVMSR_PER_VCPU);
909 HVM_REGISTER_SAVE_RESTORE(LAPIC_REGS, lapic_save_regs, lapic_load_regs,
910 1, HVMSR_PER_VCPU);
912 int vlapic_init(struct vcpu *v)
913 {
914 struct vlapic *vlapic = vcpu_vlapic(v);
915 unsigned int memflags = 0;
917 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "%d", v->vcpu_id);
919 vlapic->pt.source = PTSRC_lapic;
921 #ifdef __i386__
922 /* 32-bit VMX may be limited to 32-bit physical addresses. */
923 if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
924 memflags = MEMF_bits(32);
925 #endif
927 vlapic->regs_page = alloc_domheap_pages(NULL, 0, memflags);
928 if ( vlapic->regs_page == NULL )
929 {
930 dprintk(XENLOG_ERR, "alloc vlapic regs error: %d/%d\n",
931 v->domain->domain_id, v->vcpu_id);
932 return -ENOMEM;
933 }
935 vlapic->regs = map_domain_page_global(page_to_mfn(vlapic->regs_page));
936 if ( vlapic->regs == NULL )
937 {
938 dprintk(XENLOG_ERR, "map vlapic regs error: %d/%d\n",
939 v->domain->domain_id, v->vcpu_id);
940 return -ENOMEM;
941 }
943 clear_page(vlapic->regs);
945 vlapic_reset(vlapic);
947 vlapic->hw.apic_base_msr = (MSR_IA32_APICBASE_ENABLE |
948 APIC_DEFAULT_PHYS_BASE);
949 if ( v->vcpu_id == 0 )
950 vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP;
952 return 0;
953 }
955 void vlapic_destroy(struct vcpu *v)
956 {
957 struct vlapic *vlapic = vcpu_vlapic(v);
959 destroy_periodic_time(&vlapic->pt);
960 unmap_domain_page_global(vlapic->regs);
961 free_domheap_page(vlapic->regs_page);
962 }