ia64/xen-unstable

view xen/include/asm-ia64/vmx_phy_mode.h @ 18501:3d96f88fb220

[IA64] fix INIT injection.

xm trigger command sometimes causes an unexpected domain panic.
There are several symptoms:
* Guest nested fault (INIT handler runs with vpsr.cpl != 0)
* Interrupt when IC=0
* Unexpected virtual <--> physical mode transition

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
Signed-off-by: Kazuhiro Suzuki <kaz@jp.fujitsu.com>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Thu Sep 18 17:54:15 2008 +0900 (2008-09-18)
parents ef290f39ae6b
children
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * vmx_phy_mode.h:
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 */
21 #ifndef _PHY_MODE_H_
22 #define _PHY_MODE_H_
24 /*
25 * Guest Physical Mode is emulated by GVMM, which is actually running
26 * in virtual mode.
27 *
28 * For all combinations of (it,dt,rt), only three were taken into
29 * account:
30 * (0,0,0): some firmware and kernel start code execute in this mode;
31 * (1,1,1): most kernel C code execute in this mode;
32 * (1,0,1): some low level TLB miss handler code execute in this mode;
33 * Till now, no other kind of combinations were found.
34 *
35 * Because all physical addresses fall into two categories:
36 * 0x0xxxxxxxxxxxxxxx, which is cacheable, and 0x8xxxxxxxxxxxxxxx, which
37 * is uncacheable. These two kinds of addresses reside in region 0 and 4
38 * of the virtual mode. Therefore, we load two different Region IDs
39 * (A, B) into RR0 and RR4, respectively, when guest is entering phsical
40 * mode. These two RIDs are totally different from the RIDs used in
41 * virtual mode. So, the aliasness between physical addresses and virtual
42 * addresses can be disambiguated by different RIDs.
43 *
44 * RID A and B are stolen from the cpu ulm region id. In linux, each
45 * process is allocated 8 RIDs:
46 * mmu_context << 3 + 0
47 * mmu_context << 3 + 1
48 * mmu_context << 3 + 2
49 * mmu_context << 3 + 3
50 * mmu_context << 3 + 4
51 * mmu_context << 3 + 5
52 * mmu_context << 3 + 6
53 * mmu_context << 3 + 7
54 * Because all processes share region 5~7, the last 3 are left untouched.
55 * So, we stolen "mmu_context << 3 + 5" and "mmu_context << 3 + 6" from
56 * ulm and use them as RID A and RID B.
57 *
58 * When guest is running in (1,0,1) mode, the instructions been accessed
59 * reside in region 5~7, not in region 0 or 4. So, instruction can be
60 * accessed in virtual mode without interferring physical data access.
61 *
62 * When dt!=rt, it is rarely to perform "load/store" and "RSE" operation
63 * at the same time. No need to consider such a case. We consider (0,1)
64 * as (0,0).
65 *
66 */
69 #ifndef __ASSEMBLY__
71 #include <asm/vmx_vcpu.h>
72 #include <asm/regionreg.h>
73 #include <asm/gcc_intrin.h>
74 #include <asm/pgtable.h>
76 #define PHY_PAGE_WB (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_WB|_PAGE_AR_RWX)
78 extern void physical_mode_init(VCPU *);
79 extern void switch_to_physical_rid(VCPU *);
80 extern void switch_to_virtual_rid(VCPU *vcpu);
81 extern void switch_mm_mode(VCPU *vcpu, IA64_PSR old_psr, IA64_PSR new_psr);
82 extern void switch_mm_mode_fast(VCPU *vcpu, IA64_PSR old_psr, IA64_PSR new_psr);
83 extern void check_mm_mode_switch(VCPU *vcpu, IA64_PSR old_psr, IA64_PSR new_psr);
84 extern void prepare_if_physical_mode(VCPU *vcpu);
85 extern void recover_if_physical_mode(VCPU *vcpu);
86 extern void vmx_init_all_rr(VCPU *vcpu);
87 extern void vmx_load_all_rr(VCPU *vcpu);
88 extern void physical_tlb_miss(VCPU *vcpu, u64 vadr, int type);
90 #define VMX_MMU_MODE(v) ((v)->arch.arch_vmx.mmu_mode)
91 #define is_virtual_mode(v) (VMX_MMU_MODE(v) == VMX_MMU_VIRTUAL)
93 #endif /* __ASSEMBLY__ */
95 #define VMX_MMU_VIRTUAL 0 /* Full virtual mode: it=dt=1 */
96 #define VMX_MMU_PHY_D 1 /* Half physical: it=1,dt=0 */
97 #define VMX_MMU_PHY_DT 3 /* Full physical mode: it=0,dt=0 */
99 #define PAL_INIT_ENTRY 0x80000000ffffffa0
101 #endif /* _PHY_MODE_H_ */