ia64/xen-unstable

view tools/misc/p4perf.h @ 1820:3d4f8eb89670

bitkeeper revision 1.1106.1.2 (40faa780dekT3E5arFwcbQDu1MbX6g)

Cleaned up Xen's instruction emulator.
author kaf24@scramble.cl.cam.ac.uk
date Sun Jul 18 16:38:24 2004 +0000 (2004-07-18)
parents 399bb8faf92a
children
line source
1 /*
2 * For P6 use PERFCTR1 (0 used for APIC NMI watchdog). Must setup after
3 * APIC NMI watchdog setup. Note that if this previous setup doesn't happen
4 * we still must enable both counters.
5 *
6 * P4 Xeon with Hyperthreading has counters per physical package which can
7 * count events from either logical CPU. However, in many cases more than
8 * ECSR and CCCR/counter can be used to count the same event. For instr or
9 * uops retired, use either ESCR0/IQ_CCCR0 ESCR1/IQ_CCCR2.
10 *
11 * USE CONFIG_MPENTIUM4_HT for a P4 Xeon with hyperthreading.
12 *
13 * Note that the counters may be initialised on each logical processor
14 * which will cause each physical processor to be initialised twice. This
15 * should not cause a problem.
16 */
18 #ifndef P4PERF_H
19 #define P4PERF_H
21 #ifdef __KERNEL__
22 #include <asm/msr.h>
23 #endif
25 /*****************************************************************************
26 * Performance counter configuration. *
27 *****************************************************************************/
29 #ifndef P6_EVNTSEL_OS
30 # define P6_EVNTSEL_OS (1 << 17)
31 # define P6_EVNTSEL_USR (1 << 16)
32 # define P6_EVNTSEL_E (1 << 18)
33 # define P6_EVNTSEL_EN (1 << 22)
34 #endif
35 #define P6_PERF_INST_RETIRED 0xc0
36 #define P6_PERF_UOPS_RETIRED 0xc2
38 #define P4_ESCR_USR (1 << 2)
39 #define P4_ESCR_OS (1 << 3)
40 #define P4_ESCR_T0_USR (1 << 2) /* First logical CPU */
41 #define P4_ESCR_T0_OS (1 << 3)
42 #define P4_ESCR_T1_USR (1 << 0) /* Second logical CPU */
43 #define P4_ESCR_T1_OS (1 << 1)
44 #define P4_ESCR_TE (1 << 4)
45 #define P4_ESCR_THREADS(t) (t)
46 #define P4_ESCR_TV(tag) (tag << 5)
47 #define P4_ESCR_EVNTSEL(e) (e << 25)
48 #define P4_ESCR_EVNTMASK(e) (e << 9)
50 #define P4_ESCR_EVNTSEL_FRONT_END 0x08
51 #define P4_ESCR_EVNTSEL_EXECUTION 0x0c
52 #define P4_ESCR_EVNTSEL_REPLAY 0x09
53 #define P4_ESCR_EVNTSEL_INSTR_RETIRED 0x02
54 #define P4_ESCR_EVNTSEL_UOPS_RETIRED 0x01
55 #define P4_ESCR_EVNTSEL_UOP_TYPE 0x02
56 #define P4_ESCR_EVNTSEL_RET_MBR_TYPE 0x05
57 //#define P4_ESCR_EVNTSEL_RET_MBR_TYPE 0x04
59 #define P4_ESCR_EVNTMASK_FE_NBOGUS 0x01
60 #define P4_ESCR_EVNTMASK_FE_BOGUS 0x02
62 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS0 0x01
63 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS1 0x02
64 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS2 0x04
65 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS3 0x08
66 #define P4_ESCR_EVNTMASK_EXEC_BOGUS0 0x10
67 #define P4_ESCR_EVNTMASK_EXEC_BOGUS1 0x20
68 #define P4_ESCR_EVNTMASK_EXEC_BOGUS2 0x40
69 #define P4_ESCR_EVNTMASK_EXEC_BOGUS3 0x80
71 #define P4_ESCR_EVNTMASK_REPLAY_NBOGUS 0x01
72 #define P4_ESCR_EVNTMASK_REPLAY_BOGUS 0x02
74 #define P4_ESCR_EVNTMASK_IRET_NB_NTAG 0x01
75 #define P4_ESCR_EVNTMASK_IRET_NB_TAG 0x02
76 #define P4_ESCR_EVNTMASK_IRET_B_NTAG 0x04
77 #define P4_ESCR_EVNTMASK_IRET_B_TAG 0x08
79 #define P4_ESCR_EVNTMASK_URET_NBOGUS 0x01
80 #define P4_ESCR_EVNTMASK_URET_BOGUS 0x02
82 #define P4_ESCR_EVNTMASK_UOP_LOADS 0x02
83 #define P4_ESCR_EVNTMASK_UOP_STORES 0x04
85 #define P4_ESCR_EVNTMASK_RMBRT_COND 0x02
86 #define P4_ESCR_EVNTMASK_RMBRT_CALL 0x04
87 #define P4_ESCR_EVNTMASK_RMBRT_RETURN 0x08
88 #define P4_ESCR_EVNTMASK_RMBRT_INDIR 0x10
90 #define P4_ESCR_EVNTMASK_RBRT_COND 0x02
91 #define P4_ESCR_EVNTMASK_RBRT_CALL 0x04
92 #define P4_ESCR_EVNTMASK_RBRT_RETURN 0x08
93 #define P4_ESCR_EVNTMASK_RBRT_INDIR 0x10
95 //#define P4_ESCR_EVNTMASK_INSTR_RETIRED 0x01 /* Non bogus, not tagged */
96 //#define P4_ESCR_EVNTMASK_UOPS_RETIRED 0x01 /* Non bogus */
98 #define P4_CCCR_OVF (1 << 31)
99 #define P4_CCCR_CASCADE (1 << 30)
100 #define P4_CCCR_FORCE_OVF (1 << 25)
101 #define P4_CCCR_EDGE (1 << 24)
102 #define P4_CCCR_COMPLEMENT (1 << 19)
103 #define P4_CCCR_COMPARE (1 << 18)
104 #define P4_CCCR_THRESHOLD(t) (t << 20)
105 #define P4_CCCR_ENABLE (1 << 12)
106 #define P4_CCCR_ESCR(escr) (escr << 13)
107 #define P4_CCCR_ACTIVE_THREAD(t) (t << 16) /* Set to 11 */
108 #define P4_CCCR_OVF_PMI_T0 (1 << 26)
109 #define P4_CCCR_OVF_PMI_T1 (1 << 27)
110 #define P4_CCCR_RESERVED (3 << 16)
111 #define P4_CCCR_OVF_PMI (1 << 26)
113 // BPU
114 #define MSR_P4_BPU_COUNTER0 0x300
115 #define MSR_P4_BPU_COUNTER1 0x301
116 #define MSR_P4_BPU_CCCR0 0x360
117 #define MSR_P4_BPU_CCCR1 0x361
119 #define MSR_P4_BPU_COUNTER2 0x302
120 #define MSR_P4_BPU_COUNTER3 0x303
121 #define MSR_P4_BPU_CCCR2 0x362
122 #define MSR_P4_BPU_CCCR3 0x363
124 #define MSR_P4_BSU_ESCR0 0x3a0
125 #define MSR_P4_FSB_ESCR0 0x3a2
126 #define MSR_P4_MOB_ESCR0 0x3aa
127 #define MSR_P4_PMH_ESCR0 0x3ac
128 #define MSR_P4_BPU_ESCR0 0x3b2
129 #define MSR_P4_IS_ESCR0 0x3b4
130 #define MSR_P4_ITLB_ESCR0 0x3b6
131 #define MSR_P4_IX_ESCR0 0x3c8
133 #define P4_BSU_ESCR0_NUMBER 7
134 #define P4_FSB_ESCR0_NUMBER 6
135 #define P4_MOB_ESCR0_NUMBER 2
136 #define P4_PMH_ESCR0_NUMBER 4
137 #define P4_BPU_ESCR0_NUMBER 0
138 #define P4_IS_ESCR0_NUMBER 1
139 #define P4_ITLB_ESCR0_NUMBER 3
140 #define P4_IX_ESCR0_NUMBER 5
142 #define MSR_P4_BSU_ESCR1 0x3a1
143 #define MSR_P4_FSB_ESCR1 0x3a3
144 #define MSR_P4_MOB_ESCR1 0x3ab
145 #define MSR_P4_PMH_ESCR1 0x3ad
146 #define MSR_P4_BPU_ESCR1 0x3b3
147 #define MSR_P4_IS_ESCR1 0x3b5
148 #define MSR_P4_ITLB_ESCR1 0x3b7
149 #define MSR_P4_IX_ESCR1 0x3c9
151 #define P4_BSU_ESCR1_NUMBER 7
152 #define P4_FSB_ESCR1_NUMBER 6
153 #define P4_MOB_ESCR1_NUMBER 2
154 #define P4_PMH_ESCR1_NUMBER 4
155 #define P4_BPU_ESCR1_NUMBER 0
156 #define P4_IS_ESCR1_NUMBER 1
157 #define P4_ITLB_ESCR1_NUMBER 3
158 #define P4_IX_ESCR1_NUMBER 5
160 // MS
161 #define MSR_P4_MS_COUNTER0 0x304
162 #define MSR_P4_MS_COUNTER1 0x305
163 #define MSR_P4_MS_CCCR0 0x364
164 #define MSR_P4_MS_CCCR1 0x365
166 #define MSR_P4_MS_COUNTER2 0x306
167 #define MSR_P4_MS_COUNTER3 0x307
168 #define MSR_P4_MS_CCCR2 0x366
169 #define MSR_P4_MS_CCCR3 0x367
171 #define MSR_P4_MS_ESCR0 0x3c0
172 #define MSR_P4_TBPU_ESCR0 0x3c2
173 #define MSR_P4_TC_ESCR0 0x3c4
175 #define P4_MS_ESCR0_NUMBER 0
176 #define P4_TBPU_ESCR0_NUMBER 2
177 #define P4_TC_ESCR0_NUMBER 1
179 #define MSR_P4_MS_ESCR1 0x3c1
180 #define MSR_P4_TBPU_ESCR1 0x3c3
181 #define MSR_P4_TC_ESCR1 0x3c5
183 #define P4_MS_ESCR1_NUMBER 0
184 #define P4_TBPU_ESCR1_NUMBER 2
185 #define P4_TC_ESCR1_NUMBER 1
187 // FLAME
188 #define MSR_P4_FLAME_COUNTER0 0x308
189 #define MSR_P4_FLAME_COUNTER1 0x309
190 #define MSR_P4_FLAME_CCCR0 0x368
191 #define MSR_P4_FLAME_CCCR1 0x369
193 #define MSR_P4_FLAME_COUNTER2 0x30a
194 #define MSR_P4_FLAME_COUNTER3 0x30b
195 #define MSR_P4_FLAME_CCCR2 0x36a
196 #define MSR_P4_FLAME_CCCR3 0x36b
198 #define MSR_P4_FIRM_ESCR0 0x3a4
199 #define MSR_P4_FLAME_ESCR0 0x3a6
200 #define MSR_P4_DAC_ESCR0 0x3a8
201 #define MSR_P4_SAAT_ESCR0 0x3ae
202 #define MSR_P4_U2L_ESCR0 0x3b0
204 #define P4_FIRM_ESCR0_NUMBER 1
205 #define P4_FLAME_ESCR0_NUMBER 0
206 #define P4_DAC_ESCR0_NUMBER 5
207 #define P4_SAAT_ESCR0_NUMBER 2
208 #define P4_U2L_ESCR0_NUMBER 3
210 #define MSR_P4_FIRM_ESCR1 0x3a5
211 #define MSR_P4_FLAME_ESCR1 0x3a7
212 #define MSR_P4_DAC_ESCR1 0x3a9
213 #define MSR_P4_SAAT_ESCR1 0x3af
214 #define MSR_P4_U2L_ESCR1 0x3b1
216 #define P4_FIRM_ESCR1_NUMBER 1
217 #define P4_FLAME_ESCR1_NUMBER 0
218 #define P4_DAC_ESCR1_NUMBER 5
219 #define P4_SAAT_ESCR1_NUMBER 2
220 #define P4_U2L_ESCR1_NUMBER 3
222 // IQ
223 #define MSR_P4_IQ_COUNTER0 0x30c
224 #define MSR_P4_IQ_COUNTER1 0x30d
225 #define MSR_P4_IQ_CCCR0 0x36c
226 #define MSR_P4_IQ_CCCR1 0x36d
228 #define MSR_P4_IQ_COUNTER2 0x30e
229 #define MSR_P4_IQ_COUNTER3 0x30f
230 #define MSR_P4_IQ_CCCR2 0x36e
231 #define MSR_P4_IQ_CCCR3 0x36f
233 #define MSR_P4_IQ_COUNTER4 0x310
234 #define MSR_P4_IQ_COUNTER5 0x311
235 #define MSR_P4_IQ_CCCR4 0x370
236 #define MSR_P4_IQ_CCCR5 0x371
238 #define MSR_P4_CRU_ESCR0 0x3b8
239 #define MSR_P4_CRU_ESCR2 0x3cc
240 #define MSR_P4_CRU_ESCR4 0x3e0
241 #define MSR_P4_IQ_ESCR0 0x3ba
242 #define MSR_P4_RAT_ESCR0 0x3bc
243 #define MSR_P4_SSU_ESCR0 0x3be
244 #define MSR_P4_ALF_ESCR0 0x3ca
246 #define P4_CRU_ESCR0_NUMBER 4
247 #define P4_CRU_ESCR2_NUMBER 5
248 #define P4_CRU_ESCR4_NUMBER 6
249 #define P4_IQ_ESCR0_NUMBER 0
250 #define P4_RAT_ESCR0_NUMBER 2
251 #define P4_SSU_ESCR0_NUMBER 3
252 #define P4_ALF_ESCR0_NUMBER 1
254 #define MSR_P4_CRU_ESCR1 0x3b9
255 #define MSR_P4_CRU_ESCR3 0x3cd
256 #define MSR_P4_CRU_ESCR5 0x3e1
257 #define MSR_P4_IQ_ESCR1 0x3bb
258 #define MSR_P4_RAT_ESCR1 0x3bd
259 #define MSR_P4_ALF_ESCR1 0x3cb
261 #define P4_CRU_ESCR1_NUMBER 4
262 #define P4_CRU_ESCR3_NUMBER 5
263 #define P4_CRU_ESCR5_NUMBER 6
264 #define P4_IQ_ESCR1_NUMBER 0
265 #define P4_RAT_ESCR1_NUMBER 2
266 #define P4_ALF_ESCR1_NUMBER 1
268 #define P4_BPU_COUNTER0_NUMBER 0
269 #define P4_BPU_COUNTER1_NUMBER 1
270 #define P4_BPU_COUNTER2_NUMBER 2
271 #define P4_BPU_COUNTER3_NUMBER 3
273 #define P4_MS_COUNTER0_NUMBER 4
274 #define P4_MS_COUNTER1_NUMBER 5
275 #define P4_MS_COUNTER2_NUMBER 6
276 #define P4_MS_COUNTER3_NUMBER 7
278 #define P4_FLAME_COUNTER0_NUMBER 8
279 #define P4_FLAME_COUNTER1_NUMBER 9
280 #define P4_FLAME_COUNTER2_NUMBER 10
281 #define P4_FLAME_COUNTER3_NUMBER 11
283 #define P4_IQ_COUNTER0_NUMBER 12
284 #define P4_IQ_COUNTER1_NUMBER 13
285 #define P4_IQ_COUNTER2_NUMBER 14
286 #define P4_IQ_COUNTER3_NUMBER 15
287 #define P4_IQ_COUNTER4_NUMBER 16
288 #define P4_IQ_COUNTER5_NUMBER 17
290 /* PEBS
291 */
292 #define MSR_P4_PEBS_ENABLE 0x3F1
293 #define MSR_P4_PEBS_MATRIX_VERT 0x3F2
295 #define P4_PEBS_ENABLE_MY_THR (1 << 25)
296 #define P4_PEBS_ENABLE_OTH_THR (1 << 26)
297 #define P4_PEBS_ENABLE (1 << 24)
298 #define P4_PEBS_BIT0 (1 << 0)
299 #define P4_PEBS_BIT1 (1 << 1)
300 #define P4_PEBS_BIT2 (1 << 2)
302 #define P4_PEBS_MATRIX_VERT_BIT0 (1 << 0)
303 #define P4_PEBS_MATRIX_VERT_BIT1 (1 << 1)
304 #define P4_PEBS_MATRIX_VERT_BIT2 (1 << 2)
306 /* Replay tagging.
307 */
308 #define P4_REPLAY_TAGGING_PEBS_L1LMR P4_PEBS_BIT0
309 #define P4_REPLAY_TAGGING_PEBS_L2LMR P4_PEBS_BIT1
310 #define P4_REPLAY_TAGGING_PEBS_DTLMR P4_PEBS_BIT2
311 #define P4_REPLAY_TAGGING_PEBS_DTSMR P4_PEBS_BIT2
312 #define P4_REPLAY_TAGGING_PEBS_DTAMR P4_PEBS_BIT2
314 #define P4_REPLAY_TAGGING_VERT_L1LMR P4_PEBS_MATRIX_VERT_BIT0
315 #define P4_REPLAY_TAGGING_VERT_L2LMR P4_PEBS_MATRIX_VERT_BIT0
316 #define P4_REPLAY_TAGGING_VERT_DTLMR P4_PEBS_MATRIX_VERT_BIT0
317 #define P4_REPLAY_TAGGING_VERT_DTSMR P4_PEBS_MATRIX_VERT_BIT1
318 #define P4_REPLAY_TAGGING_VERT_DTAMR P4_PEBS_MATRIX_VERT_BIT0 | P4_PEBS_MATRIX_VERT_BIT1
323 /*****************************************************************************
324 * *
325 *****************************************************************************/
327 // x87_FP_uop
328 #define EVENT_SEL_x87_FP_uop 0x04
329 #define EVENT_MASK_x87_FP_uop_ALL (1 << 15)
331 // execution event (at retirement)
332 #define EVENT_SEL_execution_event 0x0C
334 // scalar_SP_uop
335 #define EVENT_SEL_scalar_SP_uop 0x0a
336 #define EVENT_MASK_scalar_SP_uop_ALL (1 << 15)
338 // scalar_DP_uop
339 #define EVENT_SEL_scalar_DP_uop 0x0e
340 #define EVENT_MASK_scalar_DP_uop_ALL (1 << 15)
342 // Instruction retired
343 #define EVENT_SEL_instr_retired 0x02
344 #define EVENT_MASK_instr_retired_ALL 0x0f
346 // uOps retired
347 #define EVENT_SEL_uops_retired 0x01
348 #define EVENT_MASK_uops_retired_ALL 0x03
350 // L1 misses retired
351 #define EVENT_SEL_replay_event 0x09
352 #define EVENT_MASK_replay_event_ALL 0x03
354 // Trace cache
355 #define EVENT_SEL_BPU_fetch_request 0x03
356 #define EVENT_MASK_BPU_fetch_request_TCMISS 0x01
358 // Bus activity
359 #define EVENT_SEL_FSB_data_activity 0x17
360 #define EVENT_MASK_FSB_data_activity_DRDY_DRV 0x01
361 #define EVENT_MASK_FSB_data_activity_DRDY_OWN 0x02
362 #define EVENT_MASK_FSB_data_activity_DRDY_OOTHER 0x04
363 #define EVENT_MASK_FSB_data_activity_DBSY_DRV 0x08
364 #define EVENT_MASK_FSB_data_activity_DBSY_OWN 0x10
365 #define EVENT_MASK_FSB_data_activity_DBSY_OOTHER 0x20
367 // Cache L2
368 #define EVENT_SEL_BSQ_cache_reference 0x0c
369 #define EVENT_MASK_BSQ_cache_reference_RD_L2_HITS 0x001
370 #define EVENT_MASK_BSQ_cache_reference_RD_L2_HITE 0x002
371 #define EVENT_MASK_BSQ_cache_reference_RD_L2_HITM 0x004
373 #define EVENT_MASK_BSQ_cache_reference_RD_L3_HITS 0x008
374 #define EVENT_MASK_BSQ_cache_reference_RD_L3_HITE 0x010
375 #define EVENT_MASK_BSQ_cache_reference_RD_L3_HITM 0x020
377 #define EVENT_MASK_BSQ_cache_reference_RD_L2_MISS 0x100
378 #define EVENT_MASK_BSQ_cache_reference_RD_L3_MISS 0x200
379 #define EVENT_MASK_BSQ_cache_reference_WR_L2_MISS 0x400
381 /*****************************************************************************
382 * *
383 *****************************************************************************/
386 /* The following turn configuration macros into 1/0 to allow code to be
387 * selected using if(MPENTIUM4_HT) rather then #ifdef (to avoid stale code).
388 * We rely on the compiler to optimise out unreachable code,
389 */
390 #ifdef CONFIG_MPENTIUM4_HT
391 # define MPENTIUM4_HT 1
392 #else
393 # define MPENTIUM4_HT 0
394 #endif
396 #ifdef CONFIG_MPENTIUMIII
397 # define MPENTIUMIII 1
398 #else
399 # define MPENTIUMIII 0
400 #endif
402 #ifdef CONFIG_MPENTIUM4
403 # define MPENTIUM4 1
404 #else
405 # define MPENTIUM4 0
406 #endif
408 /*****************************************************************************
409 * MSR access macros *
410 *****************************************************************************/
412 /* rpcc: get full 64-bit Pentium TSC value
413 */
414 static __inline__ unsigned long long int rpcc(void)
415 {
416 unsigned int __h, __l;
417 __asm__ __volatile__ ("rdtsc" :"=a" (__l), "=d" (__h));
418 return (((unsigned long long)__h) << 32) + __l;
419 }
421 /*****************************************************************************
422 * Functions. *
423 *****************************************************************************/
425 #ifdef __KERNEL__
426 static inline void smt_sched_setup(void)
427 {
428 if (MPENTIUMIII) {
429 unsigned int evntsel, x;
431 /* Make sure counters enabled. */
432 rdmsr(MSR_P6_EVNTSEL0, evntsel, x);
433 evntsel |= P6_EVNTSEL_EN;
434 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
436 evntsel =
437 P6_PERF_INST_RETIRED |
438 P6_EVNTSEL_OS |
439 P6_EVNTSEL_USR |
440 P6_EVNTSEL_E;
441 wrmsr(MSR_P6_EVNTSEL1, evntsel, 0);
442 }
444 if(MPENTIUM4) {
445 unsigned int x;
447 /* Program the ESCR */
448 x = P4_ESCR_USR |
449 P4_ESCR_OS |
450 P4_ESCR_EVNTSEL(P4_ESCR_EVNTSEL_INSTR_RETIRED) |
451 P4_ESCR_EVNTMASK(P4_ESCR_EVNTMASK_IRET_NB_NTAG);
452 wrmsr(MSR_P4_CRU_ESCR0, x, 0);
454 /* Program the CCCR */
455 if (MPENTIUM4_HT) {
456 x = P4_CCCR_ENABLE |
457 P4_CCCR_ESCR(P4_CRU_ESCR0_NUMBER) |
458 P4_CCCR_ACTIVE_THREAD(3);
459 }
460 else {
461 x = P4_CCCR_ENABLE |
462 P4_CCCR_ESCR(P4_CRU_ESCR0_NUMBER) |
463 P4_CCCR_RESERVED;
464 }
465 wrmsr(MSR_P4_IQ_CCCR0, x, 0);
467 if (MPENTIUM4_HT) {
469 /* Program the second ESCR */
470 x = P4_ESCR_T1_USR |
471 P4_ESCR_T1_OS |
472 P4_ESCR_EVNTSEL(P4_ESCR_EVNTSEL_INSTR_RETIRED) |
473 P4_ESCR_EVNTMASK(P4_ESCR_EVNTMASK_IRET_NB_NTAG);
474 wrmsr(MSR_P4_CRU_ESCR1, x, 0);
476 /* Program the second CCCR */
477 x = P4_CCCR_ENABLE |
478 P4_CCCR_ESCR(P4_CRU_ESCR1_NUMBER) |
479 P4_CCCR_ACTIVE_THREAD(3);
480 wrmsr(MSR_P4_IQ_CCCR2, x, 0);
481 }
482 }
484 if (!MPENTIUMIII && !MPENTIUM4) {
485 printk("WARNING: Not setting up IPC performance counters.\n");
486 } else {
487 printk("Setting up IPC performance counters.\n");
488 }
489 }
491 #ifdef CONFIG_MPENTIUMIII
492 # define MY_MSR_COUNTER MSR_P6_PERFCTR1
493 #endif
494 #ifdef CONFIG_MPENTIUM4
495 # define MY_MSR_COUNTER MSR_P4_IQ_COUNTER0
496 #endif
497 #ifndef MY_MSR_COUNTER
498 # define MY_MSR_COUNTER 0 /* Never used but ensures compilation */
499 #endif
500 #define MY_MSR_COUNTER0 MSR_P4_IQ_COUNTER0
501 #define MY_MSR_COUNTER1 MSR_P4_IQ_COUNTER2
503 # define smt_sched_start_sample(task) \
504 { \
505 unsigned int l, h; \
506 \
507 if (MPENTIUM4_HT) { \
508 unsigned int msr = \
509 (task->processor & 1)?MY_MSR_COUNTER1:MY_MSR_COUNTER0; \
510 rdmsr(msr, l, h); \
511 } \
512 else { \
513 rdmsr(MY_MSR_COUNTER, l, h); \
514 } \
515 task->ipc_sample_start_count_lo = l; \
516 task->ipc_sample_start_count_hi = h; \
517 rdtsc(l, h); \
518 task->ipc_sample_start_cycle_lo = l; \
519 task->ipc_sample_start_cycle_hi = h; \
520 }
522 # define smt_sched_stop_sample(task) \
523 { \
524 if (task->ipc_sample_start_cycle_hi != 0) \
525 { \
526 unsigned int cl, ch, tl, th; \
527 unsigned int c, t; \
528 \
529 if (MPENTIUM4_HT) { \
530 unsigned int msr = \
531 (task->processor & 1)?MY_MSR_COUNTER1:MY_MSR_COUNTER0; \
532 rdmsr(msr, cl, ch); \
533 } \
534 else { \
535 rdmsr(MY_MSR_COUNTER, cl, ch); \
536 } \
537 \
538 rdtsc(tl, th); \
539 \
540 c = cl - task->ipc_sample_start_count_lo; \
541 t = tl - task->ipc_sample_start_cycle_lo; \
542 task->ipc_average = IPC_AVERAGE(task->ipc_average, \
543 ((double)c)/((double)t)); \
544 task->ipc_sample_start_cycle_hi = 0; \
545 \
546 } \
547 else \
548 task->ipc_average = 0.0; \
549 \
550 }
552 // task->ipc_sample_latest =
553 // (unsigned int)(1000.0*((double)c)/((double)t));
554 #endif /* __KERNEL__ */
557 #endif /* P4PERF_H */
559 /* End of $RCSfile$ */