ia64/xen-unstable

view extras/mini-os/h/os.h @ 795:3a4eb84cc402

bitkeeper revision 1.485 (3f81b19fL5Y4lVlRaEpJI9r_IZlDcw)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno/users/rn212/xeno.mini
into labyrinth.cl.cam.ac.uk:/auto/anfs/scratch/labyrinth/iap10/xeno-clone/xeno.bk
author iap10@labyrinth.cl.cam.ac.uk
date Mon Oct 06 18:17:03 2003 +0000 (2003-10-06)
parents 34473973889b
children 71f9c171157e
line source
1 /******************************************************************************
2 * os.h
3 *
4 * random collection of macros and definition
5 */
7 #ifndef _OS_H_
8 #define _OS_H_
11 #define NULL 0
13 /*
14 * These are the segment descriptors provided for us by the hypervisor.
15 * For now, these are hardwired -- guest OSes cannot update the GDT
16 * or LDT.
17 *
18 * It shouldn't be hard to support descriptor-table frobbing -- let me
19 * know if the BSD or XP ports require flexibility here.
20 */
23 /*
24 * these are also defined in hypervisor-if.h but can't be pulled in as
25 * they are used in start of day assembly. Need to clean up the .h files
26 * a bit more...
27 */
29 #ifndef FLAT_RING1_CS
30 #define FLAT_RING1_CS 0x0819
31 #define FLAT_RING1_DS 0x0821
32 #define FLAT_RING3_CS 0x082b
33 #define FLAT_RING3_DS 0x0833
34 #endif
36 #define __KERNEL_CS FLAT_RING1_CS
37 #define __KERNEL_DS FLAT_RING1_DS
39 /* Everything below this point is not included by assembler (.S) files. */
40 #ifndef __ASSEMBLY__
42 #include <types.h>
43 #include <hypervisor-ifs/hypervisor-if.h>
46 /* this struct defines the way the registers are stored on the
47 stack during an exception or interrupt. */
48 struct pt_regs {
49 long ebx;
50 long ecx;
51 long edx;
52 long esi;
53 long edi;
54 long ebp;
55 long eax;
56 int xds;
57 int xes;
58 long orig_eax;
59 long eip;
60 int xcs;
61 long eflags;
62 long esp;
63 int xss;
64 };
66 /* some function prototypes */
67 void trap_init(void);
68 void dump_regs(struct pt_regs *regs);
71 /*
72 * STI/CLI equivalents. These basically set and clear the virtual
73 * event_enable flag in teh shared_info structure. Note that when
74 * the enable bit is set, there may be pending events to be handled.
75 * We may therefore call into do_hypervisor_callback() directly.
76 */
77 #define unlikely(x) __builtin_expect((x),0)
78 #define __save_flags(x) \
79 do { \
80 (x) = test_bit(EVENTS_MASTER_ENABLE_BIT, \
81 &HYPERVISOR_shared_info->events_mask); \
82 barrier(); \
83 } while (0)
85 #define __restore_flags(x) \
86 do { \
87 shared_info_t *_shared = HYPERVISOR_shared_info; \
88 if (x) set_bit(EVENTS_MASTER_ENABLE_BIT, &_shared->events_mask); \
89 barrier(); \
90 if ( unlikely(_shared->events) && (x) ) do_hypervisor_callback(NULL); \
91 } while (0)
93 #define __cli() \
94 do { \
95 clear_bit(EVENTS_MASTER_ENABLE_BIT, &HYPERVISOR_shared_info->events_mask);\
96 barrier(); \
97 } while (0)
99 #define __sti() \
100 do { \
101 shared_info_t *_shared = HYPERVISOR_shared_info; \
102 set_bit(EVENTS_MASTER_ENABLE_BIT, &_shared->events_mask); \
103 barrier(); \
104 if ( unlikely(_shared->events) ) do_hypervisor_callback(NULL); \
105 } while (0)
106 #define cli() __cli()
107 #define sti() __sti()
108 #define save_flags(x) __save_flags(x)
109 #define restore_flags(x) __restore_flags(x)
110 #define save_and_cli(x) __save_and_cli(x)
111 #define save_and_sti(x) __save_and_sti(x)
115 /* This is a barrier for the compiler only, NOT the processor! */
116 #define barrier() __asm__ __volatile__("": : :"memory")
118 #define LOCK_PREFIX ""
119 #define LOCK ""
120 #define ADDR (*(volatile long *) addr)
121 /*
122 * Make sure gcc doesn't try to be clever and move things around
123 * on us. We need to use _exactly_ the address the user gave us,
124 * not some alias that contains the same information.
125 */
126 typedef struct { volatile int counter; } atomic_t;
129 /*
130 * This XCHG macro is straight from Linux. It is gross.
131 */
132 #define xchg(ptr,v) \
133 ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
134 struct __xchg_dummy { unsigned long a[100]; };
135 #define __xg(x) ((struct __xchg_dummy *)(x))
136 static inline unsigned long __xchg(unsigned long x, volatile void * ptr,
137 int size)
138 {
139 switch (size) {
140 case 1:
141 __asm__ __volatile__("xchgb %b0,%1"
142 :"=q" (x)
143 :"m" (*__xg(ptr)), "0" (x)
144 :"memory");
145 break;
146 case 2:
147 __asm__ __volatile__("xchgw %w0,%1"
148 :"=r" (x)
149 :"m" (*__xg(ptr)), "0" (x)
150 :"memory");
151 break;
152 case 4:
153 __asm__ __volatile__("xchgl %0,%1"
154 :"=r" (x)
155 :"m" (*__xg(ptr)), "0" (x)
156 :"memory");
157 break;
158 }
159 return x;
160 }
162 /**
163 * test_and_clear_bit - Clear a bit and return its old value
164 * @nr: Bit to set
165 * @addr: Address to count from
166 *
167 * This operation is atomic and cannot be reordered.
168 * It also implies a memory barrier.
169 */
170 static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
171 {
172 int oldbit;
174 __asm__ __volatile__( LOCK_PREFIX
175 "btrl %2,%1\n\tsbbl %0,%0"
176 :"=r" (oldbit),"=m" (ADDR)
177 :"Ir" (nr) : "memory");
178 return oldbit;
179 }
181 static __inline__ int constant_test_bit(int nr, const volatile void * addr)
182 {
183 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
184 }
186 static __inline__ int variable_test_bit(int nr, volatile void * addr)
187 {
188 int oldbit;
190 __asm__ __volatile__(
191 "btl %2,%1\n\tsbbl %0,%0"
192 :"=r" (oldbit)
193 :"m" (ADDR),"Ir" (nr));
194 return oldbit;
195 }
197 #define test_bit(nr,addr) \
198 (__builtin_constant_p(nr) ? \
199 constant_test_bit((nr),(addr)) : \
200 variable_test_bit((nr),(addr)))
203 /**
204 * set_bit - Atomically set a bit in memory
205 * @nr: the bit to set
206 * @addr: the address to start counting from
207 *
208 * This function is atomic and may not be reordered. See __set_bit()
209 * if you do not require the atomic guarantees.
210 * Note that @nr may be almost arbitrarily large; this function is not
211 * restricted to acting on a single-word quantity.
212 */
213 static __inline__ void set_bit(int nr, volatile void * addr)
214 {
215 __asm__ __volatile__( LOCK_PREFIX
216 "btsl %1,%0"
217 :"=m" (ADDR)
218 :"Ir" (nr));
219 }
221 /**
222 * clear_bit - Clears a bit in memory
223 * @nr: Bit to clear
224 * @addr: Address to start counting from
225 *
226 * clear_bit() is atomic and may not be reordered. However, it does
227 * not contain a memory barrier, so if it is used for locking purposes,
228 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
229 * in order to ensure changes are visible on other processors.
230 */
231 static __inline__ void clear_bit(int nr, volatile void * addr)
232 {
233 __asm__ __volatile__( LOCK_PREFIX
234 "btrl %1,%0"
235 :"=m" (ADDR)
236 :"Ir" (nr));
237 }
239 /**
240 * atomic_inc - increment atomic variable
241 * @v: pointer of type atomic_t
242 *
243 * Atomically increments @v by 1. Note that the guaranteed
244 * useful range of an atomic_t is only 24 bits.
245 */
246 static __inline__ void atomic_inc(atomic_t *v)
247 {
248 __asm__ __volatile__(
249 LOCK "incl %0"
250 :"=m" (v->counter)
251 :"m" (v->counter));
252 }
255 /* useful hypervisor macros */
257 struct desc_struct {
258 unsigned long a,b;
259 };
260 extern struct desc_struct default_ldt[];
262 #define asmlinkage __attribute__((regparm(0)))
264 /*
265 * some random linux macros
266 */
268 #define rdtscll(val) \
269 __asm__ __volatile__("rdtsc" : "=A" (val))
272 #endif /* !__ASSEMBLY__ */
274 #endif /* _OS_H_ */