ia64/xen-unstable

view tools/misc/xen_cpuperf.c @ 815:399bb8faf92a

bitkeeper revision 1.502 (3f87080cq7U6Gnq5kREYk6dTNB2VJA)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno/BK/xeno.bk
into labyrinth.cl.cam.ac.uk:/auto/anfs/scratch/labyrinth/iap10/xeno-clone/xeno.bk
author iap10@labyrinth.cl.cam.ac.uk
date Fri Oct 10 19:27:08 2003 +0000 (2003-10-10)
parents b487e696e814
children 0cd58ce5a503
line source
1 /*
2 * User mode program to prod MSR values through /proc/perfcntr
3 *
4 *
5 * $Id$
6 *
7 * $Log$
8 */
10 #include <sys/types.h>
11 #include <sched.h>
12 #include <error.h>
13 #include <stdio.h>
14 #include <unistd.h>
15 #include <stdlib.h>
16 #include <string.h>
18 #include "p4perf.h"
19 #include "hypervisor-ifs/dom0_ops.h"
20 #include "dom0_defs.h"
22 void dom0_wrmsr( int cpu_mask, int msr, unsigned int low, unsigned int high )
23 {
24 dom0_op_t op;
25 op.cmd = DOM0_MSR;
26 op.u.msr.write = 1;
27 op.u.msr.msr = msr;
28 op.u.msr.cpu_mask = cpu_mask;
29 op.u.msr.in1 = low;
30 op.u.msr.in2 = high;
31 do_dom0_op(&op);
32 }
34 unsigned long long dom0_rdmsr( int cpu_mask, int msr )
35 {
36 dom0_op_t op;
37 op.cmd = DOM0_MSR;
38 op.u.msr.write = 0;
39 op.u.msr.msr = msr;
40 op.u.msr.cpu_mask = cpu_mask;
41 do_dom0_op(&op);
42 return (((unsigned long long)op.u.msr.out2)<<32) | op.u.msr.out1 ;
43 }
45 struct macros {
46 char *name;
47 unsigned long msr_addr;
48 int number;
49 };
51 struct macros msr[] = {
52 {"BPU_COUNTER0", 0x300, 0},
53 {"BPU_COUNTER1", 0x301, 1},
54 {"BPU_COUNTER2", 0x302, 2},
55 {"BPU_COUNTER3", 0x303, 3},
56 {"MS_COUNTER0", 0x304, 4},
57 {"MS_COUNTER1", 0x305, 5},
58 {"MS_COUNTER2", 0x306, 6},
59 {"MS_COUNTER3", 0x307, 7},
60 {"FLAME_COUNTER0", 0x308, 8},
61 {"FLAME_COUNTER1", 0x309, 9},
62 {"FLAME_COUNTER2", 0x30a, 10},
63 {"FLAME_COUNTER3", 0x30b, 11},
64 {"IQ_COUNTER0", 0x30c, 12},
65 {"IQ_COUNTER1", 0x30d, 13},
66 {"IQ_COUNTER2", 0x30e, 14},
67 {"IQ_COUNTER3", 0x30f, 15},
68 {"IQ_COUNTER4", 0x310, 16},
69 {"IQ_COUNTER5", 0x311, 17},
70 {"BPU_CCCR0", 0x360, 0},
71 {"BPU_CCCR1", 0x361, 1},
72 {"BPU_CCCR2", 0x362, 2},
73 {"BPU_CCCR3", 0x363, 3},
74 {"MS_CCCR0", 0x364, 4},
75 {"MS_CCCR1", 0x365, 5},
76 {"MS_CCCR2", 0x366, 6},
77 {"MS_CCCR3", 0x367, 7},
78 {"FLAME_CCCR0", 0x368, 8},
79 {"FLAME_CCCR1", 0x369, 9},
80 {"FLAME_CCCR2", 0x36a, 10},
81 {"FLAME_CCCR3", 0x36b, 11},
82 {"IQ_CCCR0", 0x36c, 12},
83 {"IQ_CCCR1", 0x36d, 13},
84 {"IQ_CCCR2", 0x36e, 14},
85 {"IQ_CCCR3", 0x36f, 15},
86 {"IQ_CCCR4", 0x370, 16},
87 {"IQ_CCCR5", 0x371, 17},
88 {"BSU_ESCR0", 0x3a0, 7},
89 {"BSU_ESCR1", 0x3a1, 7},
90 {"FSB_ESCR0", 0x3a2, 6},
91 {"FSB_ESCR1", 0x3a3, 6},
92 {"MOB_ESCR0", 0x3aa, 2},
93 {"MOB_ESCR1", 0x3ab, 2},
94 {"PMH_ESCR0", 0x3ac, 4},
95 {"PMH_ESCR1", 0x3ad, 4},
96 {"BPU_ESCR0", 0x3b2, 0},
97 {"BPU_ESCR1", 0x3b3, 0},
98 {"IS_ESCR0", 0x3b4, 1},
99 {"IS_ESCR1", 0x3b5, 1},
100 {"ITLB_ESCR0", 0x3b6, 3},
101 {"ITLB_ESCR1", 0x3b7, 3},
102 {"IX_ESCR0", 0x3c8, 5},
103 {"IX_ESCR1", 0x3c9, 5},
104 {"MS_ESCR0", 0x3c0, 0},
105 {"MS_ESCR1", 0x3c1, 0},
106 {"TBPU_ESCR0", 0x3c2, 2},
107 {"TBPU_ESCR1", 0x3c3, 2},
108 {"TC_ESCR0", 0x3c4, 1},
109 {"TC_ESCR1", 0x3c5, 1},
110 {"FIRM_ESCR0", 0x3a4, 1},
111 {"FIRM_ESCR1", 0x3a5, 1},
112 {"FLAME_ESCR0", 0x3a6, 0},
113 {"FLAME_ESCR1", 0x3a7, 0},
114 {"DAC_ESCR0", 0x3a8, 5},
115 {"DAC_ESCR1", 0x3a9, 5},
116 {"SAAT_ESCR0", 0x3ae, 2},
117 {"SAAT_ESCR1", 0x3af, 2},
118 {"U2L_ESCR0", 0x3b0, 3},
119 {"U2L_ESCR1", 0x3b1, 3},
120 {"CRU_ESCR0", 0x3b8, 4},
121 {"CRU_ESCR1", 0x3b9, 4},
122 {"CRU_ESCR2", 0x3cc, 5},
123 {"CRU_ESCR3", 0x3cd, 5},
124 {"CRU_ESCR4", 0x3e0, 6},
125 {"CRU_ESCR5", 0x3e1, 6},
126 {"IQ_ESCR0", 0x3ba, 0},
127 {"IQ_ESCR1", 0x3bb, 0},
128 {"RAT_ESCR0", 0x3bc, 2},
129 {"RAT_ESCR1", 0x3bd, 2},
130 {"SSU_ESCR0", 0x3be, 3},
131 {"SSU_ESCR1", 0x3bf, 3},
132 {"ALF_ESCR0", 0x3ca, 1},
133 {"ALF_ESCR1", 0x3cb, 1},
134 {"PEBS_ENABLE", 0x3f1, 0},
135 {"PEBS_MATRIX_VERT", 0x3f2, 0},
136 {NULL, 0, 0}
137 };
139 struct macros *lookup_macro(char *str)
140 {
141 struct macros *m;
143 m = msr;
144 while (m->name) {
145 if (strcmp(m->name, str) == 0)
146 return m;
147 m++;
148 }
149 return NULL;
150 }
152 int main(int argc, char **argv)
153 {
154 int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
155 unsigned int cpu_mask = 1;
156 struct macros *escr = NULL, *cccr = NULL;
157 unsigned long escr_val, cccr_val;
158 int debug = 0;
159 unsigned long pebs = 0, pebs_vert = 0;
160 int pebs_x = 0, pebs_vert_x = 0;
161 int read = 0;
163 while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:r")) != -1) {
164 switch((char)c) {
165 case 'P':
166 pebs |= 1 << atoi(optarg);
167 pebs_x = 1;
168 break;
169 case 'V':
170 pebs_vert |= 1 << atoi(optarg);
171 pebs_vert_x = 1;
172 break;
173 case 'd':
174 debug = 1;
175 break;
176 case 'c':
177 {
178 int cpu = atoi(optarg);
179 cpu_mask = (cpu == -1)?(~0):(1<<cpu);
180 break;
181 }
182 case 't': // ESCR thread bits
183 t = atoi(optarg);
184 break;
185 case 'e': // eventsel
186 es = atoi(optarg);
187 break;
188 case 'm': // eventmask
189 em = atoi(optarg);
190 break;
191 case 'T': // tag value
192 tv = atoi(optarg);
193 te = 1;
194 break;
195 case 'E':
196 escr = lookup_macro(optarg);
197 if (!escr) {
198 fprintf(stderr, "Macro '%s' not found.\n", optarg);
199 exit(1);
200 }
201 break;
202 case 'C':
203 cccr = lookup_macro(optarg);
204 if (!cccr) {
205 fprintf(stderr, "Macro '%s' not found.\n", optarg);
206 exit(1);
207 }
208 break;
209 case 'r':
210 read = 1;
211 break;
212 }
213 }
215 if (read) {
216 while((cpu_mask&1)) {
217 int i;
218 for (i=0x300;i<0x312;i++)
219 {
220 printf("%010llx ",dom0_rdmsr( cpu_mask, i ) );
221 }
222 printf("\n");
223 cpu_mask>>=1;
224 }
225 exit(1);
226 }
228 if (!escr) {
229 fprintf(stderr, "Need an ESCR.\n");
230 exit(1);
231 }
232 if (!cccr) {
233 fprintf(stderr, "Need a counter number.\n");
234 exit(1);
235 }
237 escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
238 P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
239 cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
240 P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
242 if (debug) {
243 fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
244 fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
245 cccr->msr_addr, cccr_val, cccr->number);
246 if (pebs_x)
247 fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
248 MSR_P4_PEBS_ENABLE, pebs);
249 if (pebs_vert_x)
250 fprintf(stderr, "PMV 0x%x <= 0x%08lx\n",
251 MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
252 }
254 dom0_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
255 dom0_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
257 if (pebs_x)
258 dom0_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
260 if (pebs_vert_x)
261 dom0_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
263 return 0;
264 }