ia64/xen-unstable

view xen/include/public/arch-ia64.h @ 9887:3726c0afc5af

Allow for arch specific virq definitions.

Signed-off-by Kevin Tian <kevin.tian@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Fri Apr 28 14:27:38 2006 +0100 (2006-04-28)
parents dfdc32a9814f
children 5d9eb92e63e2 e99987843336
line source
1 /******************************************************************************
2 * arch-ia64/hypervisor-if.h
3 *
4 * Guest OS interface to IA64 Xen.
5 */
7 #ifndef __HYPERVISOR_IF_IA64_H__
8 #define __HYPERVISOR_IF_IA64_H__
10 #define __DEFINE_XEN_GUEST_HANDLE(name, type) \
11 typedef struct { type *p; } __guest_handle_ ## name
13 #define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name)
14 #define XEN_GUEST_HANDLE(name) __guest_handle_ ## name
15 #define set_xen_guest_handle(hnd, val) do { (hnd).p = val; } while (0)
16 #ifdef __XEN_TOOLS__
17 #define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0)
18 #endif
20 #ifndef __ASSEMBLY__
21 /* Guest handles for primitive C types. */
22 __DEFINE_XEN_GUEST_HANDLE(uchar, unsigned char);
23 __DEFINE_XEN_GUEST_HANDLE(uint, unsigned int);
24 __DEFINE_XEN_GUEST_HANDLE(ulong, unsigned long);
25 DEFINE_XEN_GUEST_HANDLE(char);
26 DEFINE_XEN_GUEST_HANDLE(int);
27 DEFINE_XEN_GUEST_HANDLE(long);
28 DEFINE_XEN_GUEST_HANDLE(void);
29 #endif
31 /* Arch specific VIRQs definition */
32 #define VIRQ_ITC VIRQ_ARCH_0 /* V. Virtual itc timer */
34 /* Maximum number of virtual CPUs in multi-processor guests. */
35 /* WARNING: before changing this, check that shared_info fits on a page */
36 #define MAX_VIRT_CPUS 64
38 #ifndef __ASSEMBLY__
40 #define MAX_NR_SECTION 32 /* at most 32 memory holes */
41 typedef struct {
42 unsigned long start; /* start of memory hole */
43 unsigned long end; /* end of memory hole */
44 } mm_section_t;
46 typedef struct {
47 unsigned long mfn : 56;
48 unsigned long type: 8;
49 } pmt_entry_t;
51 #define GPFN_MEM (0UL << 56) /* Guest pfn is normal mem */
52 #define GPFN_FRAME_BUFFER (1UL << 56) /* VGA framebuffer */
53 #define GPFN_LOW_MMIO (2UL << 56) /* Low MMIO range */
54 #define GPFN_PIB (3UL << 56) /* PIB base */
55 #define GPFN_IOSAPIC (4UL << 56) /* IOSAPIC base */
56 #define GPFN_LEGACY_IO (5UL << 56) /* Legacy I/O base */
57 #define GPFN_GFW (6UL << 56) /* Guest Firmware */
58 #define GPFN_HIGH_MMIO (7UL << 56) /* High MMIO range */
60 #define GPFN_IO_MASK (7UL << 56) /* Guest pfn is I/O type */
61 #define GPFN_INV_MASK (31UL << 59) /* Guest pfn is invalid */
63 #define INVALID_MFN (~0UL)
65 #define MEM_G (1UL << 30)
66 #define MEM_M (1UL << 20)
68 #define MMIO_START (3 * MEM_G)
69 #define MMIO_SIZE (512 * MEM_M)
71 #define VGA_IO_START 0xA0000UL
72 #define VGA_IO_SIZE 0x20000
74 #define LEGACY_IO_START (MMIO_START + MMIO_SIZE)
75 #define LEGACY_IO_SIZE (64*MEM_M)
77 #define IO_PAGE_START (LEGACY_IO_START + LEGACY_IO_SIZE)
78 #define IO_PAGE_SIZE PAGE_SIZE
80 #define STORE_PAGE_START (IO_PAGE_START + IO_PAGE_SIZE)
81 #define STORE_PAGE_SIZE PAGE_SIZE
83 #define IO_SAPIC_START 0xfec00000UL
84 #define IO_SAPIC_SIZE 0x100000
86 #define PIB_START 0xfee00000UL
87 #define PIB_SIZE 0x100000
89 #define GFW_START (4*MEM_G -16*MEM_M)
90 #define GFW_SIZE (16*MEM_M)
92 /*
93 * NB. This may become a 64-bit count with no shift. If this happens then the
94 * structure size will still be 8 bytes, so no other alignments will change.
95 */
96 typedef struct {
97 unsigned int tsc_bits; /* 0: 32 bits read from the CPU's TSC. */
98 unsigned int tsc_bitshift; /* 4: 'tsc_bits' uses N:N+31 of TSC. */
99 } tsc_timestamp_t; /* 8 bytes */
101 struct pt_fpreg {
102 union {
103 unsigned long bits[2];
104 long double __dummy; /* force 16-byte alignment */
105 } u;
106 };
108 typedef struct cpu_user_regs{
109 /* The following registers are saved by SAVE_MIN: */
110 unsigned long b6; /* scratch */
111 unsigned long b7; /* scratch */
113 unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
114 unsigned long ar_ssd; /* reserved for future use (scratch) */
116 unsigned long r8; /* scratch (return value register 0) */
117 unsigned long r9; /* scratch (return value register 1) */
118 unsigned long r10; /* scratch (return value register 2) */
119 unsigned long r11; /* scratch (return value register 3) */
121 unsigned long cr_ipsr; /* interrupted task's psr */
122 unsigned long cr_iip; /* interrupted task's instruction pointer */
123 unsigned long cr_ifs; /* interrupted task's function state */
125 unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
126 unsigned long ar_pfs; /* prev function state */
127 unsigned long ar_rsc; /* RSE configuration */
128 /* The following two are valid only if cr_ipsr.cpl > 0: */
129 unsigned long ar_rnat; /* RSE NaT */
130 unsigned long ar_bspstore; /* RSE bspstore */
132 unsigned long pr; /* 64 predicate registers (1 bit each) */
133 unsigned long b0; /* return pointer (bp) */
134 unsigned long loadrs; /* size of dirty partition << 16 */
136 unsigned long r1; /* the gp pointer */
137 unsigned long r12; /* interrupted task's memory stack pointer */
138 unsigned long r13; /* thread pointer */
140 unsigned long ar_fpsr; /* floating point status (preserved) */
141 unsigned long r15; /* scratch */
143 /* The remaining registers are NOT saved for system calls. */
145 unsigned long r14; /* scratch */
146 unsigned long r2; /* scratch */
147 unsigned long r3; /* scratch */
148 unsigned long r16; /* scratch */
149 unsigned long r17; /* scratch */
150 unsigned long r18; /* scratch */
151 unsigned long r19; /* scratch */
152 unsigned long r20; /* scratch */
153 unsigned long r21; /* scratch */
154 unsigned long r22; /* scratch */
155 unsigned long r23; /* scratch */
156 unsigned long r24; /* scratch */
157 unsigned long r25; /* scratch */
158 unsigned long r26; /* scratch */
159 unsigned long r27; /* scratch */
160 unsigned long r28; /* scratch */
161 unsigned long r29; /* scratch */
162 unsigned long r30; /* scratch */
163 unsigned long r31; /* scratch */
164 unsigned long ar_ccv; /* compare/exchange value (scratch) */
166 /*
167 * Floating point registers that the kernel considers scratch:
168 */
169 struct pt_fpreg f6; /* scratch */
170 struct pt_fpreg f7; /* scratch */
171 struct pt_fpreg f8; /* scratch */
172 struct pt_fpreg f9; /* scratch */
173 struct pt_fpreg f10; /* scratch */
174 struct pt_fpreg f11; /* scratch */
175 unsigned long r4; /* preserved */
176 unsigned long r5; /* preserved */
177 unsigned long r6; /* preserved */
178 unsigned long r7; /* preserved */
179 unsigned long eml_unat; /* used for emulating instruction */
180 unsigned long rfi_pfs; /* used for elulating rfi */
182 }cpu_user_regs_t;
184 typedef union {
185 unsigned long value;
186 struct {
187 int a_int:1;
188 int a_from_int_cr:1;
189 int a_to_int_cr:1;
190 int a_from_psr:1;
191 int a_from_cpuid:1;
192 int a_cover:1;
193 int a_bsw:1;
194 long reserved:57;
195 };
196 } vac_t;
198 typedef union {
199 unsigned long value;
200 struct {
201 int d_vmsw:1;
202 int d_extint:1;
203 int d_ibr_dbr:1;
204 int d_pmc:1;
205 int d_to_pmd:1;
206 int d_itm:1;
207 long reserved:58;
208 };
209 } vdc_t;
211 typedef struct {
212 vac_t vac;
213 vdc_t vdc;
214 unsigned long virt_env_vaddr;
215 unsigned long reserved1[29];
216 unsigned long vhpi;
217 unsigned long reserved2[95];
218 union {
219 unsigned long vgr[16];
220 unsigned long bank1_regs[16]; // bank1 regs (r16-r31) when bank0 active
221 };
222 union {
223 unsigned long vbgr[16];
224 unsigned long bank0_regs[16]; // bank0 regs (r16-r31) when bank1 active
225 };
226 unsigned long vnat;
227 unsigned long vbnat;
228 unsigned long vcpuid[5];
229 unsigned long reserved3[11];
230 unsigned long vpsr;
231 unsigned long vpr;
232 unsigned long reserved4[76];
233 union {
234 unsigned long vcr[128];
235 struct {
236 unsigned long dcr; // CR0
237 unsigned long itm;
238 unsigned long iva;
239 unsigned long rsv1[5];
240 unsigned long pta; // CR8
241 unsigned long rsv2[7];
242 unsigned long ipsr; // CR16
243 unsigned long isr;
244 unsigned long rsv3;
245 unsigned long iip;
246 unsigned long ifa;
247 unsigned long itir;
248 unsigned long iipa;
249 unsigned long ifs;
250 unsigned long iim; // CR24
251 unsigned long iha;
252 unsigned long rsv4[38];
253 unsigned long lid; // CR64
254 unsigned long ivr;
255 unsigned long tpr;
256 unsigned long eoi;
257 unsigned long irr[4];
258 unsigned long itv; // CR72
259 unsigned long pmv;
260 unsigned long cmcv;
261 unsigned long rsv5[5];
262 unsigned long lrr0; // CR80
263 unsigned long lrr1;
264 unsigned long rsv6[46];
265 };
266 };
267 union {
268 unsigned long reserved5[128];
269 struct {
270 unsigned long precover_ifs;
271 unsigned long unat; // not sure if this is needed until NaT arch is done
272 int interrupt_collection_enabled; // virtual psr.ic
273 /* virtual interrupt deliverable flag is evtchn_upcall_mask in
274 * shared info area now. interrupt_mask_addr is the address
275 * of evtchn_upcall_mask for current vcpu
276 */
277 unsigned long interrupt_mask_addr;
278 int pending_interruption;
279 int incomplete_regframe; // see SDM vol2 6.8
280 unsigned long reserved5_1[4];
281 int metaphysical_mode; // 1 = use metaphys mapping, 0 = use virtual
282 int banknum; // 0 or 1, which virtual register bank is active
283 unsigned long rrs[8]; // region registers
284 unsigned long krs[8]; // kernel registers
285 unsigned long pkrs[8]; // protection key registers
286 unsigned long tmp[8]; // temp registers (e.g. for hyperprivops)
287 // FIXME: tmp[8] temp'ly being used for virtual psr.pp
288 };
289 };
290 unsigned long reserved6[3456];
291 unsigned long vmm_avail[128];
292 unsigned long reserved7[4096];
293 } mapped_regs_t;
295 typedef struct {
296 mapped_regs_t *privregs;
297 int evtchn_vector;
298 } arch_vcpu_info_t;
300 typedef mapped_regs_t vpd_t;
302 typedef struct {
303 unsigned int flags;
304 unsigned long start_info_pfn;
305 } arch_shared_info_t;
307 typedef struct {
308 unsigned long start;
309 unsigned long size;
310 } arch_initrd_info_t;
312 #define IA64_COMMAND_LINE_SIZE 512
313 typedef struct vcpu_guest_context {
314 #define VGCF_FPU_VALID (1<<0)
315 #define VGCF_VMX_GUEST (1<<1)
316 #define VGCF_IN_KERNEL (1<<2)
317 unsigned long flags; /* VGCF_* flags */
318 unsigned long pt_base; /* PMT table base */
319 unsigned long share_io_pg; /* Shared page for I/O emulation */
320 unsigned long sys_pgnr; /* System pages out of domain memory */
321 unsigned long vm_assist; /* VMASST_TYPE_* bitmap, now none on IPF */
323 cpu_user_regs_t regs;
324 arch_vcpu_info_t vcpu;
325 arch_shared_info_t shared;
326 arch_initrd_info_t initrd;
327 char cmdline[IA64_COMMAND_LINE_SIZE];
328 } vcpu_guest_context_t;
329 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
331 // dom0 vp op
332 #define __HYPERVISOR_ia64_dom0vp_op 256 // XXX sufficient large
333 // TODO
334 // arch specific hypercall
335 // number conversion
336 #define IA64_DOM0VP_ioremap 0 // map io space in machine
337 // address to dom0 physical
338 // address space.
339 // currently physical
340 // assignedg address equals to
341 // machine address
342 #define IA64_DOM0VP_phystomach 1 // convert a pseudo physical
343 // page frame number
344 // to the corresponding
345 // machine page frame number.
346 // if no page is assigned,
347 // INVALID_MFN or GPFN_INV_MASK
348 // is returned depending on
349 // domain's non-vti/vti mode.
350 #define IA64_DOM0VP_machtophys 3 // convert a machine page
351 // frame number
352 // to the corresponding
353 // pseudo physical page frame
354 // number of the caller domain
355 #define IA64_DOM0VP_populate_physmap 16 // allocate machine-contigusous
356 // memory region and
357 // map it to pseudo physical
358 // address
359 #define IA64_DOM0VP_zap_physmap 17 // unmap and free pages
360 // contained in the specified
361 // pseudo physical region
362 #define IA64_DOM0VP_add_physmap 18 // assigne machine page frane
363 // to dom0's pseudo physical
364 // address space.
366 #endif /* !__ASSEMBLY__ */
368 #endif /* __HYPERVISOR_IF_IA64_H__ */
370 /*
371 * Local variables:
372 * mode: C
373 * c-set-style: "BSD"
374 * c-basic-offset: 4
375 * tab-width: 4
376 * indent-tabs-mode: nil
377 * End:
378 */