ia64/xen-unstable

view tools/ioemu/hw/i8259.c @ 6427:3428d58a85e1

merge?
author cl349@firebug.cl.cam.ac.uk
date Thu Aug 25 14:41:52 2005 +0000 (2005-08-25)
parents 4abd299ef2f6 6e899a3840b2
children b54144915ae6
line source
1 /*
2 * QEMU 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "xenctrl.h"
26 #include <io/ioreq.h>
28 /* debug PIC */
29 //#define DEBUG_PIC
31 //#define DEBUG_IRQ_LATENCY
32 #define DEBUG_IRQ_COUNT
34 extern void pit_reset_vmx_vectors();
36 typedef struct PicState {
37 uint8_t last_irr; /* edge detection */
38 uint8_t irr; /* interrupt request register */
39 uint8_t imr; /* interrupt mask register */
40 uint8_t isr; /* interrupt service register */
41 uint8_t priority_add; /* highest irq priority */
42 uint8_t irq_base;
43 uint8_t read_reg_select;
44 uint8_t poll;
45 uint8_t special_mask;
46 uint8_t init_state;
47 uint8_t auto_eoi;
48 uint8_t rotate_on_auto_eoi;
49 uint8_t special_fully_nested_mode;
50 uint8_t init4; /* true if 4 byte init */
51 uint8_t elcr; /* PIIX edge/trigger selection*/
52 uint8_t elcr_mask;
53 } PicState;
55 /* 0 is master pic, 1 is slave pic */
56 static PicState pics[2];
58 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
59 static int irq_level[16];
60 #endif
61 #ifdef DEBUG_IRQ_COUNT
62 static uint64_t irq_count[16];
63 #endif
65 /* set irq level. If an edge is detected, then the IRR is set to 1 */
66 static inline void pic_set_irq1(PicState *s, int irq, int level)
67 {
68 int mask;
69 mask = 1 << irq;
70 if (s->elcr & mask) {
71 /* level triggered */
72 if (level) {
73 s->irr |= mask;
74 s->last_irr |= mask;
75 } else {
76 s->irr &= ~mask;
77 s->last_irr &= ~mask;
78 }
79 } else {
80 /* edge triggered */
81 if (level) {
82 if ((s->last_irr & mask) == 0)
83 s->irr |= mask;
84 s->last_irr |= mask;
85 } else {
86 s->last_irr &= ~mask;
87 }
88 }
89 }
91 /* return the highest priority found in mask (highest = smallest
92 number). Return 8 if no irq */
93 static inline int get_priority(PicState *s, int mask)
94 {
95 int priority;
96 if (mask == 0)
97 return 8;
98 priority = 0;
99 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
100 priority++;
101 return priority;
102 }
104 /* return the pic wanted interrupt. return -1 if none */
105 static int pic_get_irq(PicState *s)
106 {
107 int mask, cur_priority, priority;
109 mask = s->irr & ~s->imr;
110 priority = get_priority(s, mask);
111 if (priority == 8)
112 return -1;
113 /* compute current priority. If special fully nested mode on the
114 master, the IRQ coming from the slave is not taken into account
115 for the priority computation. */
116 mask = s->isr;
117 if (s->special_fully_nested_mode && s == &pics[0])
118 mask &= ~(1 << 2);
119 cur_priority = get_priority(s, mask);
120 if (priority < cur_priority) {
121 /* higher priority found: an irq should be generated */
122 return (priority + s->priority_add) & 7;
123 } else {
124 return -1;
125 }
126 }
128 /* pic[1] is connected to pin2 of pic[0] */
129 #define CASCADE_IRQ 2
131 static void shared_page_update()
132 {
133 extern shared_iopage_t *shared_page;
134 uint8_t * pmask = (uint8_t *)&(shared_page->sp_global.pic_mask[0]);
135 int index;
137 index = pics[0].irq_base/8;
138 pmask[index] = pics[0].imr;
139 index = pics[1].irq_base/8;
141 if ( pics[0].imr & (1 << CASCADE_IRQ) ) {
142 pmask[index] = 0xff;
143 } else {
144 pmask[index] = pics[1].imr;
145 }
146 }
148 /* raise irq to CPU if necessary. must be called every time the active
149 irq may change */
150 static void pic_update_irq(void)
151 {
152 int irq2, irq;
154 /* first look at slave pic */
155 irq2 = pic_get_irq(&pics[1]);
156 if (irq2 >= 0) {
157 /* if irq request by slave pic, signal master PIC */
158 pic_set_irq1(&pics[0], 2, 1);
159 pic_set_irq1(&pics[0], 2, 0);
160 }
161 /* look at requested irq */
162 irq = pic_get_irq(&pics[0]);
163 if (irq >= 0) {
164 #if defined(DEBUG_PIC)
165 {
166 int i;
167 for(i = 0; i < 2; i++) {
168 printf("pic%d: imr=%x irr=%x padd=%d\n",
169 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
171 }
172 }
173 printf("pic: cpu_interrupt\n");
174 #endif
175 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
176 }
177 shared_page_update();
178 }
180 #ifdef DEBUG_IRQ_LATENCY
181 int64_t irq_time[16];
182 #endif
184 extern void ioapic_legacy_irq(int irq, int level);
186 void pic_set_irq(int irq, int level)
187 {
188 ioapic_legacy_irq(irq, level);
189 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
190 if (level != irq_level[irq]) {
191 #if defined(DEBUG_PIC)
192 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
193 #endif
194 irq_level[irq] = level;
195 #ifdef DEBUG_IRQ_COUNT
196 if (level == 1)
197 irq_count[irq]++;
198 #endif
199 }
200 #endif
201 #ifdef DEBUG_IRQ_LATENCY
202 if (level) {
203 irq_time[irq] = qemu_get_clock(vm_clock);
204 }
205 #endif
206 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
207 pic_update_irq();
208 }
210 /* acknowledge interrupt 'irq' */
211 static inline void pic_intack(PicState *s, int irq)
212 {
213 if (s->auto_eoi) {
214 if (s->rotate_on_auto_eoi)
215 s->priority_add = (irq + 1) & 7;
216 } else {
217 s->isr |= (1 << irq);
218 }
219 /* We don't clear a level sensitive interrupt here */
220 if (!(s->elcr & (1 << irq)))
221 s->irr &= ~(1 << irq);
222 }
224 int cpu_get_pic_interrupt(CPUState *env)
225 {
226 int irq, irq2, intno;
228 /* read the irq from the PIC */
230 irq = pic_get_irq(&pics[0]);
231 if (irq >= 0) {
232 pic_intack(&pics[0], irq);
233 if (irq == 2) {
234 irq2 = pic_get_irq(&pics[1]);
235 if (irq2 >= 0) {
236 pic_intack(&pics[1], irq2);
237 } else {
238 /* spurious IRQ on slave controller */
239 irq2 = 7;
240 }
241 intno = pics[1].irq_base + irq2;
242 irq = irq2 + 8;
243 } else {
244 intno = pics[0].irq_base + irq;
245 }
246 } else {
247 /* spurious IRQ on host controller */
248 irq = 7;
249 intno = pics[0].irq_base + irq;
250 }
251 pic_update_irq();
253 #ifdef DEBUG_IRQ_LATENCY
254 printf("IRQ%d latency=%0.3fus\n",
255 irq,
256 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
257 #endif
258 #if defined(DEBUG_PIC)
259 printf("pic_interrupt: irq=%d\n", irq);
260 #endif
261 return intno;
262 }
264 int pic_irq2vec(int irq)
265 {
266 int vector = -1;
268 if (irq >= 8 && irq <= 15) {
269 if (pics[1].irq_base != 0xFF)
270 vector = pics[1].irq_base + irq;
271 } else if (irq != 2 && irq <= 7) {
272 if (pics[0].irq_base != 0xFF)
273 vector = pics[0].irq_base + irq;
274 }
275 return vector;
276 }
278 static void pic_reset(void *opaque)
279 {
280 PicState *s = opaque;
281 int tmp;
283 tmp = s->elcr_mask;
284 memset(s, 0, sizeof(PicState));
285 s->elcr_mask = tmp;
286 shared_page_update();
287 }
289 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
290 {
291 PicState *s = opaque;
292 int priority, cmd, irq;
294 #ifdef DEBUG_PIC
295 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
296 #endif
297 addr &= 1;
298 if (addr == 0) {
299 if (val & 0x10) {
300 /* init */
301 pic_reset(s);
302 /* deassert a pending interrupt */
303 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
305 s->init_state = 1;
306 s->init4 = val & 1;
307 if (val & 0x02)
308 hw_error("single mode not supported");
309 if (val & 0x08)
310 hw_error("level sensitive irq not supported");
311 } else if (val & 0x08) {
312 if (val & 0x04)
313 s->poll = 1;
314 if (val & 0x02)
315 s->read_reg_select = val & 1;
316 if (val & 0x40)
317 s->special_mask = (val >> 5) & 1;
318 } else {
319 cmd = val >> 5;
320 switch(cmd) {
321 case 0:
322 case 4:
323 s->rotate_on_auto_eoi = cmd >> 2;
324 break;
325 case 1: /* end of interrupt */
326 case 5:
327 priority = get_priority(s, s->isr);
328 if (priority != 8) {
329 irq = (priority + s->priority_add) & 7;
330 s->isr &= ~(1 << irq);
331 if (cmd == 5)
332 s->priority_add = (irq + 1) & 7;
333 pic_update_irq();
334 }
335 break;
336 case 3:
337 irq = val & 7;
338 s->isr &= ~(1 << irq);
339 pic_update_irq();
340 break;
341 case 6:
342 s->priority_add = (val + 1) & 7;
343 pic_update_irq();
344 break;
345 case 7:
346 irq = val & 7;
347 s->isr &= ~(1 << irq);
348 s->priority_add = (irq + 1) & 7;
349 pic_update_irq();
350 break;
351 default:
352 /* no operation */
353 break;
354 }
355 }
356 } else {
357 switch(s->init_state) {
358 case 0:
359 /* normal mode */
360 s->imr = val;
361 pic_update_irq();
362 break;
363 case 1:
364 s->irq_base = val & 0xf8;
365 s->init_state = 2;
366 pit_reset_vmx_vectors();
367 break;
368 case 2:
369 if (s->init4) {
370 s->init_state = 3;
371 } else {
372 s->init_state = 0;
373 }
374 break;
375 case 3:
376 s->special_fully_nested_mode = (val >> 4) & 1;
377 s->auto_eoi = (val >> 1) & 1;
378 s->init_state = 0;
379 break;
380 }
381 }
382 }
384 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
385 {
386 int ret;
388 ret = pic_get_irq(s);
389 if (ret >= 0) {
390 if (addr1 >> 7) {
391 pics[0].isr &= ~(1 << 2);
392 pics[0].irr &= ~(1 << 2);
393 }
394 s->irr &= ~(1 << ret);
395 s->isr &= ~(1 << ret);
396 if (addr1 >> 7 || ret != 2)
397 pic_update_irq();
398 } else {
399 ret = 0x07;
400 pic_update_irq();
401 }
403 return ret;
404 }
406 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
407 {
408 PicState *s = opaque;
409 unsigned int addr;
410 int ret;
412 addr = addr1;
413 addr &= 1;
414 if (s->poll) {
415 ret = pic_poll_read(s, addr1);
416 s->poll = 0;
417 } else {
418 if (addr == 0) {
419 if (s->read_reg_select)
420 ret = s->isr;
421 else
422 ret = s->irr;
423 } else {
424 ret = s->imr;
425 }
426 }
427 #ifdef DEBUG_PIC
428 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
429 #endif
430 return ret;
431 }
433 /* memory mapped interrupt status */
434 uint32_t pic_intack_read(CPUState *env)
435 {
436 int ret;
438 ret = pic_poll_read(&pics[0], 0x00);
439 if (ret == 2)
440 ret = pic_poll_read(&pics[1], 0x80) + 8;
441 /* Prepare for ISR read */
442 pics[0].read_reg_select = 1;
444 return ret;
445 }
447 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
448 {
449 PicState *s = opaque;
450 s->elcr = val & s->elcr_mask;
451 }
453 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
454 {
455 PicState *s = opaque;
456 return s->elcr;
457 }
459 static void pic_save(QEMUFile *f, void *opaque)
460 {
461 PicState *s = opaque;
463 qemu_put_8s(f, &s->last_irr);
464 qemu_put_8s(f, &s->irr);
465 qemu_put_8s(f, &s->imr);
466 qemu_put_8s(f, &s->isr);
467 qemu_put_8s(f, &s->priority_add);
468 qemu_put_8s(f, &s->irq_base);
469 qemu_put_8s(f, &s->read_reg_select);
470 qemu_put_8s(f, &s->poll);
471 qemu_put_8s(f, &s->special_mask);
472 qemu_put_8s(f, &s->init_state);
473 qemu_put_8s(f, &s->auto_eoi);
474 qemu_put_8s(f, &s->rotate_on_auto_eoi);
475 qemu_put_8s(f, &s->special_fully_nested_mode);
476 qemu_put_8s(f, &s->init4);
477 qemu_put_8s(f, &s->elcr);
478 }
480 static int pic_load(QEMUFile *f, void *opaque, int version_id)
481 {
482 PicState *s = opaque;
484 if (version_id != 1)
485 return -EINVAL;
487 qemu_get_8s(f, &s->last_irr);
488 qemu_get_8s(f, &s->irr);
489 qemu_get_8s(f, &s->imr);
490 qemu_get_8s(f, &s->isr);
491 qemu_get_8s(f, &s->priority_add);
492 qemu_get_8s(f, &s->irq_base);
493 qemu_get_8s(f, &s->read_reg_select);
494 qemu_get_8s(f, &s->poll);
495 qemu_get_8s(f, &s->special_mask);
496 qemu_get_8s(f, &s->init_state);
497 qemu_get_8s(f, &s->auto_eoi);
498 qemu_get_8s(f, &s->rotate_on_auto_eoi);
499 qemu_get_8s(f, &s->special_fully_nested_mode);
500 qemu_get_8s(f, &s->init4);
501 qemu_get_8s(f, &s->elcr);
502 return 0;
503 }
505 /* XXX: add generic master/slave system */
506 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
507 {
508 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
509 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
510 if (elcr_addr >= 0) {
511 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
512 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
513 }
514 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
515 qemu_register_reset(pic_reset, s);
516 }
518 void pic_info(void)
519 {
520 int i;
521 PicState *s;
523 for(i=0;i<2;i++) {
524 s = &pics[i];
525 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
526 i, s->irr, s->imr, s->isr, s->priority_add,
527 s->irq_base, s->read_reg_select, s->elcr,
528 s->special_fully_nested_mode);
529 }
530 }
532 void irq_info(void)
533 {
534 #ifndef DEBUG_IRQ_COUNT
535 term_printf("irq statistic code not compiled.\n");
536 #else
537 int i;
538 int64_t count;
540 term_printf("IRQ statistics:\n");
541 for (i = 0; i < 16; i++) {
542 count = irq_count[i];
543 if (count > 0)
544 term_printf("%2d: %lld\n", i, count);
545 }
546 #endif
547 }
549 void pic_init(void)
550 {
551 pic_init1(0x20, 0x4d0, &pics[0]);
552 pic_init1(0xa0, 0x4d1, &pics[1]);
553 pics[0].elcr_mask = 0xf8;
554 pics[1].elcr_mask = 0xde;
555 pics[0].irq_base = 0xff;
556 pics[0].irq_base = 0xff;
557 }