ia64/xen-unstable

view xen/arch/x86/x86_emulate/x86_emulate.c @ 17719:30bf34f5a414

x86_emulate: Check single-step status at instruction start rather than end.

This fixes booting of FreeDOS with HIMEM.SYS enabled.

Signed-off-by: Trolle Selander <trolle.selander@eu.citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Sat May 24 08:54:59 2008 +0100 (2008-05-24)
parents 6271ba3bb4b6
children 049a42108c65
line source
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005-2007 Keir Fraser
7 * Copyright (c) 2005-2007 XenSource Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
24 /* Operand sizes: 8-bit operands or specified/overridden size. */
25 #define ByteOp (1<<0) /* 8-bit operands. */
26 /* Destination operand type. */
27 #define DstBitBase (0<<1) /* Memory operand, bit string. */
28 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
29 #define DstReg (2<<1) /* Register operand. */
30 #define DstMem (3<<1) /* Memory operand. */
31 #define DstMask (3<<1)
32 /* Source operand type. */
33 #define SrcNone (0<<3) /* No source operand. */
34 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
35 #define SrcReg (1<<3) /* Register operand. */
36 #define SrcMem (2<<3) /* Memory operand. */
37 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
38 #define SrcImm (4<<3) /* Immediate operand. */
39 #define SrcImmByte (5<<3) /* 8-bit sign-extended immediate operand. */
40 #define SrcMask (7<<3)
41 /* Generic ModRM decode. */
42 #define ModRM (1<<6)
43 /* Destination is only written; never read. */
44 #define Mov (1<<7)
46 static uint8_t opcode_table[256] = {
47 /* 0x00 - 0x07 */
48 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
49 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
50 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
51 /* 0x08 - 0x0F */
52 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
53 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
54 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, 0,
55 /* 0x10 - 0x17 */
56 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
57 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
58 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
59 /* 0x18 - 0x1F */
60 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
61 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
62 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
63 /* 0x20 - 0x27 */
64 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
65 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
66 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
67 /* 0x28 - 0x2F */
68 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
69 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
70 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
71 /* 0x30 - 0x37 */
72 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
73 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
74 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
75 /* 0x38 - 0x3F */
76 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
77 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
78 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
79 /* 0x40 - 0x4F */
80 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
81 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
82 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
83 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
84 /* 0x50 - 0x5F */
85 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
86 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
87 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
88 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
89 /* 0x60 - 0x67 */
90 ImplicitOps, ImplicitOps, DstReg|SrcMem|ModRM, DstReg|SrcMem16|ModRM|Mov,
91 0, 0, 0, 0,
92 /* 0x68 - 0x6F */
93 ImplicitOps|Mov, DstReg|SrcImm|ModRM|Mov,
94 ImplicitOps|Mov, DstReg|SrcImmByte|ModRM|Mov,
95 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
96 /* 0x70 - 0x77 */
97 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
98 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
99 /* 0x78 - 0x7F */
100 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
101 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
102 /* 0x80 - 0x87 */
103 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImm|ModRM,
104 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM,
105 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
106 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
107 /* 0x88 - 0x8F */
108 ByteOp|DstMem|SrcReg|ModRM|Mov, DstMem|SrcReg|ModRM|Mov,
109 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
110 DstMem|SrcReg|ModRM|Mov, DstReg|SrcNone|ModRM,
111 DstReg|SrcMem|ModRM|Mov, DstMem|SrcNone|ModRM|Mov,
112 /* 0x90 - 0x97 */
113 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
114 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
115 /* 0x98 - 0x9F */
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
118 /* 0xA0 - 0xA7 */
119 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
120 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
121 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
122 ByteOp|ImplicitOps, ImplicitOps,
123 /* 0xA8 - 0xAF */
124 ByteOp|DstReg|SrcImm, DstReg|SrcImm,
125 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
126 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
127 ByteOp|ImplicitOps, ImplicitOps,
128 /* 0xB0 - 0xB7 */
129 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
130 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
131 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
132 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
133 /* 0xB8 - 0xBF */
134 DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov,
135 DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov,
136 /* 0xC0 - 0xC7 */
137 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM,
138 ImplicitOps, ImplicitOps,
139 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
140 ByteOp|DstMem|SrcImm|ModRM|Mov, DstMem|SrcImm|ModRM|Mov,
141 /* 0xC8 - 0xCF */
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
143 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
144 /* 0xD0 - 0xD7 */
145 ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,
146 ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,
147 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
148 /* 0xD8 - 0xDF */
149 0, ImplicitOps|ModRM|Mov, 0, ImplicitOps|ModRM|Mov,
150 0, ImplicitOps|ModRM|Mov, ImplicitOps|ModRM|Mov, ImplicitOps|ModRM|Mov,
151 /* 0xE0 - 0xE7 */
152 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
153 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
154 /* 0xE8 - 0xEF */
155 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
156 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
157 /* 0xF0 - 0xF7 */
158 0, ImplicitOps, 0, 0,
159 ImplicitOps, ImplicitOps,
160 ByteOp|DstMem|SrcNone|ModRM, DstMem|SrcNone|ModRM,
161 /* 0xF8 - 0xFF */
162 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
163 ImplicitOps, ImplicitOps, ByteOp|DstMem|SrcNone|ModRM, DstMem|SrcNone|ModRM
164 };
166 static uint8_t twobyte_table[256] = {
167 /* 0x00 - 0x07 */
168 0, ImplicitOps|ModRM, 0, 0, 0, 0, ImplicitOps, 0,
169 /* 0x08 - 0x0F */
170 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps|ModRM, 0, 0,
171 /* 0x10 - 0x17 */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x18 - 0x1F */
174 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
175 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
176 /* 0x20 - 0x27 */
177 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
178 0, 0, 0, 0,
179 /* 0x28 - 0x2F */
180 0, 0, 0, 0, 0, 0, 0, 0,
181 /* 0x30 - 0x37 */
182 ImplicitOps, ImplicitOps, ImplicitOps, 0, 0, 0, 0, 0,
183 /* 0x38 - 0x3F */
184 0, 0, 0, 0, 0, 0, 0, 0,
185 /* 0x40 - 0x47 */
186 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
187 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
188 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
189 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
190 /* 0x48 - 0x4F */
191 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
192 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
193 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
194 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
195 /* 0x50 - 0x5F */
196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
197 /* 0x60 - 0x6F */
198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps|ModRM,
199 /* 0x70 - 0x7F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps|ModRM,
201 /* 0x80 - 0x87 */
202 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
203 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
204 /* 0x88 - 0x8F */
205 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
206 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
207 /* 0x90 - 0x97 */
208 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
209 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
210 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
211 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
212 /* 0x98 - 0x9F */
213 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
214 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
215 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
216 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
217 /* 0xA0 - 0xA7 */
218 ImplicitOps, ImplicitOps, ImplicitOps, DstBitBase|SrcReg|ModRM,
219 DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, 0,
220 /* 0xA8 - 0xAF */
221 ImplicitOps, ImplicitOps, 0, DstBitBase|SrcReg|ModRM,
222 DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, DstReg|SrcMem|ModRM,
223 /* 0xB0 - 0xB7 */
224 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
225 DstReg|SrcMem|ModRM|Mov, DstBitBase|SrcReg|ModRM,
226 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
227 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem16|ModRM|Mov,
228 /* 0xB8 - 0xBF */
229 0, 0, DstBitBase|SrcImmByte|ModRM, DstBitBase|SrcReg|ModRM,
230 DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
231 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem16|ModRM|Mov,
232 /* 0xC0 - 0xC7 */
233 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, 0,
234 0, 0, 0, ImplicitOps|ModRM,
235 /* 0xC8 - 0xCF */
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
237 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
238 /* 0xD0 - 0xDF */
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0xE0 - 0xEF */
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0xF0 - 0xFF */
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
244 };
246 /* Type, address-of, and value of an instruction's operand. */
247 struct operand {
248 enum { OP_REG, OP_MEM, OP_IMM, OP_NONE } type;
249 unsigned int bytes;
250 unsigned long val, orig_val;
251 union {
252 /* OP_REG: Pointer to register field. */
253 unsigned long *reg;
254 /* OP_MEM: Segment and offset. */
255 struct {
256 enum x86_segment seg;
257 unsigned long off;
258 } mem;
259 };
260 };
262 /* MSRs. */
263 #define MSR_TSC 0x10
265 /* Control register flags. */
266 #define CR0_PE (1<<0)
267 #define CR4_TSD (1<<2)
269 /* EFLAGS bit definitions. */
270 #define EFLG_VIP (1<<20)
271 #define EFLG_VIF (1<<19)
272 #define EFLG_AC (1<<18)
273 #define EFLG_VM (1<<17)
274 #define EFLG_RF (1<<16)
275 #define EFLG_NT (1<<14)
276 #define EFLG_IOPL (3<<12)
277 #define EFLG_OF (1<<11)
278 #define EFLG_DF (1<<10)
279 #define EFLG_IF (1<<9)
280 #define EFLG_TF (1<<8)
281 #define EFLG_SF (1<<7)
282 #define EFLG_ZF (1<<6)
283 #define EFLG_AF (1<<4)
284 #define EFLG_PF (1<<2)
285 #define EFLG_CF (1<<0)
287 /* Exception definitions. */
288 #define EXC_DE 0
289 #define EXC_DB 1
290 #define EXC_BP 3
291 #define EXC_OF 4
292 #define EXC_BR 5
293 #define EXC_UD 6
294 #define EXC_TS 10
295 #define EXC_NP 11
296 #define EXC_SS 12
297 #define EXC_GP 13
298 #define EXC_PF 14
299 #define EXC_MF 16
301 /*
302 * Instruction emulation:
303 * Most instructions are emulated directly via a fragment of inline assembly
304 * code. This allows us to save/restore EFLAGS and thus very easily pick up
305 * any modified flags.
306 */
308 #if defined(__x86_64__)
309 #define _LO32 "k" /* force 32-bit operand */
310 #define _STK "%%rsp" /* stack pointer */
311 #define _BYTES_PER_LONG "8"
312 #elif defined(__i386__)
313 #define _LO32 "" /* force 32-bit operand */
314 #define _STK "%%esp" /* stack pointer */
315 #define _BYTES_PER_LONG "4"
316 #endif
318 /*
319 * These EFLAGS bits are restored from saved value during emulation, and
320 * any changes are written back to the saved value after emulation.
321 */
322 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
324 /* Before executing instruction: restore necessary bits in EFLAGS. */
325 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
326 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
327 "movl %"_sav",%"_LO32 _tmp"; " \
328 "push %"_tmp"; " \
329 "push %"_tmp"; " \
330 "movl %"_msk",%"_LO32 _tmp"; " \
331 "andl %"_LO32 _tmp",("_STK"); " \
332 "pushf; " \
333 "notl %"_LO32 _tmp"; " \
334 "andl %"_LO32 _tmp",("_STK"); " \
335 "andl %"_LO32 _tmp",2*"_BYTES_PER_LONG"("_STK"); " \
336 "pop %"_tmp"; " \
337 "orl %"_LO32 _tmp",("_STK"); " \
338 "popf; " \
339 "pop %"_sav"; "
341 /* After executing instruction: write-back necessary bits in EFLAGS. */
342 #define _POST_EFLAGS(_sav, _msk, _tmp) \
343 /* _sav |= EFLAGS & _msk; */ \
344 "pushf; " \
345 "pop %"_tmp"; " \
346 "andl %"_msk",%"_LO32 _tmp"; " \
347 "orl %"_LO32 _tmp",%"_sav"; "
349 /* Raw emulation: instruction has two explicit operands. */
350 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy)\
351 do{ unsigned long _tmp; \
352 switch ( (_dst).bytes ) \
353 { \
354 case 2: \
355 asm volatile ( \
356 _PRE_EFLAGS("0","4","2") \
357 _op"w %"_wx"3,%1; " \
358 _POST_EFLAGS("0","4","2") \
359 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
360 : _wy ((_src).val), "i" (EFLAGS_MASK), \
361 "m" (_eflags), "m" ((_dst).val) ); \
362 break; \
363 case 4: \
364 asm volatile ( \
365 _PRE_EFLAGS("0","4","2") \
366 _op"l %"_lx"3,%1; " \
367 _POST_EFLAGS("0","4","2") \
368 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
369 : _ly ((_src).val), "i" (EFLAGS_MASK), \
370 "m" (_eflags), "m" ((_dst).val) ); \
371 break; \
372 case 8: \
373 __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy); \
374 break; \
375 } \
376 } while (0)
377 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)\
378 do{ unsigned long _tmp; \
379 switch ( (_dst).bytes ) \
380 { \
381 case 1: \
382 asm volatile ( \
383 _PRE_EFLAGS("0","4","2") \
384 _op"b %"_bx"3,%1; " \
385 _POST_EFLAGS("0","4","2") \
386 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
387 : _by ((_src).val), "i" (EFLAGS_MASK), \
388 "m" (_eflags), "m" ((_dst).val) ); \
389 break; \
390 default: \
391 __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy);\
392 break; \
393 } \
394 } while (0)
395 /* Source operand is byte-sized and may be restricted to just %cl. */
396 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
397 __emulate_2op(_op, _src, _dst, _eflags, \
398 "b", "c", "b", "c", "b", "c", "b", "c")
399 /* Source operand is byte, word, long or quad sized. */
400 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
401 __emulate_2op(_op, _src, _dst, _eflags, \
402 "b", "q", "w", "r", _LO32, "r", "", "r")
403 /* Source operand is word, long or quad sized. */
404 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
405 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
406 "w", "r", _LO32, "r", "", "r")
408 /* Instruction has only one explicit operand (no source operand). */
409 #define emulate_1op(_op,_dst,_eflags) \
410 do{ unsigned long _tmp; \
411 switch ( (_dst).bytes ) \
412 { \
413 case 1: \
414 asm volatile ( \
415 _PRE_EFLAGS("0","3","2") \
416 _op"b %1; " \
417 _POST_EFLAGS("0","3","2") \
418 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
419 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
420 break; \
421 case 2: \
422 asm volatile ( \
423 _PRE_EFLAGS("0","3","2") \
424 _op"w %1; " \
425 _POST_EFLAGS("0","3","2") \
426 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
427 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
428 break; \
429 case 4: \
430 asm volatile ( \
431 _PRE_EFLAGS("0","3","2") \
432 _op"l %1; " \
433 _POST_EFLAGS("0","3","2") \
434 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
435 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
436 break; \
437 case 8: \
438 __emulate_1op_8byte(_op, _dst, _eflags); \
439 break; \
440 } \
441 } while (0)
443 /* Emulate an instruction with quadword operands (x86/64 only). */
444 #if defined(__x86_64__)
445 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
446 do{ asm volatile ( \
447 _PRE_EFLAGS("0","4","2") \
448 _op"q %"_qx"3,%1; " \
449 _POST_EFLAGS("0","4","2") \
450 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
451 : _qy ((_src).val), "i" (EFLAGS_MASK), \
452 "m" (_eflags), "m" ((_dst).val) ); \
453 } while (0)
454 #define __emulate_1op_8byte(_op, _dst, _eflags) \
455 do{ asm volatile ( \
456 _PRE_EFLAGS("0","3","2") \
457 _op"q %1; " \
458 _POST_EFLAGS("0","3","2") \
459 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
460 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
461 } while (0)
462 #elif defined(__i386__)
463 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
464 #define __emulate_1op_8byte(_op, _dst, _eflags)
465 #endif /* __i386__ */
467 /* Fetch next part of the instruction being emulated. */
468 #define insn_fetch_bytes(_size) \
469 ({ unsigned long _x, _eip = _regs.eip; \
470 if ( !mode_64bit() ) _eip = (uint32_t)_eip; /* ignore upper dword */ \
471 _regs.eip += (_size); /* real hardware doesn't truncate */ \
472 generate_exception_if((uint8_t)(_regs.eip - ctxt->regs->eip) > 15, \
473 EXC_GP, 0); \
474 rc = ops->insn_fetch(x86_seg_cs, _eip, &_x, (_size), ctxt); \
475 if ( rc ) goto done; \
476 _x; \
477 })
478 #define insn_fetch_type(_type) ((_type)insn_fetch_bytes(sizeof(_type)))
480 #define truncate_word(ea, byte_width) \
481 ({ unsigned long __ea = (ea); \
482 unsigned int _width = (byte_width); \
483 ((_width == sizeof(unsigned long)) ? __ea : \
484 (__ea & ((1UL << (_width << 3)) - 1))); \
485 })
486 #define truncate_ea(ea) truncate_word((ea), ad_bytes)
488 #define mode_64bit() (def_ad_bytes == 8)
490 #define fail_if(p) \
491 do { \
492 rc = (p) ? X86EMUL_UNHANDLEABLE : X86EMUL_OKAY; \
493 if ( rc ) goto done; \
494 } while (0)
496 #define generate_exception_if(p, e, ec) \
497 ({ if ( (p) ) { \
498 fail_if(ops->inject_hw_exception == NULL); \
499 rc = ops->inject_hw_exception(e, ec, ctxt) ? : X86EMUL_EXCEPTION; \
500 goto done; \
501 } \
502 })
504 /*
505 * Given byte has even parity (even number of 1s)? SDM Vol. 1 Sec. 3.4.3.1,
506 * "Status Flags": EFLAGS.PF reflects parity of least-sig. byte of result only.
507 */
508 static int even_parity(uint8_t v)
509 {
510 asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) );
511 return v;
512 }
514 /* Update address held in a register, based on addressing mode. */
515 #define _register_address_increment(reg, inc, byte_width) \
516 do { \
517 int _inc = (inc); /* signed type ensures sign extension to long */ \
518 unsigned int _width = (byte_width); \
519 if ( _width == sizeof(unsigned long) ) \
520 (reg) += _inc; \
521 else if ( mode_64bit() ) \
522 (reg) = ((reg) + _inc) & ((1UL << (_width << 3)) - 1); \
523 else \
524 (reg) = ((reg) & ~((1UL << (_width << 3)) - 1)) | \
525 (((reg) + _inc) & ((1UL << (_width << 3)) - 1)); \
526 } while (0)
527 #define register_address_increment(reg, inc) \
528 _register_address_increment((reg), (inc), ad_bytes)
530 #define sp_pre_dec(dec) ({ \
531 _register_address_increment(_regs.esp, -(dec), ctxt->sp_size/8); \
532 truncate_word(_regs.esp, ctxt->sp_size/8); \
533 })
534 #define sp_post_inc(inc) ({ \
535 unsigned long __esp = truncate_word(_regs.esp, ctxt->sp_size/8); \
536 _register_address_increment(_regs.esp, (inc), ctxt->sp_size/8); \
537 __esp; \
538 })
540 #define jmp_rel(rel) \
541 do { \
542 int _rel = (int)(rel); \
543 _regs.eip += _rel; \
544 if ( !mode_64bit() ) \
545 _regs.eip = ((op_bytes == 2) \
546 ? (uint16_t)_regs.eip : (uint32_t)_regs.eip); \
547 } while (0)
549 struct fpu_insn_ctxt {
550 uint8_t insn_bytes;
551 uint8_t exn_raised;
552 };
554 static void fpu_handle_exception(void *_fic, struct cpu_user_regs *regs)
555 {
556 struct fpu_insn_ctxt *fic = _fic;
557 fic->exn_raised = 1;
558 regs->eip += fic->insn_bytes;
559 }
561 #define get_fpu(_type, _fic) \
562 do{ (_fic)->exn_raised = 0; \
563 fail_if(ops->get_fpu == NULL); \
564 rc = ops->get_fpu(fpu_handle_exception, _fic, _type, ctxt); \
565 if ( rc ) goto done; \
566 } while (0)
567 #define put_fpu(_fic) \
568 do{ \
569 if ( ops->put_fpu != NULL ) \
570 ops->put_fpu(ctxt); \
571 generate_exception_if((_fic)->exn_raised, EXC_MF, -1); \
572 } while (0)
574 #define emulate_fpu_insn(_op) \
575 do{ struct fpu_insn_ctxt fic; \
576 get_fpu(X86EMUL_FPU_fpu, &fic); \
577 asm volatile ( \
578 "movb $2f-1f,%0 \n" \
579 "1: " _op " \n" \
580 "2: \n" \
581 : "=m" (fic.insn_bytes) : : "memory" ); \
582 put_fpu(&fic); \
583 } while (0)
585 #define emulate_fpu_insn_memdst(_op, _arg) \
586 do{ struct fpu_insn_ctxt fic; \
587 get_fpu(X86EMUL_FPU_fpu, &fic); \
588 asm volatile ( \
589 "movb $2f-1f,%0 \n" \
590 "1: " _op " %1 \n" \
591 "2: \n" \
592 : "=m" (fic.insn_bytes), "=m" (_arg) \
593 : : "memory" ); \
594 put_fpu(&fic); \
595 } while (0)
597 #define emulate_fpu_insn_stub(_bytes...) \
598 do{ uint8_t stub[] = { _bytes, 0xc3 }; \
599 struct fpu_insn_ctxt fic = { .insn_bytes = sizeof(stub)-1 }; \
600 get_fpu(X86EMUL_FPU_fpu, &fic); \
601 (*(void(*)(void))stub)(); \
602 put_fpu(&fic); \
603 } while (0)
605 static unsigned long __get_rep_prefix(
606 struct cpu_user_regs *int_regs,
607 struct cpu_user_regs *ext_regs,
608 int ad_bytes)
609 {
610 unsigned long ecx = ((ad_bytes == 2) ? (uint16_t)int_regs->ecx :
611 (ad_bytes == 4) ? (uint32_t)int_regs->ecx :
612 int_regs->ecx);
614 /* Skip the instruction if no repetitions are required. */
615 if ( ecx == 0 )
616 ext_regs->eip = int_regs->eip;
618 return ecx;
619 }
621 #define get_rep_prefix() ({ \
622 unsigned long max_reps = 1; \
623 if ( rep_prefix ) \
624 max_reps = __get_rep_prefix(&_regs, ctxt->regs, ad_bytes); \
625 if ( max_reps == 0 ) \
626 goto done; \
627 max_reps; \
628 })
630 static void __put_rep_prefix(
631 struct cpu_user_regs *int_regs,
632 struct cpu_user_regs *ext_regs,
633 int ad_bytes,
634 unsigned long reps_completed)
635 {
636 unsigned long ecx = ((ad_bytes == 2) ? (uint16_t)int_regs->ecx :
637 (ad_bytes == 4) ? (uint32_t)int_regs->ecx :
638 int_regs->ecx);
640 /* Reduce counter appropriately, and repeat instruction if non-zero. */
641 ecx -= reps_completed;
642 if ( ecx != 0 )
643 int_regs->eip = ext_regs->eip;
645 if ( ad_bytes == 2 )
646 *(uint16_t *)&int_regs->ecx = ecx;
647 else if ( ad_bytes == 4 )
648 int_regs->ecx = (uint32_t)ecx;
649 else
650 int_regs->ecx = ecx;
651 }
653 #define put_rep_prefix(reps_completed) ({ \
654 if ( rep_prefix ) \
655 __put_rep_prefix(&_regs, ctxt->regs, ad_bytes, reps_completed); \
656 })
658 /*
659 * Unsigned multiplication with double-word result.
660 * IN: Multiplicand=m[0], Multiplier=m[1]
661 * OUT: Return CF/OF (overflow status); Result=m[1]:m[0]
662 */
663 static int mul_dbl(unsigned long m[2])
664 {
665 int rc;
666 asm ( "mul %4; seto %b2"
667 : "=a" (m[0]), "=d" (m[1]), "=q" (rc)
668 : "0" (m[0]), "1" (m[1]), "2" (0) );
669 return rc;
670 }
672 /*
673 * Signed multiplication with double-word result.
674 * IN: Multiplicand=m[0], Multiplier=m[1]
675 * OUT: Return CF/OF (overflow status); Result=m[1]:m[0]
676 */
677 static int imul_dbl(unsigned long m[2])
678 {
679 int rc;
680 asm ( "imul %4; seto %b2"
681 : "=a" (m[0]), "=d" (m[1]), "=q" (rc)
682 : "0" (m[0]), "1" (m[1]), "2" (0) );
683 return rc;
684 }
686 /*
687 * Unsigned division of double-word dividend.
688 * IN: Dividend=u[1]:u[0], Divisor=v
689 * OUT: Return 1: #DE
690 * Return 0: Quotient=u[0], Remainder=u[1]
691 */
692 static int div_dbl(unsigned long u[2], unsigned long v)
693 {
694 if ( (v == 0) || (u[1] >= v) )
695 return 1;
696 asm ( "div %4"
697 : "=a" (u[0]), "=d" (u[1])
698 : "0" (u[0]), "1" (u[1]), "r" (v) );
699 return 0;
700 }
702 /*
703 * Signed division of double-word dividend.
704 * IN: Dividend=u[1]:u[0], Divisor=v
705 * OUT: Return 1: #DE
706 * Return 0: Quotient=u[0], Remainder=u[1]
707 * NB. We don't use idiv directly as it's moderately hard to work out
708 * ahead of time whether it will #DE, which we cannot allow to happen.
709 */
710 static int idiv_dbl(unsigned long u[2], unsigned long v)
711 {
712 int negu = (long)u[1] < 0, negv = (long)v < 0;
714 /* u = abs(u) */
715 if ( negu )
716 {
717 u[1] = ~u[1];
718 if ( (u[0] = -u[0]) == 0 )
719 u[1]++;
720 }
722 /* abs(u) / abs(v) */
723 if ( div_dbl(u, negv ? -v : v) )
724 return 1;
726 /* Remainder has same sign as dividend. It cannot overflow. */
727 if ( negu )
728 u[1] = -u[1];
730 /* Quotient is overflowed if sign bit is set. */
731 if ( negu ^ negv )
732 {
733 if ( (long)u[0] >= 0 )
734 u[0] = -u[0];
735 else if ( (u[0] << 1) != 0 ) /* == 0x80...0 is okay */
736 return 1;
737 }
738 else if ( (long)u[0] < 0 )
739 return 1;
741 return 0;
742 }
744 static int
745 test_cc(
746 unsigned int condition, unsigned int flags)
747 {
748 int rc = 0;
750 switch ( (condition & 15) >> 1 )
751 {
752 case 0: /* o */
753 rc |= (flags & EFLG_OF);
754 break;
755 case 1: /* b/c/nae */
756 rc |= (flags & EFLG_CF);
757 break;
758 case 2: /* z/e */
759 rc |= (flags & EFLG_ZF);
760 break;
761 case 3: /* be/na */
762 rc |= (flags & (EFLG_CF|EFLG_ZF));
763 break;
764 case 4: /* s */
765 rc |= (flags & EFLG_SF);
766 break;
767 case 5: /* p/pe */
768 rc |= (flags & EFLG_PF);
769 break;
770 case 7: /* le/ng */
771 rc |= (flags & EFLG_ZF);
772 /* fall through */
773 case 6: /* l/nge */
774 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
775 break;
776 }
778 /* Odd condition identifiers (lsb == 1) have inverted sense. */
779 return (!!rc ^ (condition & 1));
780 }
782 static int
783 get_cpl(
784 struct x86_emulate_ctxt *ctxt,
785 struct x86_emulate_ops *ops)
786 {
787 struct segment_register reg;
789 if ( ctxt->regs->eflags & EFLG_VM )
790 return 3;
792 if ( (ops->read_segment == NULL) ||
793 ops->read_segment(x86_seg_ss, &reg, ctxt) )
794 return -1;
796 return reg.attr.fields.dpl;
797 }
799 static int
800 _mode_iopl(
801 struct x86_emulate_ctxt *ctxt,
802 struct x86_emulate_ops *ops)
803 {
804 int cpl = get_cpl(ctxt, ops);
805 if ( cpl == -1 )
806 return -1;
807 return (cpl <= ((ctxt->regs->eflags >> 12) & 3));
808 }
810 #define mode_ring0() ({ \
811 int _cpl = get_cpl(ctxt, ops); \
812 fail_if(_cpl < 0); \
813 (_cpl == 0); \
814 })
815 #define mode_iopl() ({ \
816 int _iopl = _mode_iopl(ctxt, ops); \
817 fail_if(_iopl < 0); \
818 _iopl; \
819 })
821 static int ioport_access_check(
822 unsigned int first_port,
823 unsigned int bytes,
824 struct x86_emulate_ctxt *ctxt,
825 struct x86_emulate_ops *ops)
826 {
827 unsigned long iobmp;
828 struct segment_register tr;
829 int rc = X86EMUL_OKAY;
831 if ( !(ctxt->regs->eflags & EFLG_VM) && mode_iopl() )
832 return X86EMUL_OKAY;
834 fail_if(ops->read_segment == NULL);
835 if ( (rc = ops->read_segment(x86_seg_tr, &tr, ctxt)) != 0 )
836 return rc;
838 /* Ensure that the TSS is valid and has an io-bitmap-offset field. */
839 if ( !tr.attr.fields.p ||
840 ((tr.attr.fields.type & 0xd) != 0x9) ||
841 (tr.limit < 0x67) )
842 goto raise_exception;
844 if ( (rc = ops->read(x86_seg_none, tr.base + 0x66, &iobmp, 2, ctxt)) )
845 return rc;
847 /* Ensure TSS includes two bytes including byte containing first port. */
848 iobmp += first_port / 8;
849 if ( tr.limit <= iobmp )
850 goto raise_exception;
852 if ( (rc = ops->read(x86_seg_none, tr.base + iobmp, &iobmp, 2, ctxt)) )
853 return rc;
854 if ( (iobmp & (((1<<bytes)-1) << (first_port&7))) != 0 )
855 goto raise_exception;
857 done:
858 return rc;
860 raise_exception:
861 fail_if(ops->inject_hw_exception == NULL);
862 return ops->inject_hw_exception(EXC_GP, 0, ctxt) ? : X86EMUL_EXCEPTION;
863 }
865 static int
866 in_realmode(
867 struct x86_emulate_ctxt *ctxt,
868 struct x86_emulate_ops *ops)
869 {
870 unsigned long cr0;
871 int rc;
873 if ( ops->read_cr == NULL )
874 return 0;
876 rc = ops->read_cr(0, &cr0, ctxt);
877 return (!rc && !(cr0 & CR0_PE));
878 }
880 static int
881 realmode_load_seg(
882 enum x86_segment seg,
883 uint16_t sel,
884 struct x86_emulate_ctxt *ctxt,
885 struct x86_emulate_ops *ops)
886 {
887 struct segment_register reg;
888 int rc;
890 if ( (rc = ops->read_segment(seg, &reg, ctxt)) != 0 )
891 return rc;
893 reg.sel = sel;
894 reg.base = (uint32_t)sel << 4;
896 return ops->write_segment(seg, &reg, ctxt);
897 }
899 static int
900 protmode_load_seg(
901 enum x86_segment seg,
902 uint16_t sel,
903 struct x86_emulate_ctxt *ctxt,
904 struct x86_emulate_ops *ops)
905 {
906 struct segment_register desctab, cs, segr;
907 struct { uint32_t a, b; } desc;
908 unsigned long val;
909 uint8_t dpl, rpl, cpl;
910 uint32_t new_desc_b;
911 int rc, fault_type = EXC_TS;
913 /* NULL selector? */
914 if ( (sel & 0xfffc) == 0 )
915 {
916 if ( (seg == x86_seg_cs) || (seg == x86_seg_ss) )
917 goto raise_exn;
918 memset(&segr, 0, sizeof(segr));
919 return ops->write_segment(seg, &segr, ctxt);
920 }
922 /* LDT descriptor must be in the GDT. */
923 if ( (seg == x86_seg_ldtr) && (sel & 4) )
924 goto raise_exn;
926 if ( (rc = ops->read_segment(x86_seg_cs, &cs, ctxt)) ||
927 (rc = ops->read_segment((sel & 4) ? x86_seg_ldtr : x86_seg_gdtr,
928 &desctab, ctxt)) )
929 return rc;
931 /* Check against descriptor table limit. */
932 if ( ((sel & 0xfff8) + 7) > desctab.limit )
933 goto raise_exn;
935 do {
936 if ( (rc = ops->read(x86_seg_none, desctab.base + (sel & 0xfff8),
937 &val, 4, ctxt)) )
938 return rc;
939 desc.a = val;
940 if ( (rc = ops->read(x86_seg_none, desctab.base + (sel & 0xfff8) + 4,
941 &val, 4, ctxt)) )
942 return rc;
943 desc.b = val;
945 /* Segment present in memory? */
946 if ( !(desc.b & (1u<<15)) )
947 {
948 fault_type = EXC_NP;
949 goto raise_exn;
950 }
952 /* LDT descriptor is a system segment. All others are code/data. */
953 if ( (desc.b & (1u<<12)) == ((seg == x86_seg_ldtr) << 12) )
954 goto raise_exn;
956 dpl = (desc.b >> 13) & 3;
957 rpl = sel & 3;
958 cpl = cs.sel & 3;
960 switch ( seg )
961 {
962 case x86_seg_cs:
963 /* Code segment? */
964 if ( !(desc.b & (1u<<11)) )
965 goto raise_exn;
966 /* Non-conforming segment: check DPL against RPL. */
967 if ( ((desc.b & (6u<<9)) != 6) && (dpl != rpl) )
968 goto raise_exn;
969 break;
970 case x86_seg_ss:
971 /* Writable data segment? */
972 if ( (desc.b & (5u<<9)) != (1u<<9) )
973 goto raise_exn;
974 if ( (dpl != cpl) || (dpl != rpl) )
975 goto raise_exn;
976 break;
977 case x86_seg_ldtr:
978 /* LDT system segment? */
979 if ( (desc.b & (15u<<8)) != (2u<<8) )
980 goto raise_exn;
981 goto skip_accessed_flag;
982 default:
983 /* Readable code or data segment? */
984 if ( (desc.b & (5u<<9)) == (4u<<9) )
985 goto raise_exn;
986 /* Non-conforming segment: check DPL against RPL and CPL. */
987 if ( ((desc.b & (6u<<9)) != 6) && ((dpl < cpl) || (dpl < rpl)) )
988 goto raise_exn;
989 break;
990 }
992 /* Ensure Accessed flag is set. */
993 new_desc_b = desc.b | 0x100;
994 rc = ((desc.b & 0x100) ? X86EMUL_OKAY :
995 ops->cmpxchg(
996 x86_seg_none, desctab.base + (sel & 0xfff8) + 4,
997 &desc.b, &new_desc_b, 4, ctxt));
998 } while ( rc == X86EMUL_CMPXCHG_FAILED );
1000 if ( rc )
1001 return rc;
1003 /* Force the Accessed flag in our local copy. */
1004 desc.b |= 0x100;
1006 skip_accessed_flag:
1007 segr.base = (((desc.b << 0) & 0xff000000u) |
1008 ((desc.b << 16) & 0x00ff0000u) |
1009 ((desc.a >> 16) & 0x0000ffffu));
1010 segr.attr.bytes = (((desc.b >> 8) & 0x00ffu) |
1011 ((desc.b >> 12) & 0x0f00u));
1012 segr.limit = (desc.b & 0x000f0000u) | (desc.a & 0x0000ffffu);
1013 if ( segr.attr.fields.g )
1014 segr.limit = (segr.limit << 12) | 0xfffu;
1015 segr.sel = sel;
1016 return ops->write_segment(seg, &segr, ctxt);
1018 raise_exn:
1019 if ( ops->inject_hw_exception == NULL )
1020 return X86EMUL_UNHANDLEABLE;
1021 if ( (rc = ops->inject_hw_exception(fault_type, sel & 0xfffc, ctxt)) )
1022 return rc;
1023 return X86EMUL_EXCEPTION;
1026 static int
1027 load_seg(
1028 enum x86_segment seg,
1029 uint16_t sel,
1030 struct x86_emulate_ctxt *ctxt,
1031 struct x86_emulate_ops *ops)
1033 if ( (ops->read_segment == NULL) ||
1034 (ops->write_segment == NULL) )
1035 return X86EMUL_UNHANDLEABLE;
1037 if ( in_realmode(ctxt, ops) )
1038 return realmode_load_seg(seg, sel, ctxt, ops);
1040 return protmode_load_seg(seg, sel, ctxt, ops);
1043 void *
1044 decode_register(
1045 uint8_t modrm_reg, struct cpu_user_regs *regs, int highbyte_regs)
1047 void *p;
1049 switch ( modrm_reg )
1051 case 0: p = &regs->eax; break;
1052 case 1: p = &regs->ecx; break;
1053 case 2: p = &regs->edx; break;
1054 case 3: p = &regs->ebx; break;
1055 case 4: p = (highbyte_regs ?
1056 ((unsigned char *)&regs->eax + 1) :
1057 (unsigned char *)&regs->esp); break;
1058 case 5: p = (highbyte_regs ?
1059 ((unsigned char *)&regs->ecx + 1) :
1060 (unsigned char *)&regs->ebp); break;
1061 case 6: p = (highbyte_regs ?
1062 ((unsigned char *)&regs->edx + 1) :
1063 (unsigned char *)&regs->esi); break;
1064 case 7: p = (highbyte_regs ?
1065 ((unsigned char *)&regs->ebx + 1) :
1066 (unsigned char *)&regs->edi); break;
1067 #if defined(__x86_64__)
1068 case 8: p = &regs->r8; break;
1069 case 9: p = &regs->r9; break;
1070 case 10: p = &regs->r10; break;
1071 case 11: p = &regs->r11; break;
1072 case 12: p = &regs->r12; break;
1073 case 13: p = &regs->r13; break;
1074 case 14: p = &regs->r14; break;
1075 case 15: p = &regs->r15; break;
1076 #endif
1077 default: p = NULL; break;
1080 return p;
1083 #define decode_segment_failed x86_seg_tr
1084 enum x86_segment
1085 decode_segment(
1086 uint8_t modrm_reg)
1088 switch ( modrm_reg )
1090 case 0: return x86_seg_es;
1091 case 1: return x86_seg_cs;
1092 case 2: return x86_seg_ss;
1093 case 3: return x86_seg_ds;
1094 case 4: return x86_seg_fs;
1095 case 5: return x86_seg_gs;
1096 default: break;
1098 return decode_segment_failed;
1101 int
1102 x86_emulate(
1103 struct x86_emulate_ctxt *ctxt,
1104 struct x86_emulate_ops *ops)
1106 /* Shadow copy of register state. Committed on successful emulation. */
1107 struct cpu_user_regs _regs = *ctxt->regs;
1109 uint8_t b, d, sib, sib_index, sib_base, twobyte = 0, rex_prefix = 0;
1110 uint8_t modrm = 0, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
1111 unsigned int op_bytes, def_op_bytes, ad_bytes, def_ad_bytes;
1112 #define REPE_PREFIX 1
1113 #define REPNE_PREFIX 2
1114 unsigned int lock_prefix = 0, rep_prefix = 0;
1115 int override_seg = -1, rc = X86EMUL_OKAY;
1116 struct operand src, dst;
1118 /* Data operand effective address (usually computed from ModRM). */
1119 struct operand ea;
1121 /* Default is a memory operand relative to segment DS. */
1122 ea.type = OP_MEM;
1123 ea.mem.seg = x86_seg_ds;
1124 ea.mem.off = 0;
1126 ctxt->retire.byte = 0;
1128 op_bytes = def_op_bytes = ad_bytes = def_ad_bytes = ctxt->addr_size/8;
1129 if ( op_bytes == 8 )
1131 op_bytes = def_op_bytes = 4;
1132 #ifndef __x86_64__
1133 return X86EMUL_UNHANDLEABLE;
1134 #endif
1137 /* Prefix bytes. */
1138 for ( ; ; )
1140 switch ( b = insn_fetch_type(uint8_t) )
1142 case 0x66: /* operand-size override */
1143 op_bytes = def_op_bytes ^ 6;
1144 break;
1145 case 0x67: /* address-size override */
1146 ad_bytes = def_ad_bytes ^ (mode_64bit() ? 12 : 6);
1147 break;
1148 case 0x2e: /* CS override */
1149 override_seg = x86_seg_cs;
1150 break;
1151 case 0x3e: /* DS override */
1152 override_seg = x86_seg_ds;
1153 break;
1154 case 0x26: /* ES override */
1155 override_seg = x86_seg_es;
1156 break;
1157 case 0x64: /* FS override */
1158 override_seg = x86_seg_fs;
1159 break;
1160 case 0x65: /* GS override */
1161 override_seg = x86_seg_gs;
1162 break;
1163 case 0x36: /* SS override */
1164 override_seg = x86_seg_ss;
1165 break;
1166 case 0xf0: /* LOCK */
1167 lock_prefix = 1;
1168 break;
1169 case 0xf2: /* REPNE/REPNZ */
1170 rep_prefix = REPNE_PREFIX;
1171 break;
1172 case 0xf3: /* REP/REPE/REPZ */
1173 rep_prefix = REPE_PREFIX;
1174 break;
1175 case 0x40 ... 0x4f: /* REX */
1176 if ( !mode_64bit() )
1177 goto done_prefixes;
1178 rex_prefix = b;
1179 continue;
1180 default:
1181 goto done_prefixes;
1184 /* Any legacy prefix after a REX prefix nullifies its effect. */
1185 rex_prefix = 0;
1187 done_prefixes:
1189 if ( rex_prefix & 8 ) /* REX.W */
1190 op_bytes = 8;
1192 /* Opcode byte(s). */
1193 d = opcode_table[b];
1194 if ( d == 0 )
1196 /* Two-byte opcode? */
1197 if ( b == 0x0f )
1199 twobyte = 1;
1200 b = insn_fetch_type(uint8_t);
1201 d = twobyte_table[b];
1204 /* Unrecognised? */
1205 if ( d == 0 )
1206 goto cannot_emulate;
1209 /* Lock prefix is allowed only on RMW instructions. */
1210 generate_exception_if((d & Mov) && lock_prefix, EXC_GP, 0);
1212 /* ModRM and SIB bytes. */
1213 if ( d & ModRM )
1215 modrm = insn_fetch_type(uint8_t);
1216 modrm_mod = (modrm & 0xc0) >> 6;
1217 modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3);
1218 modrm_rm = modrm & 0x07;
1220 if ( modrm_mod == 3 )
1222 modrm_rm |= (rex_prefix & 1) << 3;
1223 ea.type = OP_REG;
1224 ea.reg = decode_register(
1225 modrm_rm, &_regs, (d & ByteOp) && (rex_prefix == 0));
1227 else if ( ad_bytes == 2 )
1229 /* 16-bit ModR/M decode. */
1230 switch ( modrm_rm )
1232 case 0:
1233 ea.mem.off = _regs.ebx + _regs.esi;
1234 break;
1235 case 1:
1236 ea.mem.off = _regs.ebx + _regs.edi;
1237 break;
1238 case 2:
1239 ea.mem.seg = x86_seg_ss;
1240 ea.mem.off = _regs.ebp + _regs.esi;
1241 break;
1242 case 3:
1243 ea.mem.seg = x86_seg_ss;
1244 ea.mem.off = _regs.ebp + _regs.edi;
1245 break;
1246 case 4:
1247 ea.mem.off = _regs.esi;
1248 break;
1249 case 5:
1250 ea.mem.off = _regs.edi;
1251 break;
1252 case 6:
1253 if ( modrm_mod == 0 )
1254 break;
1255 ea.mem.seg = x86_seg_ss;
1256 ea.mem.off = _regs.ebp;
1257 break;
1258 case 7:
1259 ea.mem.off = _regs.ebx;
1260 break;
1262 switch ( modrm_mod )
1264 case 0:
1265 if ( modrm_rm == 6 )
1266 ea.mem.off = insn_fetch_type(int16_t);
1267 break;
1268 case 1:
1269 ea.mem.off += insn_fetch_type(int8_t);
1270 break;
1271 case 2:
1272 ea.mem.off += insn_fetch_type(int16_t);
1273 break;
1275 ea.mem.off = truncate_ea(ea.mem.off);
1277 else
1279 /* 32/64-bit ModR/M decode. */
1280 if ( modrm_rm == 4 )
1282 sib = insn_fetch_type(uint8_t);
1283 sib_index = ((sib >> 3) & 7) | ((rex_prefix << 2) & 8);
1284 sib_base = (sib & 7) | ((rex_prefix << 3) & 8);
1285 if ( sib_index != 4 )
1286 ea.mem.off = *(long*)decode_register(sib_index, &_regs, 0);
1287 ea.mem.off <<= (sib >> 6) & 3;
1288 if ( (modrm_mod == 0) && ((sib_base & 7) == 5) )
1289 ea.mem.off += insn_fetch_type(int32_t);
1290 else if ( sib_base == 4 )
1292 ea.mem.seg = x86_seg_ss;
1293 ea.mem.off += _regs.esp;
1294 if ( !twobyte && (b == 0x8f) )
1295 /* POP <rm> computes its EA post increment. */
1296 ea.mem.off += ((mode_64bit() && (op_bytes == 4))
1297 ? 8 : op_bytes);
1299 else if ( sib_base == 5 )
1301 ea.mem.seg = x86_seg_ss;
1302 ea.mem.off += _regs.ebp;
1304 else
1305 ea.mem.off += *(long*)decode_register(sib_base, &_regs, 0);
1307 else
1309 modrm_rm |= (rex_prefix & 1) << 3;
1310 ea.mem.off = *(long *)decode_register(modrm_rm, &_regs, 0);
1311 if ( (modrm_rm == 5) && (modrm_mod != 0) )
1312 ea.mem.seg = x86_seg_ss;
1314 switch ( modrm_mod )
1316 case 0:
1317 if ( (modrm_rm & 7) != 5 )
1318 break;
1319 ea.mem.off = insn_fetch_type(int32_t);
1320 if ( !mode_64bit() )
1321 break;
1322 /* Relative to RIP of next instruction. Argh! */
1323 ea.mem.off += _regs.eip;
1324 if ( (d & SrcMask) == SrcImm )
1325 ea.mem.off += (d & ByteOp) ? 1 :
1326 ((op_bytes == 8) ? 4 : op_bytes);
1327 else if ( (d & SrcMask) == SrcImmByte )
1328 ea.mem.off += 1;
1329 else if ( !twobyte && ((b & 0xfe) == 0xf6) &&
1330 ((modrm_reg & 7) <= 1) )
1331 /* Special case in Grp3: test has immediate operand. */
1332 ea.mem.off += (d & ByteOp) ? 1
1333 : ((op_bytes == 8) ? 4 : op_bytes);
1334 else if ( twobyte && ((b & 0xf7) == 0xa4) )
1335 /* SHLD/SHRD with immediate byte third operand. */
1336 ea.mem.off++;
1337 break;
1338 case 1:
1339 ea.mem.off += insn_fetch_type(int8_t);
1340 break;
1341 case 2:
1342 ea.mem.off += insn_fetch_type(int32_t);
1343 break;
1345 ea.mem.off = truncate_ea(ea.mem.off);
1349 if ( override_seg != -1 )
1350 ea.mem.seg = override_seg;
1352 /* Special instructions do their own operand decoding. */
1353 if ( (d & DstMask) == ImplicitOps )
1354 goto special_insn;
1356 /* Decode and fetch the source operand: register, memory or immediate. */
1357 switch ( d & SrcMask )
1359 case SrcNone:
1360 break;
1361 case SrcReg:
1362 src.type = OP_REG;
1363 if ( d & ByteOp )
1365 src.reg = decode_register(modrm_reg, &_regs, (rex_prefix == 0));
1366 src.val = *(uint8_t *)src.reg;
1367 src.bytes = 1;
1369 else
1371 src.reg = decode_register(modrm_reg, &_regs, 0);
1372 switch ( (src.bytes = op_bytes) )
1374 case 2: src.val = *(uint16_t *)src.reg; break;
1375 case 4: src.val = *(uint32_t *)src.reg; break;
1376 case 8: src.val = *(uint64_t *)src.reg; break;
1379 break;
1380 case SrcMem16:
1381 ea.bytes = 2;
1382 goto srcmem_common;
1383 case SrcMem:
1384 ea.bytes = (d & ByteOp) ? 1 : op_bytes;
1385 srcmem_common:
1386 src = ea;
1387 if ( src.type == OP_REG )
1389 switch ( src.bytes )
1391 case 1: src.val = *(uint8_t *)src.reg; break;
1392 case 2: src.val = *(uint16_t *)src.reg; break;
1393 case 4: src.val = *(uint32_t *)src.reg; break;
1394 case 8: src.val = *(uint64_t *)src.reg; break;
1397 else if ( (rc = ops->read(src.mem.seg, src.mem.off,
1398 &src.val, src.bytes, ctxt)) )
1399 goto done;
1400 break;
1401 case SrcImm:
1402 src.type = OP_IMM;
1403 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1404 if ( src.bytes == 8 ) src.bytes = 4;
1405 /* NB. Immediates are sign-extended as necessary. */
1406 switch ( src.bytes )
1408 case 1: src.val = insn_fetch_type(int8_t); break;
1409 case 2: src.val = insn_fetch_type(int16_t); break;
1410 case 4: src.val = insn_fetch_type(int32_t); break;
1412 break;
1413 case SrcImmByte:
1414 src.type = OP_IMM;
1415 src.bytes = 1;
1416 src.val = insn_fetch_type(int8_t);
1417 break;
1420 /* Decode and fetch the destination operand: register or memory. */
1421 switch ( d & DstMask )
1423 case DstReg:
1424 dst.type = OP_REG;
1425 if ( d & ByteOp )
1427 dst.reg = decode_register(modrm_reg, &_regs, (rex_prefix == 0));
1428 dst.val = *(uint8_t *)dst.reg;
1429 dst.bytes = 1;
1431 else
1433 dst.reg = decode_register(modrm_reg, &_regs, 0);
1434 switch ( (dst.bytes = op_bytes) )
1436 case 2: dst.val = *(uint16_t *)dst.reg; break;
1437 case 4: dst.val = *(uint32_t *)dst.reg; break;
1438 case 8: dst.val = *(uint64_t *)dst.reg; break;
1441 break;
1442 case DstBitBase:
1443 if ( ((d & SrcMask) == SrcImmByte) || (ea.type == OP_REG) )
1445 src.val &= (op_bytes << 3) - 1;
1447 else
1449 /*
1450 * EA += BitOffset DIV op_bytes*8
1451 * BitOffset = BitOffset MOD op_bytes*8
1452 * DIV truncates towards negative infinity.
1453 * MOD always produces a positive result.
1454 */
1455 if ( op_bytes == 2 )
1456 src.val = (int16_t)src.val;
1457 else if ( op_bytes == 4 )
1458 src.val = (int32_t)src.val;
1459 if ( (long)src.val < 0 )
1461 unsigned long byte_offset;
1462 byte_offset = op_bytes + (((-src.val-1) >> 3) & ~(op_bytes-1));
1463 ea.mem.off -= byte_offset;
1464 src.val = (byte_offset << 3) + src.val;
1466 else
1468 ea.mem.off += (src.val >> 3) & ~(op_bytes - 1);
1469 src.val &= (op_bytes << 3) - 1;
1472 /* Becomes a normal DstMem operation from here on. */
1473 d = (d & ~DstMask) | DstMem;
1474 case DstMem:
1475 ea.bytes = (d & ByteOp) ? 1 : op_bytes;
1476 dst = ea;
1477 if ( dst.type == OP_REG )
1479 switch ( dst.bytes )
1481 case 1: dst.val = *(uint8_t *)dst.reg; break;
1482 case 2: dst.val = *(uint16_t *)dst.reg; break;
1483 case 4: dst.val = *(uint32_t *)dst.reg; break;
1484 case 8: dst.val = *(uint64_t *)dst.reg; break;
1487 else if ( !(d & Mov) ) /* optimisation - avoid slow emulated read */
1489 if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
1490 &dst.val, dst.bytes, ctxt)) )
1491 goto done;
1492 dst.orig_val = dst.val;
1494 break;
1497 /* LOCK prefix allowed only on instructions with memory destination. */
1498 generate_exception_if(lock_prefix && (dst.type != OP_MEM), EXC_GP, 0);
1500 if ( twobyte )
1501 goto twobyte_insn;
1503 switch ( b )
1505 case 0x04 ... 0x05: /* add imm,%%eax */
1506 dst.reg = (unsigned long *)&_regs.eax;
1507 dst.val = _regs.eax;
1508 case 0x00 ... 0x03: add: /* add */
1509 emulate_2op_SrcV("add", src, dst, _regs.eflags);
1510 break;
1512 case 0x0c ... 0x0d: /* or imm,%%eax */
1513 dst.reg = (unsigned long *)&_regs.eax;
1514 dst.val = _regs.eax;
1515 case 0x08 ... 0x0b: or: /* or */
1516 emulate_2op_SrcV("or", src, dst, _regs.eflags);
1517 break;
1519 case 0x14 ... 0x15: /* adc imm,%%eax */
1520 dst.reg = (unsigned long *)&_regs.eax;
1521 dst.val = _regs.eax;
1522 case 0x10 ... 0x13: adc: /* adc */
1523 emulate_2op_SrcV("adc", src, dst, _regs.eflags);
1524 break;
1526 case 0x1c ... 0x1d: /* sbb imm,%%eax */
1527 dst.reg = (unsigned long *)&_regs.eax;
1528 dst.val = _regs.eax;
1529 case 0x18 ... 0x1b: sbb: /* sbb */
1530 emulate_2op_SrcV("sbb", src, dst, _regs.eflags);
1531 break;
1533 case 0x24 ... 0x25: /* and imm,%%eax */
1534 dst.reg = (unsigned long *)&_regs.eax;
1535 dst.val = _regs.eax;
1536 case 0x20 ... 0x23: and: /* and */
1537 emulate_2op_SrcV("and", src, dst, _regs.eflags);
1538 break;
1540 case 0x2c ... 0x2d: /* sub imm,%%eax */
1541 dst.reg = (unsigned long *)&_regs.eax;
1542 dst.val = _regs.eax;
1543 case 0x28 ... 0x2b: sub: /* sub */
1544 emulate_2op_SrcV("sub", src, dst, _regs.eflags);
1545 break;
1547 case 0x34 ... 0x35: /* xor imm,%%eax */
1548 dst.reg = (unsigned long *)&_regs.eax;
1549 dst.val = _regs.eax;
1550 case 0x30 ... 0x33: xor: /* xor */
1551 emulate_2op_SrcV("xor", src, dst, _regs.eflags);
1552 break;
1554 case 0x3c ... 0x3d: /* cmp imm,%%eax */
1555 dst.reg = (unsigned long *)&_regs.eax;
1556 dst.val = _regs.eax;
1557 case 0x38 ... 0x3b: cmp: /* cmp */
1558 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
1559 break;
1561 case 0x62: /* bound */ {
1562 unsigned long src_val2;
1563 int lb, ub, idx;
1564 generate_exception_if(mode_64bit() || (src.type != OP_MEM),
1565 EXC_UD, -1);
1566 if ( (rc = ops->read(src.mem.seg, src.mem.off + op_bytes,
1567 &src_val2, op_bytes, ctxt)) )
1568 goto done;
1569 ub = (op_bytes == 2) ? (int16_t)src_val2 : (int32_t)src_val2;
1570 lb = (op_bytes == 2) ? (int16_t)src.val : (int32_t)src.val;
1571 idx = (op_bytes == 2) ? (int16_t)dst.val : (int32_t)dst.val;
1572 generate_exception_if((idx < lb) || (idx > ub), EXC_BR, -1);
1573 dst.type = OP_NONE;
1574 break;
1577 case 0x63: /* movsxd (x86/64) / arpl (x86/32) */
1578 if ( mode_64bit() )
1580 /* movsxd */
1581 if ( src.type == OP_REG )
1582 src.val = *(int32_t *)src.reg;
1583 else if ( (rc = ops->read(src.mem.seg, src.mem.off,
1584 &src.val, 4, ctxt)) )
1585 goto done;
1586 dst.val = (int32_t)src.val;
1588 else
1590 /* arpl */
1591 uint16_t src_val = dst.val;
1592 dst = src;
1593 _regs.eflags &= ~EFLG_ZF;
1594 _regs.eflags |= ((src_val & 3) > (dst.val & 3)) ? EFLG_ZF : 0;
1595 if ( _regs.eflags & EFLG_ZF )
1596 dst.val = (dst.val & ~3) | (src_val & 3);
1597 else
1598 dst.type = OP_NONE;
1599 generate_exception_if(in_realmode(ctxt, ops), EXC_UD, -1);
1601 break;
1603 case 0x69: /* imul imm16/32 */
1604 case 0x6b: /* imul imm8 */ {
1605 unsigned long src1; /* ModR/M source operand */
1606 if ( ea.type == OP_REG )
1607 src1 = *ea.reg;
1608 else if ( (rc = ops->read(ea.mem.seg, ea.mem.off,
1609 &src1, op_bytes, ctxt)) )
1610 goto done;
1611 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1612 switch ( dst.bytes )
1614 case 2:
1615 dst.val = ((uint32_t)(int16_t)src.val *
1616 (uint32_t)(int16_t)src1);
1617 if ( (int16_t)dst.val != (uint32_t)dst.val )
1618 _regs.eflags |= EFLG_OF|EFLG_CF;
1619 break;
1620 #ifdef __x86_64__
1621 case 4:
1622 dst.val = ((uint64_t)(int32_t)src.val *
1623 (uint64_t)(int32_t)src1);
1624 if ( (int32_t)dst.val != dst.val )
1625 _regs.eflags |= EFLG_OF|EFLG_CF;
1626 break;
1627 #endif
1628 default: {
1629 unsigned long m[2] = { src.val, src1 };
1630 if ( imul_dbl(m) )
1631 _regs.eflags |= EFLG_OF|EFLG_CF;
1632 dst.val = m[0];
1633 break;
1636 break;
1639 case 0x82: /* Grp1 (x86/32 only) */
1640 generate_exception_if(mode_64bit(), EXC_UD, -1);
1641 case 0x80: case 0x81: case 0x83: /* Grp1 */
1642 switch ( modrm_reg & 7 )
1644 case 0: goto add;
1645 case 1: goto or;
1646 case 2: goto adc;
1647 case 3: goto sbb;
1648 case 4: goto and;
1649 case 5: goto sub;
1650 case 6: goto xor;
1651 case 7: goto cmp;
1653 break;
1655 case 0xa8 ... 0xa9: /* test imm,%%eax */
1656 dst.reg = (unsigned long *)&_regs.eax;
1657 dst.val = _regs.eax;
1658 case 0x84 ... 0x85: test: /* test */
1659 emulate_2op_SrcV("test", src, dst, _regs.eflags);
1660 break;
1662 case 0x86 ... 0x87: xchg: /* xchg */
1663 /* Write back the register source. */
1664 switch ( dst.bytes )
1666 case 1: *(uint8_t *)src.reg = (uint8_t)dst.val; break;
1667 case 2: *(uint16_t *)src.reg = (uint16_t)dst.val; break;
1668 case 4: *src.reg = (uint32_t)dst.val; break; /* 64b reg: zero-extend */
1669 case 8: *src.reg = dst.val; break;
1671 /* Write back the memory destination with implicit LOCK prefix. */
1672 dst.val = src.val;
1673 lock_prefix = 1;
1674 break;
1676 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1677 generate_exception_if((modrm_reg & 7) != 0, EXC_UD, -1);
1678 case 0x88 ... 0x8b: /* mov */
1679 dst.val = src.val;
1680 break;
1682 case 0x8c: /* mov Sreg,r/m */ {
1683 struct segment_register reg;
1684 enum x86_segment seg = decode_segment(modrm_reg);
1685 generate_exception_if(seg == decode_segment_failed, EXC_UD, -1);
1686 fail_if(ops->read_segment == NULL);
1687 if ( (rc = ops->read_segment(seg, &reg, ctxt)) != 0 )
1688 goto done;
1689 dst.val = reg.sel;
1690 if ( dst.type == OP_MEM )
1691 dst.bytes = 2;
1692 break;
1695 case 0x8e: /* mov r/m,Sreg */ {
1696 enum x86_segment seg = decode_segment(modrm_reg);
1697 generate_exception_if(seg == decode_segment_failed, EXC_UD, -1);
1698 if ( (rc = load_seg(seg, (uint16_t)src.val, ctxt, ops)) != 0 )
1699 goto done;
1700 if ( seg == x86_seg_ss )
1701 ctxt->retire.flags.mov_ss = 1;
1702 dst.type = OP_NONE;
1703 break;
1706 case 0x8d: /* lea */
1707 dst.val = ea.mem.off;
1708 break;
1710 case 0x8f: /* pop (sole member of Grp1a) */
1711 generate_exception_if((modrm_reg & 7) != 0, EXC_UD, -1);
1712 /* 64-bit mode: POP defaults to a 64-bit operand. */
1713 if ( mode_64bit() && (dst.bytes == 4) )
1714 dst.bytes = 8;
1715 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
1716 &dst.val, dst.bytes, ctxt)) != 0 )
1717 goto done;
1718 break;
1720 case 0xb0 ... 0xb7: /* mov imm8,r8 */
1721 dst.reg = decode_register(
1722 (b & 7) | ((rex_prefix & 1) << 3), &_regs, (rex_prefix == 0));
1723 dst.val = src.val;
1724 break;
1726 case 0xb8 ... 0xbf: /* mov imm{16,32,64},r{16,32,64} */
1727 if ( dst.bytes == 8 ) /* Fetch more bytes to obtain imm64 */
1728 src.val = ((uint32_t)src.val |
1729 ((uint64_t)insn_fetch_type(uint32_t) << 32));
1730 dst.reg = decode_register(
1731 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
1732 dst.val = src.val;
1733 break;
1735 case 0xc0 ... 0xc1: grp2: /* Grp2 */
1736 switch ( modrm_reg & 7 )
1738 case 0: /* rol */
1739 emulate_2op_SrcB("rol", src, dst, _regs.eflags);
1740 break;
1741 case 1: /* ror */
1742 emulate_2op_SrcB("ror", src, dst, _regs.eflags);
1743 break;
1744 case 2: /* rcl */
1745 emulate_2op_SrcB("rcl", src, dst, _regs.eflags);
1746 break;
1747 case 3: /* rcr */
1748 emulate_2op_SrcB("rcr", src, dst, _regs.eflags);
1749 break;
1750 case 4: /* sal/shl */
1751 case 6: /* sal/shl */
1752 emulate_2op_SrcB("sal", src, dst, _regs.eflags);
1753 break;
1754 case 5: /* shr */
1755 emulate_2op_SrcB("shr", src, dst, _regs.eflags);
1756 break;
1757 case 7: /* sar */
1758 emulate_2op_SrcB("sar", src, dst, _regs.eflags);
1759 break;
1761 break;
1763 case 0xc4: /* les */ {
1764 unsigned long sel;
1765 dst.val = x86_seg_es;
1766 les: /* dst.val identifies the segment */
1767 generate_exception_if(src.type != OP_MEM, EXC_UD, -1);
1768 if ( (rc = ops->read(src.mem.seg, src.mem.off + src.bytes,
1769 &sel, 2, ctxt)) != 0 )
1770 goto done;
1771 if ( (rc = load_seg(dst.val, (uint16_t)sel, ctxt, ops)) != 0 )
1772 goto done;
1773 dst.val = src.val;
1774 break;
1777 case 0xc5: /* lds */
1778 dst.val = x86_seg_ds;
1779 goto les;
1781 case 0xd0 ... 0xd1: /* Grp2 */
1782 src.val = 1;
1783 goto grp2;
1785 case 0xd2 ... 0xd3: /* Grp2 */
1786 src.val = _regs.ecx;
1787 goto grp2;
1789 case 0xf6 ... 0xf7: /* Grp3 */
1790 switch ( modrm_reg & 7 )
1792 case 0 ... 1: /* test */
1793 /* Special case in Grp3: test has an immediate source operand. */
1794 src.type = OP_IMM;
1795 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1796 if ( src.bytes == 8 ) src.bytes = 4;
1797 switch ( src.bytes )
1799 case 1: src.val = insn_fetch_type(int8_t); break;
1800 case 2: src.val = insn_fetch_type(int16_t); break;
1801 case 4: src.val = insn_fetch_type(int32_t); break;
1803 goto test;
1804 case 2: /* not */
1805 dst.val = ~dst.val;
1806 break;
1807 case 3: /* neg */
1808 emulate_1op("neg", dst, _regs.eflags);
1809 break;
1810 case 4: /* mul */
1811 src = dst;
1812 dst.type = OP_REG;
1813 dst.reg = (unsigned long *)&_regs.eax;
1814 dst.val = *dst.reg;
1815 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1816 switch ( src.bytes )
1818 case 1:
1819 dst.val = (uint8_t)dst.val;
1820 dst.val *= src.val;
1821 if ( (uint8_t)dst.val != (uint16_t)dst.val )
1822 _regs.eflags |= EFLG_OF|EFLG_CF;
1823 dst.bytes = 2;
1824 break;
1825 case 2:
1826 dst.val = (uint16_t)dst.val;
1827 dst.val *= src.val;
1828 if ( (uint16_t)dst.val != (uint32_t)dst.val )
1829 _regs.eflags |= EFLG_OF|EFLG_CF;
1830 *(uint16_t *)&_regs.edx = dst.val >> 16;
1831 break;
1832 #ifdef __x86_64__
1833 case 4:
1834 dst.val = (uint32_t)dst.val;
1835 dst.val *= src.val;
1836 if ( (uint32_t)dst.val != dst.val )
1837 _regs.eflags |= EFLG_OF|EFLG_CF;
1838 _regs.edx = (uint32_t)(dst.val >> 32);
1839 break;
1840 #endif
1841 default: {
1842 unsigned long m[2] = { src.val, dst.val };
1843 if ( mul_dbl(m) )
1844 _regs.eflags |= EFLG_OF|EFLG_CF;
1845 _regs.edx = m[1];
1846 dst.val = m[0];
1847 break;
1850 break;
1851 case 5: /* imul */
1852 src = dst;
1853 dst.type = OP_REG;
1854 dst.reg = (unsigned long *)&_regs.eax;
1855 dst.val = *dst.reg;
1856 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1857 switch ( src.bytes )
1859 case 1:
1860 dst.val = ((uint16_t)(int8_t)src.val *
1861 (uint16_t)(int8_t)dst.val);
1862 if ( (int8_t)dst.val != (uint16_t)dst.val )
1863 _regs.eflags |= EFLG_OF|EFLG_CF;
1864 dst.bytes = 2;
1865 break;
1866 case 2:
1867 dst.val = ((uint32_t)(int16_t)src.val *
1868 (uint32_t)(int16_t)dst.val);
1869 if ( (int16_t)dst.val != (uint32_t)dst.val )
1870 _regs.eflags |= EFLG_OF|EFLG_CF;
1871 *(uint16_t *)&_regs.edx = dst.val >> 16;
1872 break;
1873 #ifdef __x86_64__
1874 case 4:
1875 dst.val = ((uint64_t)(int32_t)src.val *
1876 (uint64_t)(int32_t)dst.val);
1877 if ( (int32_t)dst.val != dst.val )
1878 _regs.eflags |= EFLG_OF|EFLG_CF;
1879 _regs.edx = (uint32_t)(dst.val >> 32);
1880 break;
1881 #endif
1882 default: {
1883 unsigned long m[2] = { src.val, dst.val };
1884 if ( imul_dbl(m) )
1885 _regs.eflags |= EFLG_OF|EFLG_CF;
1886 _regs.edx = m[1];
1887 dst.val = m[0];
1888 break;
1891 break;
1892 case 6: /* div */ {
1893 unsigned long u[2], v;
1894 src = dst;
1895 dst.type = OP_REG;
1896 dst.reg = (unsigned long *)&_regs.eax;
1897 switch ( src.bytes )
1899 case 1:
1900 u[0] = (uint16_t)_regs.eax;
1901 u[1] = 0;
1902 v = (uint8_t)src.val;
1903 generate_exception_if(
1904 div_dbl(u, v) || ((uint8_t)u[0] != (uint16_t)u[0]),
1905 EXC_DE, -1);
1906 dst.val = (uint8_t)u[0];
1907 ((uint8_t *)&_regs.eax)[1] = u[1];
1908 break;
1909 case 2:
1910 u[0] = ((uint32_t)_regs.edx << 16) | (uint16_t)_regs.eax;
1911 u[1] = 0;
1912 v = (uint16_t)src.val;
1913 generate_exception_if(
1914 div_dbl(u, v) || ((uint16_t)u[0] != (uint32_t)u[0]),
1915 EXC_DE, -1);
1916 dst.val = (uint16_t)u[0];
1917 *(uint16_t *)&_regs.edx = u[1];
1918 break;
1919 #ifdef __x86_64__
1920 case 4:
1921 u[0] = (_regs.edx << 32) | (uint32_t)_regs.eax;
1922 u[1] = 0;
1923 v = (uint32_t)src.val;
1924 generate_exception_if(
1925 div_dbl(u, v) || ((uint32_t)u[0] != u[0]),
1926 EXC_DE, -1);
1927 dst.val = (uint32_t)u[0];
1928 _regs.edx = (uint32_t)u[1];
1929 break;
1930 #endif
1931 default:
1932 u[0] = _regs.eax;
1933 u[1] = _regs.edx;
1934 v = src.val;
1935 generate_exception_if(div_dbl(u, v), EXC_DE, -1);
1936 dst.val = u[0];
1937 _regs.edx = u[1];
1938 break;
1940 break;
1942 case 7: /* idiv */ {
1943 unsigned long u[2], v;
1944 src = dst;
1945 dst.type = OP_REG;
1946 dst.reg = (unsigned long *)&_regs.eax;
1947 switch ( src.bytes )
1949 case 1:
1950 u[0] = (int16_t)_regs.eax;
1951 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1952 v = (int8_t)src.val;
1953 generate_exception_if(
1954 idiv_dbl(u, v) || ((int8_t)u[0] != (int16_t)u[0]),
1955 EXC_DE, -1);
1956 dst.val = (int8_t)u[0];
1957 ((int8_t *)&_regs.eax)[1] = u[1];
1958 break;
1959 case 2:
1960 u[0] = (int32_t)((_regs.edx << 16) | (uint16_t)_regs.eax);
1961 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1962 v = (int16_t)src.val;
1963 generate_exception_if(
1964 idiv_dbl(u, v) || ((int16_t)u[0] != (int32_t)u[0]),
1965 EXC_DE, -1);
1966 dst.val = (int16_t)u[0];
1967 *(int16_t *)&_regs.edx = u[1];
1968 break;
1969 #ifdef __x86_64__
1970 case 4:
1971 u[0] = (_regs.edx << 32) | (uint32_t)_regs.eax;
1972 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1973 v = (int32_t)src.val;
1974 generate_exception_if(
1975 idiv_dbl(u, v) || ((int32_t)u[0] != u[0]),
1976 EXC_DE, -1);
1977 dst.val = (int32_t)u[0];
1978 _regs.edx = (uint32_t)u[1];
1979 break;
1980 #endif
1981 default:
1982 u[0] = _regs.eax;
1983 u[1] = _regs.edx;
1984 v = src.val;
1985 generate_exception_if(idiv_dbl(u, v), EXC_DE, -1);
1986 dst.val = u[0];
1987 _regs.edx = u[1];
1988 break;
1990 break;
1992 default:
1993 goto cannot_emulate;
1995 break;
1997 case 0xfe: /* Grp4 */
1998 generate_exception_if((modrm_reg & 7) >= 2, EXC_UD, -1);
1999 case 0xff: /* Grp5 */
2000 switch ( modrm_reg & 7 )
2002 case 0: /* inc */
2003 emulate_1op("inc", dst, _regs.eflags);
2004 break;
2005 case 1: /* dec */
2006 emulate_1op("dec", dst, _regs.eflags);
2007 break;
2008 case 2: /* call (near) */
2009 case 4: /* jmp (near) */
2010 if ( (dst.bytes != 8) && mode_64bit() )
2012 dst.bytes = op_bytes = 8;
2013 if ( dst.type == OP_REG )
2014 dst.val = *dst.reg;
2015 else if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
2016 &dst.val, 8, ctxt)) != 0 )
2017 goto done;
2019 src.val = _regs.eip;
2020 _regs.eip = dst.val;
2021 if ( (modrm_reg & 7) == 2 )
2022 goto push; /* call */
2023 dst.type = OP_NONE;
2024 break;
2025 case 3: /* call (far, absolute indirect) */
2026 case 5: /* jmp (far, absolute indirect) */ {
2027 unsigned long sel;
2029 generate_exception_if(dst.type != OP_MEM, EXC_UD, -1);
2031 if ( (rc = ops->read(dst.mem.seg, dst.mem.off+dst.bytes,
2032 &sel, 2, ctxt)) )
2033 goto done;
2035 if ( (modrm_reg & 7) == 3 ) /* call */
2037 struct segment_register reg;
2038 fail_if(ops->read_segment == NULL);
2039 if ( (rc = ops->read_segment(x86_seg_cs, &reg, ctxt)) ||
2040 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2041 reg.sel, op_bytes, ctxt)) ||
2042 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2043 _regs.eip, op_bytes, ctxt)) )
2044 goto done;
2047 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2048 goto done;
2049 _regs.eip = dst.val;
2051 dst.type = OP_NONE;
2052 break;
2054 case 6: /* push */
2055 /* 64-bit mode: PUSH defaults to a 64-bit operand. */
2056 if ( mode_64bit() && (dst.bytes == 4) )
2058 dst.bytes = 8;
2059 if ( dst.type == OP_REG )
2060 dst.val = *dst.reg;
2061 else if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
2062 &dst.val, 8, ctxt)) != 0 )
2063 goto done;
2065 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2066 dst.val, dst.bytes, ctxt)) != 0 )
2067 goto done;
2068 dst.type = OP_NONE;
2069 break;
2070 case 7:
2071 generate_exception_if(1, EXC_UD, -1);
2072 default:
2073 goto cannot_emulate;
2075 break;
2078 writeback:
2079 switch ( dst.type )
2081 case OP_REG:
2082 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
2083 switch ( dst.bytes )
2085 case 1: *(uint8_t *)dst.reg = (uint8_t)dst.val; break;
2086 case 2: *(uint16_t *)dst.reg = (uint16_t)dst.val; break;
2087 case 4: *dst.reg = (uint32_t)dst.val; break; /* 64b: zero-ext */
2088 case 8: *dst.reg = dst.val; break;
2090 break;
2091 case OP_MEM:
2092 if ( !(d & Mov) && (dst.orig_val == dst.val) &&
2093 !ctxt->force_writeback )
2094 /* nothing to do */;
2095 else if ( lock_prefix )
2096 rc = ops->cmpxchg(
2097 dst.mem.seg, dst.mem.off, &dst.orig_val,
2098 &dst.val, dst.bytes, ctxt);
2099 else
2100 rc = ops->write(
2101 dst.mem.seg, dst.mem.off, dst.val, dst.bytes, ctxt);
2102 if ( rc != 0 )
2103 goto done;
2104 default:
2105 break;
2108 /* Inject #DB if single-step tracing was enabled at instruction start. */
2109 if ( (ctxt->regs->eflags & EFLG_TF) && (rc == X86EMUL_OKAY) &&
2110 (ops->inject_hw_exception != NULL) )
2111 rc = ops->inject_hw_exception(EXC_DB, -1, ctxt) ? : X86EMUL_EXCEPTION;
2113 /* Commit shadow register state. */
2114 _regs.eflags &= ~EFLG_RF;
2115 *ctxt->regs = _regs;
2117 done:
2118 return rc;
2120 special_insn:
2121 dst.type = OP_NONE;
2123 /*
2124 * The only implicit-operands instructions allowed a LOCK prefix are
2125 * CMPXCHG{8,16}B, MOV CRn, MOV DRn.
2126 */
2127 generate_exception_if(lock_prefix &&
2128 ((b < 0x20) || (b > 0x23)) && /* MOV CRn/DRn */
2129 (b != 0xc7), /* CMPXCHG{8,16}B */
2130 EXC_GP, 0);
2132 if ( twobyte )
2133 goto twobyte_special_insn;
2135 switch ( b )
2137 case 0x06: /* push %%es */ {
2138 struct segment_register reg;
2139 src.val = x86_seg_es;
2140 push_seg:
2141 fail_if(ops->read_segment == NULL);
2142 if ( (rc = ops->read_segment(src.val, &reg, ctxt)) != 0 )
2143 return rc;
2144 /* 64-bit mode: PUSH defaults to a 64-bit operand. */
2145 if ( mode_64bit() && (op_bytes == 4) )
2146 op_bytes = 8;
2147 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2148 reg.sel, op_bytes, ctxt)) != 0 )
2149 goto done;
2150 break;
2153 case 0x07: /* pop %%es */
2154 src.val = x86_seg_es;
2155 pop_seg:
2156 fail_if(ops->write_segment == NULL);
2157 /* 64-bit mode: POP defaults to a 64-bit operand. */
2158 if ( mode_64bit() && (op_bytes == 4) )
2159 op_bytes = 8;
2160 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2161 &dst.val, op_bytes, ctxt)) != 0 )
2162 goto done;
2163 if ( (rc = load_seg(src.val, (uint16_t)dst.val, ctxt, ops)) != 0 )
2164 return rc;
2165 break;
2167 case 0x0e: /* push %%cs */
2168 src.val = x86_seg_cs;
2169 goto push_seg;
2171 case 0x16: /* push %%ss */
2172 src.val = x86_seg_ss;
2173 goto push_seg;
2175 case 0x17: /* pop %%ss */
2176 src.val = x86_seg_ss;
2177 ctxt->retire.flags.mov_ss = 1;
2178 goto pop_seg;
2180 case 0x1e: /* push %%ds */
2181 src.val = x86_seg_ds;
2182 goto push_seg;
2184 case 0x1f: /* pop %%ds */
2185 src.val = x86_seg_ds;
2186 goto pop_seg;
2188 case 0x27: /* daa */ {
2189 uint8_t al = _regs.eax;
2190 unsigned long eflags = _regs.eflags;
2191 generate_exception_if(mode_64bit(), EXC_UD, -1);
2192 _regs.eflags &= ~(EFLG_CF|EFLG_AF);
2193 if ( ((al & 0x0f) > 9) || (eflags & EFLG_AF) )
2195 *(uint8_t *)&_regs.eax += 6;
2196 _regs.eflags |= EFLG_AF;
2198 if ( (al > 0x99) || (eflags & EFLG_CF) )
2200 *(uint8_t *)&_regs.eax += 0x60;
2201 _regs.eflags |= EFLG_CF;
2203 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2204 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2205 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2206 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2207 break;
2210 case 0x2f: /* das */ {
2211 uint8_t al = _regs.eax;
2212 unsigned long eflags = _regs.eflags;
2213 generate_exception_if(mode_64bit(), EXC_UD, -1);
2214 _regs.eflags &= ~(EFLG_CF|EFLG_AF);
2215 if ( ((al & 0x0f) > 9) || (eflags & EFLG_AF) )
2217 _regs.eflags |= EFLG_AF;
2218 if ( (al < 6) || (eflags & EFLG_CF) )
2219 _regs.eflags |= EFLG_CF;
2220 *(uint8_t *)&_regs.eax -= 6;
2222 if ( (al > 0x99) || (eflags & EFLG_CF) )
2224 *(uint8_t *)&_regs.eax -= 0x60;
2225 _regs.eflags |= EFLG_CF;
2227 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2228 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2229 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2230 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2231 break;
2234 case 0x37: /* aaa */
2235 case 0x3f: /* aas */
2236 generate_exception_if(mode_64bit(), EXC_UD, -1);
2237 _regs.eflags &= ~EFLG_CF;
2238 if ( ((uint8_t)_regs.eax > 9) || (_regs.eflags & EFLG_AF) )
2240 ((uint8_t *)&_regs.eax)[0] += (b == 0x37) ? 6 : -6;
2241 ((uint8_t *)&_regs.eax)[1] += (b == 0x37) ? 1 : -1;
2242 _regs.eflags |= EFLG_CF | EFLG_AF;
2244 ((uint8_t *)&_regs.eax)[0] &= 0x0f;
2245 break;
2247 case 0x40 ... 0x4f: /* inc/dec reg */
2248 dst.type = OP_REG;
2249 dst.reg = decode_register(b & 7, &_regs, 0);
2250 dst.bytes = op_bytes;
2251 dst.val = *dst.reg;
2252 if ( b & 8 )
2253 emulate_1op("dec", dst, _regs.eflags);
2254 else
2255 emulate_1op("inc", dst, _regs.eflags);
2256 break;
2258 case 0x50 ... 0x57: /* push reg */
2259 src.val = *(unsigned long *)decode_register(
2260 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2261 goto push;
2263 case 0x58 ... 0x5f: /* pop reg */
2264 dst.type = OP_REG;
2265 dst.reg = decode_register(
2266 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2267 dst.bytes = op_bytes;
2268 if ( mode_64bit() && (dst.bytes == 4) )
2269 dst.bytes = 8;
2270 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
2271 &dst.val, dst.bytes, ctxt)) != 0 )
2272 goto done;
2273 break;
2275 case 0x60: /* pusha */ {
2276 int i;
2277 unsigned long regs[] = {
2278 _regs.eax, _regs.ecx, _regs.edx, _regs.ebx,
2279 _regs.esp, _regs.ebp, _regs.esi, _regs.edi };
2280 generate_exception_if(mode_64bit(), EXC_UD, -1);
2281 for ( i = 0; i < 8; i++ )
2282 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2283 regs[i], op_bytes, ctxt)) != 0 )
2284 goto done;
2285 break;
2288 case 0x61: /* popa */ {
2289 int i;
2290 unsigned long dummy_esp, *regs[] = {
2291 (unsigned long *)&_regs.edi, (unsigned long *)&_regs.esi,
2292 (unsigned long *)&_regs.ebp, (unsigned long *)&dummy_esp,
2293 (unsigned long *)&_regs.ebx, (unsigned long *)&_regs.edx,
2294 (unsigned long *)&_regs.ecx, (unsigned long *)&_regs.eax };
2295 generate_exception_if(mode_64bit(), EXC_UD, -1);
2296 for ( i = 0; i < 8; i++ )
2298 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2299 &dst.val, op_bytes, ctxt)) != 0 )
2300 goto done;
2301 switch ( op_bytes )
2303 case 1: *(uint8_t *)regs[i] = (uint8_t)dst.val; break;
2304 case 2: *(uint16_t *)regs[i] = (uint16_t)dst.val; break;
2305 case 4: *regs[i] = (uint32_t)dst.val; break; /* 64b: zero-ext */
2306 case 8: *regs[i] = dst.val; break;
2309 break;
2312 case 0x68: /* push imm{16,32,64} */
2313 src.val = ((op_bytes == 2)
2314 ? (int32_t)insn_fetch_type(int16_t)
2315 : insn_fetch_type(int32_t));
2316 goto push;
2318 case 0x6a: /* push imm8 */
2319 src.val = insn_fetch_type(int8_t);
2320 push:
2321 d |= Mov; /* force writeback */
2322 dst.type = OP_MEM;
2323 dst.bytes = op_bytes;
2324 if ( mode_64bit() && (dst.bytes == 4) )
2325 dst.bytes = 8;
2326 dst.val = src.val;
2327 dst.mem.seg = x86_seg_ss;
2328 dst.mem.off = sp_pre_dec(dst.bytes);
2329 break;
2331 case 0x6c ... 0x6d: /* ins %dx,%es:%edi */ {
2332 unsigned long nr_reps = get_rep_prefix();
2333 unsigned int port = (uint16_t)_regs.edx;
2334 dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2335 dst.mem.seg = x86_seg_es;
2336 dst.mem.off = truncate_ea(_regs.edi);
2337 if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
2338 goto done;
2339 if ( (nr_reps > 1) && (ops->rep_ins != NULL) &&
2340 ((rc = ops->rep_ins(port, dst.mem.seg, dst.mem.off, dst.bytes,
2341 &nr_reps, ctxt)) != X86EMUL_UNHANDLEABLE) )
2343 if ( rc != 0 )
2344 goto done;
2346 else
2348 fail_if(ops->read_io == NULL);
2349 if ( (rc = ops->read_io(port, dst.bytes, &dst.val, ctxt)) != 0 )
2350 goto done;
2351 dst.type = OP_MEM;
2352 nr_reps = 1;
2354 register_address_increment(
2355 _regs.edi,
2356 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2357 put_rep_prefix(nr_reps);
2358 break;
2361 case 0x6e ... 0x6f: /* outs %esi,%dx */ {
2362 unsigned long nr_reps = get_rep_prefix();
2363 unsigned int port = (uint16_t)_regs.edx;
2364 dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2365 if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
2366 goto done;
2367 if ( (nr_reps > 1) && (ops->rep_outs != NULL) &&
2368 ((rc = ops->rep_outs(ea.mem.seg, truncate_ea(_regs.esi),
2369 port, dst.bytes,
2370 &nr_reps, ctxt)) != X86EMUL_UNHANDLEABLE) )
2372 if ( rc != 0 )
2373 goto done;
2375 else
2377 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2378 &dst.val, dst.bytes, ctxt)) != 0 )
2379 goto done;
2380 fail_if(ops->write_io == NULL);
2381 if ( (rc = ops->write_io(port, dst.bytes, dst.val, ctxt)) != 0 )
2382 goto done;
2383 nr_reps = 1;
2385 register_address_increment(
2386 _regs.esi,
2387 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2388 put_rep_prefix(nr_reps);
2389 break;
2392 case 0x70 ... 0x7f: /* jcc (short) */ {
2393 int rel = insn_fetch_type(int8_t);
2394 if ( test_cc(b, _regs.eflags) )
2395 jmp_rel(rel);
2396 break;
2399 case 0x90: /* nop / xchg %%r8,%%rax */
2400 if ( !(rex_prefix & 1) )
2401 break; /* nop */
2403 case 0x91 ... 0x97: /* xchg reg,%%rax */
2404 src.type = dst.type = OP_REG;
2405 src.bytes = dst.bytes = op_bytes;
2406 src.reg = (unsigned long *)&_regs.eax;
2407 src.val = *src.reg;
2408 dst.reg = decode_register(
2409 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2410 dst.val = *dst.reg;
2411 goto xchg;
2413 case 0x98: /* cbw/cwde/cdqe */
2414 switch ( op_bytes )
2416 case 2: *(int16_t *)&_regs.eax = (int8_t)_regs.eax; break; /* cbw */
2417 case 4: _regs.eax = (uint32_t)(int16_t)_regs.eax; break; /* cwde */
2418 case 8: _regs.eax = (int32_t)_regs.eax; break; /* cdqe */
2420 break;
2422 case 0x99: /* cwd/cdq/cqo */
2423 switch ( op_bytes )
2425 case 2:
2426 *(int16_t *)&_regs.edx = ((int16_t)_regs.eax < 0) ? -1 : 0;
2427 break;
2428 case 4:
2429 _regs.edx = (uint32_t)(((int32_t)_regs.eax < 0) ? -1 : 0);
2430 break;
2431 case 8:
2432 _regs.edx = (_regs.eax < 0) ? -1 : 0;
2433 break;
2435 break;
2437 case 0x9a: /* call (far, absolute) */ {
2438 struct segment_register reg;
2439 uint16_t sel;
2440 uint32_t eip;
2442 fail_if(ops->read_segment == NULL);
2443 generate_exception_if(mode_64bit(), EXC_UD, -1);
2445 eip = insn_fetch_bytes(op_bytes);
2446 sel = insn_fetch_type(uint16_t);
2448 if ( (rc = ops->read_segment(x86_seg_cs, &reg, ctxt)) ||
2449 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2450 reg.sel, op_bytes, ctxt)) ||
2451 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2452 _regs.eip, op_bytes, ctxt)) )
2453 goto done;
2455 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2456 goto done;
2457 _regs.eip = eip;
2458 break;
2461 case 0x9b: /* wait/fwait */
2462 emulate_fpu_insn("fwait");
2463 break;
2465 case 0x9c: /* pushf */
2466 src.val = _regs.eflags;
2467 goto push;
2469 case 0x9d: /* popf */ {
2470 uint32_t mask = EFLG_VIP | EFLG_VIF | EFLG_VM;
2471 if ( !mode_ring0() )
2472 mask |= EFLG_IOPL;
2473 if ( !mode_iopl() )
2474 mask |= EFLG_IF;
2475 /* 64-bit mode: POP defaults to a 64-bit operand. */
2476 if ( mode_64bit() && (op_bytes == 4) )
2477 op_bytes = 8;
2478 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2479 &dst.val, op_bytes, ctxt)) != 0 )
2480 goto done;
2481 if ( op_bytes == 2 )
2482 dst.val = (uint16_t)dst.val | (_regs.eflags & 0xffff0000u);
2483 dst.val &= 0x257fd5;
2484 _regs.eflags &= mask;
2485 _regs.eflags |= (uint32_t)(dst.val & ~mask) | 0x02;
2486 break;
2489 case 0x9e: /* sahf */
2490 *(uint8_t *)&_regs.eflags = (((uint8_t *)&_regs.eax)[1] & 0xd7) | 0x02;
2491 break;
2493 case 0x9f: /* lahf */
2494 ((uint8_t *)&_regs.eax)[1] = (_regs.eflags & 0xd7) | 0x02;
2495 break;
2497 case 0xa0 ... 0xa1: /* mov mem.offs,{%al,%ax,%eax,%rax} */
2498 /* Source EA is not encoded via ModRM. */
2499 dst.type = OP_REG;
2500 dst.reg = (unsigned long *)&_regs.eax;
2501 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2502 if ( (rc = ops->read(ea.mem.seg, insn_fetch_bytes(ad_bytes),
2503 &dst.val, dst.bytes, ctxt)) != 0 )
2504 goto done;
2505 break;
2507 case 0xa2 ... 0xa3: /* mov {%al,%ax,%eax,%rax},mem.offs */
2508 /* Destination EA is not encoded via ModRM. */
2509 dst.type = OP_MEM;
2510 dst.mem.seg = ea.mem.seg;
2511 dst.mem.off = insn_fetch_bytes(ad_bytes);
2512 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2513 dst.val = (unsigned long)_regs.eax;
2514 break;
2516 case 0xa4 ... 0xa5: /* movs */ {
2517 unsigned long nr_reps = get_rep_prefix();
2518 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2519 dst.mem.seg = x86_seg_es;
2520 dst.mem.off = truncate_ea(_regs.edi);
2521 if ( (nr_reps > 1) && (ops->rep_movs != NULL) &&
2522 ((rc = ops->rep_movs(ea.mem.seg, truncate_ea(_regs.esi),
2523 dst.mem.seg, dst.mem.off, dst.bytes,
2524 &nr_reps, ctxt)) != X86EMUL_UNHANDLEABLE) )
2526 if ( rc != 0 )
2527 goto done;
2529 else
2531 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2532 &dst.val, dst.bytes, ctxt)) != 0 )
2533 goto done;
2534 dst.type = OP_MEM;
2535 nr_reps = 1;
2537 register_address_increment(
2538 _regs.esi,
2539 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2540 register_address_increment(
2541 _regs.edi,
2542 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2543 put_rep_prefix(nr_reps);
2544 break;
2547 case 0xa6 ... 0xa7: /* cmps */ {
2548 unsigned long next_eip = _regs.eip;
2549 get_rep_prefix();
2550 src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2551 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2552 &dst.val, dst.bytes, ctxt)) ||
2553 (rc = ops->read(x86_seg_es, truncate_ea(_regs.edi),
2554 &src.val, src.bytes, ctxt)) )
2555 goto done;
2556 register_address_increment(
2557 _regs.esi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2558 register_address_increment(
2559 _regs.edi, (_regs.eflags & EFLG_DF) ? -src.bytes : src.bytes);
2560 put_rep_prefix(1);
2561 /* cmp: dst - src ==> src=*%%edi,dst=*%%esi ==> *%%esi - *%%edi */
2562 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2563 if ( ((rep_prefix == REPE_PREFIX) && !(_regs.eflags & EFLG_ZF)) ||
2564 ((rep_prefix == REPNE_PREFIX) && (_regs.eflags & EFLG_ZF)) )
2565 _regs.eip = next_eip;
2566 break;
2569 case 0xaa ... 0xab: /* stos */ {
2570 /* unsigned long max_reps = */get_rep_prefix();
2571 dst.type = OP_MEM;
2572 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2573 dst.mem.seg = x86_seg_es;
2574 dst.mem.off = truncate_ea(_regs.edi);
2575 dst.val = _regs.eax;
2576 register_address_increment(
2577 _regs.edi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2578 put_rep_prefix(1);
2579 break;
2582 case 0xac ... 0xad: /* lods */ {
2583 /* unsigned long max_reps = */get_rep_prefix();
2584 dst.type = OP_REG;
2585 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2586 dst.reg = (unsigned long *)&_regs.eax;
2587 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2588 &dst.val, dst.bytes, ctxt)) != 0 )
2589 goto done;
2590 register_address_increment(
2591 _regs.esi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2592 put_rep_prefix(1);
2593 break;
2596 case 0xae ... 0xaf: /* scas */ {
2597 unsigned long next_eip = _regs.eip;
2598 get_rep_prefix();
2599 src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2600 dst.val = _regs.eax;
2601 if ( (rc = ops->read(x86_seg_es, truncate_ea(_regs.edi),
2602 &src.val, src.bytes, ctxt)) != 0 )
2603 goto done;
2604 register_address_increment(
2605 _regs.edi, (_regs.eflags & EFLG_DF) ? -src.bytes : src.bytes);
2606 put_rep_prefix(1);
2607 /* cmp: dst - src ==> src=*%%edi,dst=%%eax ==> %%eax - *%%edi */
2608 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2609 if ( ((rep_prefix == REPE_PREFIX) && !(_regs.eflags & EFLG_ZF)) ||
2610 ((rep_prefix == REPNE_PREFIX) && (_regs.eflags & EFLG_ZF)) )
2611 _regs.eip = next_eip;
2612 break;
2615 case 0xc2: /* ret imm16 (near) */
2616 case 0xc3: /* ret (near) */ {
2617 int offset = (b == 0xc2) ? insn_fetch_type(uint16_t) : 0;
2618 op_bytes = mode_64bit() ? 8 : op_bytes;
2619 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes + offset),
2620 &dst.val, op_bytes, ctxt)) != 0 )
2621 goto done;
2622 _regs.eip = dst.val;
2623 break;
2626 case 0xc8: /* enter imm16,imm8 */ {
2627 uint16_t size = insn_fetch_type(uint16_t);
2628 uint8_t depth = insn_fetch_type(uint8_t) & 31;
2629 int i;
2631 dst.type = OP_REG;
2632 dst.bytes = (mode_64bit() && (op_bytes == 4)) ? 8 : op_bytes;
2633 dst.reg = (unsigned long *)&_regs.ebp;
2634 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2635 _regs.ebp, dst.bytes, ctxt)) )
2636 goto done;
2637 dst.val = _regs.esp;
2639 if ( depth > 0 )
2641 for ( i = 1; i < depth; i++ )
2643 unsigned long ebp, temp_data;
2644 ebp = truncate_word(_regs.ebp - i*dst.bytes, ctxt->sp_size/8);
2645 if ( (rc = ops->read(x86_seg_ss, ebp,
2646 &temp_data, dst.bytes, ctxt)) ||
2647 (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2648 temp_data, dst.bytes, ctxt)) )
2649 goto done;
2651 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2652 dst.val, dst.bytes, ctxt)) )
2653 goto done;
2656 sp_pre_dec(size);
2657 break;
2660 case 0xc9: /* leave */
2661 /* First writeback, to %%esp. */
2662 dst.type = OP_REG;
2663 dst.bytes = (mode_64bit() && (op_bytes == 4)) ? 8 : op_bytes;
2664 dst.reg = (unsigned long *)&_regs.esp;
2665 dst.val = _regs.ebp;
2667 /* Flush first writeback, since there is a second. */
2668 switch ( dst.bytes )
2670 case 1: *(uint8_t *)dst.reg = (uint8_t)dst.val; break;
2671 case 2: *(uint16_t *)dst.reg = (uint16_t)dst.val; break;
2672 case 4: *dst.reg = (uint32_t)dst.val; break; /* 64b: zero-ext */
2673 case 8: *dst.reg = dst.val; break;
2676 /* Second writeback, to %%ebp. */
2677 dst.reg = (unsigned long *)&_regs.ebp;
2678 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
2679 &dst.val, dst.bytes, ctxt)) )
2680 goto done;
2681 break;
2683 case 0xca: /* ret imm16 (far) */
2684 case 0xcb: /* ret (far) */ {
2685 int offset = (b == 0xca) ? insn_fetch_type(uint16_t) : 0;
2686 op_bytes = mode_64bit() ? 8 : op_bytes;
2687 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2688 &dst.val, op_bytes, ctxt)) ||
2689 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes + offset),
2690 &src.val, op_bytes, ctxt)) ||
2691 (rc = load_seg(x86_seg_cs, (uint16_t)src.val, ctxt, ops)) )
2692 goto done;
2693 _regs.eip = dst.val;
2694 break;
2697 case 0xcc: /* int3 */
2698 src.val = EXC_BP;
2699 goto swint;
2701 case 0xcd: /* int imm8 */
2702 src.val = insn_fetch_type(uint8_t);
2703 swint:
2704 fail_if(ops->inject_sw_interrupt == NULL);
2705 rc = ops->inject_sw_interrupt(src.val, _regs.eip - ctxt->regs->eip,
2706 ctxt) ? : X86EMUL_EXCEPTION;
2707 goto done;
2709 case 0xce: /* into */
2710 generate_exception_if(mode_64bit(), EXC_UD, -1);
2711 if ( !(_regs.eflags & EFLG_OF) )
2712 break;
2713 src.val = EXC_OF;
2714 goto swint;
2716 case 0xcf: /* iret */ {
2717 unsigned long cs, eip, eflags;
2718 uint32_t mask = EFLG_VIP | EFLG_VIF | EFLG_VM;
2719 if ( !mode_ring0() )
2720 mask |= EFLG_IOPL;
2721 if ( !mode_iopl() )
2722 mask |= EFLG_IF;
2723 fail_if(!in_realmode(ctxt, ops));
2724 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2725 &eip, op_bytes, ctxt)) ||
2726 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2727 &cs, op_bytes, ctxt)) ||
2728 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2729 &eflags, op_bytes, ctxt)) )
2730 goto done;
2731 if ( op_bytes == 2 )
2732 eflags = (uint16_t)eflags | (_regs.eflags & 0xffff0000u);
2733 eflags &= 0x257fd5;
2734 _regs.eflags &= mask;
2735 _regs.eflags |= (uint32_t)(eflags & ~mask) | 0x02;
2736 _regs.eip = eip;
2737 if ( (rc = load_seg(x86_seg_cs, (uint16_t)cs, ctxt, ops)) != 0 )
2738 goto done;
2739 break;
2742 case 0xd4: /* aam */ {
2743 unsigned int base = insn_fetch_type(uint8_t);
2744 uint8_t al = _regs.eax;
2745 generate_exception_if(mode_64bit(), EXC_UD, -1);
2746 generate_exception_if(base == 0, EXC_DE, -1);
2747 *(uint16_t *)&_regs.eax = ((al / base) << 8) | (al % base);
2748 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2749 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2750 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2751 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2752 break;
2755 case 0xd5: /* aad */ {
2756 unsigned int base = insn_fetch_type(uint8_t);
2757 uint16_t ax = _regs.eax;
2758 generate_exception_if(mode_64bit(), EXC_UD, -1);
2759 *(uint16_t *)&_regs.eax = (uint8_t)(ax + ((ax >> 8) * base));
2760 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2761 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2762 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2763 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2764 break;
2767 case 0xd6: /* salc */
2768 generate_exception_if(mode_64bit(), EXC_UD, -1);
2769 *(uint8_t *)&_regs.eax = (_regs.eflags & EFLG_CF) ? 0xff : 0x00;
2770 break;
2772 case 0xd7: /* xlat */ {
2773 unsigned long al = (uint8_t)_regs.eax;
2774 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.ebx + al),
2775 &al, 1, ctxt)) != 0 )
2776 goto done;
2777 *(uint8_t *)&_regs.eax = al;
2778 break;
2781 case 0xd9: /* FPU 0xd9 */
2782 switch ( modrm )
2784 case 0xc0 ... 0xc7: /* fld %stN */
2785 case 0xc8 ... 0xcf: /* fxch %stN */
2786 case 0xd0: /* fnop */
2787 case 0xe0: /* fchs */
2788 case 0xe1: /* fabs */
2789 case 0xe4: /* ftst */
2790 case 0xe5: /* fxam */
2791 case 0xe8: /* fld1 */
2792 case 0xe9: /* fldl2t */
2793 case 0xea: /* fldl2e */
2794 case 0xeb: /* fldpi */
2795 case 0xec: /* fldlg2 */
2796 case 0xed: /* fldln2 */
2797 case 0xee: /* fldz */
2798 case 0xf0: /* f2xm1 */
2799 case 0xf1: /* fyl2x */
2800 case 0xf2: /* fptan */
2801 case 0xf3: /* fpatan */
2802 case 0xf4: /* fxtract */
2803 case 0xf5: /* fprem1 */
2804 case 0xf6: /* fdecstp */
2805 case 0xf7: /* fincstp */
2806 case 0xf8: /* fprem */
2807 case 0xf9: /* fyl2xp1 */
2808 case 0xfa: /* fsqrt */
2809 case 0xfb: /* fsincos */
2810 case 0xfc: /* frndint */
2811 case 0xfd: /* fscale */
2812 case 0xfe: /* fsin */
2813 case 0xff: /* fcos */
2814 emulate_fpu_insn_stub(0xd9, modrm);
2815 break;
2816 default:
2817 fail_if((modrm_reg & 7) != 7);
2818 fail_if(modrm >= 0xc0);
2819 /* fnstcw m2byte */
2820 ea.bytes = 2;
2821 dst = ea;
2822 emulate_fpu_insn_memdst("fnstcw", dst.val);
2824 break;
2826 case 0xdb: /* FPU 0xdb */
2827 fail_if(modrm != 0xe3);
2828 /* fninit */
2829 emulate_fpu_insn("fninit");
2830 break;
2832 case 0xdd: /* FPU 0xdd */
2833 fail_if((modrm_reg & 7) != 7);
2834 fail_if(modrm >= 0xc0);
2835 /* fnstsw m2byte */
2836 ea.bytes = 2;
2837 dst = ea;
2838 emulate_fpu_insn_memdst("fnstsw", dst.val);
2839 break;
2841 case 0xde: /* FPU 0xde */
2842 switch ( modrm )
2844 case 0xc0 ... 0xc7: /* faddp %stN */
2845 case 0xc8 ... 0xcf: /* fmulp %stN */
2846 case 0xd9: /* fcompp */
2847 case 0xe0 ... 0xe7: /* fsubrp %stN */
2848 case 0xe8 ... 0xef: /* fsubp %stN */
2849 case 0xf0 ... 0xf7: /* fdivrp %stN */
2850 case 0xf8 ... 0xff: /* fdivp %stN */
2851 emulate_fpu_insn_stub(0xde, modrm);
2852 break;
2853 default:
2854 goto cannot_emulate;
2856 break;
2858 case 0xdf: /* FPU 0xdf */
2859 fail_if(modrm != 0xe0);
2860 /* fnstsw %ax */
2861 dst.bytes = 2;
2862 dst.type = OP_REG;
2863 dst.reg = (unsigned long *)&_regs.eax;
2864 emulate_fpu_insn_memdst("fnstsw", dst.val);
2865 break;
2867 case 0xe0 ... 0xe2: /* loop{,z,nz} */ {
2868 int rel = insn_fetch_type(int8_t);
2869 int do_jmp = !(_regs.eflags & EFLG_ZF); /* loopnz */
2870 if ( b == 0xe1 )
2871 do_jmp = !do_jmp; /* loopz */
2872 else if ( b == 0xe2 )
2873 do_jmp = 1; /* loop */
2874 switch ( ad_bytes )
2876 case 2:
2877 do_jmp &= --(*(uint16_t *)&_regs.ecx) != 0;
2878 break;
2879 case 4:
2880 do_jmp &= --(*(uint32_t *)&_regs.ecx) != 0;
2881 _regs.ecx = (uint32_t)_regs.ecx; /* zero extend in x86/64 mode */
2882 break;
2883 default: /* case 8: */
2884 do_jmp &= --_regs.ecx != 0;
2885 break;
2887 if ( do_jmp )
2888 jmp_rel(rel);
2889 break;
2892 case 0xe3: /* jcxz/jecxz (short) */ {
2893 int rel = insn_fetch_type(int8_t);
2894 if ( (ad_bytes == 2) ? !(uint16_t)_regs.ecx :
2895 (ad_bytes == 4) ? !(uint32_t)_regs.ecx : !_regs.ecx )
2896 jmp_rel(rel);
2897 break;
2900 case 0xe4: /* in imm8,%al */
2901 case 0xe5: /* in imm8,%eax */
2902 case 0xe6: /* out %al,imm8 */
2903 case 0xe7: /* out %eax,imm8 */
2904 case 0xec: /* in %dx,%al */
2905 case 0xed: /* in %dx,%eax */
2906 case 0xee: /* out %al,%dx */
2907 case 0xef: /* out %eax,%dx */ {
2908 unsigned int port = ((b < 0xe8)
2909 ? insn_fetch_type(uint8_t)
2910 : (uint16_t)_regs.edx);
2911 op_bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2912 if ( (rc = ioport_access_check(port, op_bytes, ctxt, ops)) != 0 )
2913 goto done;
2914 if ( b & 2 )
2916 /* out */
2917 fail_if(ops->write_io == NULL);
2918 rc = ops->write_io(port, op_bytes, _regs.eax, ctxt);
2921 else
2923 /* in */
2924 dst.type = OP_REG;
2925 dst.bytes = op_bytes;
2926 dst.reg = (unsigned long *)&_regs.eax;
2927 fail_if(ops->read_io == NULL);
2928 rc = ops->read_io(port, dst.bytes, &dst.val, ctxt);
2930 if ( rc != 0 )
2931 goto done;
2932 break;
2935 case 0xe8: /* call (near) */ {
2936 int rel = (((op_bytes == 2) && !mode_64bit())
2937 ? (int32_t)insn_fetch_type(int16_t)
2938 : insn_fetch_type(int32_t));
2939 op_bytes = mode_64bit() ? 8 : op_bytes;
2940 src.val = _regs.eip;
2941 jmp_rel(rel);
2942 goto push;
2945 case 0xe9: /* jmp (near) */ {
2946 int rel = (((op_bytes == 2) && !mode_64bit())
2947 ? (int32_t)insn_fetch_type(int16_t)
2948 : insn_fetch_type(int32_t));
2949 jmp_rel(rel);
2950 break;
2953 case 0xea: /* jmp (far, absolute) */ {
2954 uint16_t sel;
2955 uint32_t eip;
2956 generate_exception_if(mode_64bit(), EXC_UD, -1);
2957 eip = insn_fetch_bytes(op_bytes);
2958 sel = insn_fetch_type(uint16_t);
2959 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2960 goto done;
2961 _regs.eip = eip;
2962 break;
2965 case 0xeb: /* jmp (short) */ {
2966 int rel = insn_fetch_type(int8_t);
2967 jmp_rel(rel);
2968 break;
2971 case 0xf1: /* int1 (icebp) */
2972 src.val = EXC_DB;
2973 goto swint;
2975 case 0xf4: /* hlt */
2976 ctxt->retire.flags.hlt = 1;
2977 break;
2979 case 0xf5: /* cmc */
2980 _regs.eflags ^= EFLG_CF;
2981 break;
2983 case 0xf8: /* clc */
2984 _regs.eflags &= ~EFLG_CF;
2985 break;
2987 case 0xf9: /* stc */
2988 _regs.eflags |= EFLG_CF;
2989 break;
2991 case 0xfa: /* cli */
2992 generate_exception_if(!mode_iopl(), EXC_GP, 0);
2993 _regs.eflags &= ~EFLG_IF;
2994 break;
2996 case 0xfb: /* sti */
2997 generate_exception_if(!mode_iopl(), EXC_GP, 0);
2998 if ( !(_regs.eflags & EFLG_IF) )
3000 _regs.eflags |= EFLG_IF;
3001 ctxt->retire.flags.sti = 1;
3003 break;
3005 case 0xfc: /* cld */
3006 _regs.eflags &= ~EFLG_DF;
3007 break;
3009 case 0xfd: /* std */
3010 _regs.eflags |= EFLG_DF;
3011 break;
3013 goto writeback;
3015 twobyte_insn:
3016 switch ( b )
3018 case 0x40 ... 0x4f: /* cmovcc */
3019 dst.val = src.val;
3020 if ( !test_cc(b, _regs.eflags) )
3021 dst.type = OP_NONE;
3022 break;
3024 case 0x90 ... 0x9f: /* setcc */
3025 dst.val = test_cc(b, _regs.eflags);
3026 break;
3028 case 0xb0 ... 0xb1: /* cmpxchg */
3029 /* Save real source value, then compare EAX against destination. */
3030 src.orig_val = src.val;
3031 src.val = _regs.eax;
3032 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
3033 if ( _regs.eflags & EFLG_ZF )
3035 /* Success: write back to memory. */
3036 dst.val = src.orig_val;
3038 else
3040 /* Failure: write the value we saw to EAX. */
3041 dst.type = OP_REG;
3042 dst.reg = (unsigned long *)&_regs.eax;
3044 break;
3046 case 0xa3: bt: /* bt */
3047 emulate_2op_SrcV_nobyte("bt", src, dst, _regs.eflags);
3048 dst.type = OP_NONE;
3049 break;
3051 case 0xa4: /* shld imm8,r,r/m */
3052 case 0xa5: /* shld %%cl,r,r/m */
3053 case 0xac: /* shrd imm8,r,r/m */
3054 case 0xad: /* shrd %%cl,r,r/m */ {
3055 uint8_t shift, width = dst.bytes << 3;
3056 shift = (b & 1) ? (uint8_t)_regs.ecx : insn_fetch_type(uint8_t);
3057 if ( (shift &= width - 1) == 0 )
3058 break;
3059 dst.orig_val = truncate_word(dst.val, dst.bytes);
3060 dst.val = ((shift == width) ? src.val :
3061 (b & 8) ?
3062 /* shrd */
3063 ((dst.orig_val >> shift) |
3064 truncate_word(src.val << (width - shift), dst.bytes)) :
3065 /* shld */
3066 ((dst.orig_val << shift) |
3067 ((src.val >> (width - shift)) & ((1ull << shift) - 1))));
3068 dst.val = truncate_word(dst.val, dst.bytes);
3069 _regs.eflags &= ~(EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_PF|EFLG_CF);
3070 if ( (dst.val >> ((b & 8) ? (shift - 1) : (width - shift))) & 1 )
3071 _regs.eflags |= EFLG_CF;
3072 if ( ((dst.val ^ dst.orig_val) >> (width - 1)) & 1 )
3073 _regs.eflags |= EFLG_OF;
3074 _regs.eflags |= ((dst.val >> (width - 1)) & 1) ? EFLG_SF : 0;
3075 _regs.eflags |= (dst.val == 0) ? EFLG_ZF : 0;
3076 _regs.eflags |= even_parity(dst.val) ? EFLG_PF : 0;
3077 break;
3080 case 0xb3: btr: /* btr */
3081 emulate_2op_SrcV_nobyte("btr", src, dst, _regs.eflags);
3082 break;
3084 case 0xab: bts: /* bts */
3085 emulate_2op_SrcV_nobyte("bts", src, dst, _regs.eflags);
3086 break;
3088 case 0xaf: /* imul */
3089 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
3090 switch ( dst.bytes )
3092 case 2:
3093 dst.val = ((uint32_t)(int16_t)src.val *
3094 (uint32_t)(int16_t)dst.val);
3095 if ( (int16_t)dst.val != (uint32_t)dst.val )
3096 _regs.eflags |= EFLG_OF|EFLG_CF;
3097 break;
3098 #ifdef __x86_64__
3099 case 4:
3100 dst.val = ((uint64_t)(int32_t)src.val *
3101 (uint64_t)(int32_t)dst.val);
3102 if ( (int32_t)dst.val != dst.val )
3103 _regs.eflags |= EFLG_OF|EFLG_CF;
3104 break;
3105 #endif
3106 default: {
3107 unsigned long m[2] = { src.val, dst.val };
3108 if ( imul_dbl(m) )
3109 _regs.eflags |= EFLG_OF|EFLG_CF;
3110 dst.val = m[0];
3111 break;
3114 break;
3116 case 0xb2: /* lss */
3117 dst.val = x86_seg_ss;
3118 goto les;
3120 case 0xb4: /* lfs */
3121 dst.val = x86_seg_fs;
3122 goto les;
3124 case 0xb5: /* lgs */
3125 dst.val = x86_seg_gs;
3126 goto les;
3128 case 0xb6: /* movzx rm8,r{16,32,64} */
3129 /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */
3130 dst.reg = decode_register(modrm_reg, &_regs, 0);
3131 dst.bytes = op_bytes;
3132 dst.val = (uint8_t)src.val;
3133 break;
3135 case 0xbc: /* bsf */ {
3136 int zf;
3137 asm ( "bsf %2,%0; setz %b1"
3138 : "=r" (dst.val), "=q" (zf)
3139 : "r" (src.val), "1" (0) );
3140 _regs.eflags &= ~EFLG_ZF;
3141 if ( zf )
3143 _regs.eflags |= EFLG_ZF;
3144 dst.type = OP_NONE;
3146 break;
3149 case 0xbd: /* bsr */ {
3150 int zf;
3151 asm ( "bsr %2,%0; setz %b1"
3152 : "=r" (dst.val), "=q" (zf)
3153 : "r" (src.val), "1" (0) );
3154 _regs.eflags &= ~EFLG_ZF;
3155 if ( zf )
3157 _regs.eflags |= EFLG_ZF;
3158 dst.type = OP_NONE;
3160 break;
3163 case 0xb7: /* movzx rm16,r{16,32,64} */
3164 dst.val = (uint16_t)src.val;
3165 break;
3167 case 0xbb: btc: /* btc */
3168 emulate_2op_SrcV_nobyte("btc", src, dst, _regs.eflags);
3169 break;
3171 case 0xba: /* Grp8 */
3172 switch ( modrm_reg & 7 )
3174 case 4: goto bt;
3175 case 5: goto bts;
3176 case 6: goto btr;
3177 case 7: goto btc;
3178 default: generate_exception_if(1, EXC_UD, -1);
3180 break;
3182 case 0xbe: /* movsx rm8,r{16,32,64} */
3183 /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */
3184 dst.reg = decode_register(modrm_reg, &_regs, 0);
3185 dst.bytes = op_bytes;
3186 dst.val = (int8_t)src.val;
3187 break;
3189 case 0xbf: /* movsx rm16,r{16,32,64} */
3190 dst.val = (int16_t)src.val;
3191 break;
3193 case 0xc0 ... 0xc1: /* xadd */
3194 /* Write back the register source. */
3195 switch ( dst.bytes )
3197 case 1: *(uint8_t *)src.reg = (uint8_t)dst.val; break;
3198 case 2: *(uint16_t *)src.reg = (uint16_t)dst.val; break;
3199 case 4: *src.reg = (uint32_t)dst.val; break; /* 64b reg: zero-extend */
3200 case 8: *src.reg = dst.val; break;
3202 goto add;
3204 goto writeback;
3206 twobyte_special_insn:
3207 switch ( b )
3209 case 0x01: /* Grp7 */ {
3210 struct segment_register reg;
3211 unsigned long base, limit, cr0, cr0w;
3213 if ( modrm == 0xdf ) /* invlpga */
3215 generate_exception_if(in_realmode(ctxt, ops), EXC_UD, -1);
3216 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3217 fail_if(ops->invlpg == NULL);
3218 if ( (rc = ops->invlpg(x86_seg_none, truncate_ea(_regs.eax),
3219 ctxt)) )
3220 goto done;
3221 break;
3224 switch ( modrm_reg & 7 )
3226 case 0: /* sgdt */
3227 case 1: /* sidt */
3228 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3229 fail_if(ops->read_segment == NULL);
3230 if ( (rc = ops->read_segment((modrm_reg & 1) ?
3231 x86_seg_idtr : x86_seg_gdtr,
3232 &reg, ctxt)) )
3233 goto done;
3234 if ( op_bytes == 2 )
3235 reg.base &= 0xffffff;
3236 if ( (rc = ops->write(ea.mem.seg, ea.mem.off+0,
3237 reg.limit, 2, ctxt)) ||
3238 (rc = ops->write(ea.mem.seg, ea.mem.off+2,
3239 reg.base, mode_64bit() ? 8 : 4, ctxt)) )
3240 goto done;
3241 break;
3242 case 2: /* lgdt */
3243 case 3: /* lidt */
3244 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3245 fail_if(ops->write_segment == NULL);
3246 memset(&reg, 0, sizeof(reg));
3247 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0,
3248 &limit, 2, ctxt)) ||
3249 (rc = ops->read(ea.mem.seg, ea.mem.off+2,
3250 &base, mode_64bit() ? 8 : 4, ctxt)) )
3251 goto done;
3252 reg.base = base;
3253 reg.limit = limit;
3254 if ( op_bytes == 2 )
3255 reg.base &= 0xffffff;
3256 if ( (rc = ops->write_segment((modrm_reg & 1) ?
3257 x86_seg_idtr : x86_seg_gdtr,
3258 &reg, ctxt)) )
3259 goto done;
3260 break;
3261 case 4: /* smsw */
3262 ea.bytes = 2;
3263 dst = ea;
3264 fail_if(ops->read_cr == NULL);
3265 if ( (rc = ops->read_cr(0, &dst.val, ctxt)) )
3266 goto done;
3267 d |= Mov; /* force writeback */
3268 break;
3269 case 6: /* lmsw */
3270 fail_if(ops->read_cr == NULL);
3271 fail_if(ops->write_cr == NULL);
3272 if ( (rc = ops->read_cr(0, &cr0, ctxt)) )
3273 goto done;
3274 if ( ea.type == OP_REG )
3275 cr0w = *ea.reg;
3276 else if ( (rc = ops->read(ea.mem.seg, ea.mem.off,
3277 &cr0w, 2, ctxt)) )
3278 goto done;
3279 cr0 &= 0xffff0000;
3280 cr0 |= (uint16_t)cr0w;
3281 if ( (rc = ops->write_cr(0, cr0, ctxt)) )
3282 goto done;
3283 break;
3284 case 7: /* invlpg */
3285 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3286 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3287 fail_if(ops->invlpg == NULL);
3288 if ( (rc = ops->invlpg(ea.mem.seg, ea.mem.off, ctxt)) )
3289 goto done;
3290 break;
3291 default:
3292 goto cannot_emulate;
3294 break;
3297 case 0x06: /* clts */
3298 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3299 fail_if((ops->read_cr == NULL) || (ops->write_cr == NULL));
3300 if ( (rc = ops->read_cr(0, &dst.val, ctxt)) ||
3301 (rc = ops->write_cr(0, dst.val&~8, ctxt)) )
3302 goto done;
3303 break;
3305 case 0x08: /* invd */
3306 case 0x09: /* wbinvd */
3307 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3308 fail_if(ops->wbinvd == NULL);
3309 if ( (rc = ops->wbinvd(ctxt)) != 0 )
3310 goto done;
3311 break;
3313 case 0x0d: /* GrpP (prefetch) */
3314 case 0x18: /* Grp16 (prefetch/nop) */
3315 case 0x19 ... 0x1f: /* nop (amd-defined) */
3316 break;
3318 case 0x20: /* mov cr,reg */
3319 case 0x21: /* mov dr,reg */
3320 case 0x22: /* mov reg,cr */
3321 case 0x23: /* mov reg,dr */
3322 generate_exception_if(ea.type != OP_REG, EXC_UD, -1);
3323 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3324 modrm_reg |= lock_prefix << 3;
3325 if ( b & 2 )
3327 /* Write to CR/DR. */
3328 src.val = *(unsigned long *)decode_register(modrm_rm, &_regs, 0);
3329 if ( !mode_64bit() )
3330 src.val = (uint32_t)src.val;
3331 rc = ((b & 1)
3332 ? (ops->write_dr
3333 ? ops->write_dr(modrm_reg, src.val, ctxt)
3334 : X86EMUL_UNHANDLEABLE)
3335 : (ops->write_cr
3336 ? ops->write_cr(modrm_reg, src.val, ctxt)
3337 : X86EMUL_UNHANDLEABLE));
3339 else
3341 /* Read from CR/DR. */
3342 dst.type = OP_REG;
3343 dst.bytes = mode_64bit() ? 8 : 4;
3344 dst.reg = decode_register(modrm_rm, &_regs, 0);
3345 rc = ((b & 1)
3346 ? (ops->read_dr
3347 ? ops->read_dr(modrm_reg, &dst.val, ctxt)
3348 : X86EMUL_UNHANDLEABLE)
3349 : (ops->read_cr
3350 ? ops->read_cr(modrm_reg, &dst.val, ctxt)
3351 : X86EMUL_UNHANDLEABLE));
3353 if ( rc != 0 )
3354 goto done;
3355 break;
3357 case 0x30: /* wrmsr */ {
3358 uint64_t val = ((uint64_t)_regs.edx << 32) | (uint32_t)_regs.eax;
3359 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3360 fail_if(ops->write_msr == NULL);
3361 if ( (rc = ops->write_msr((uint32_t)_regs.ecx, val, ctxt)) != 0 )
3362 goto done;
3363 break;
3366 case 0x31: /* rdtsc */ {
3367 unsigned long cr4;
3368 uint64_t val;
3369 fail_if(ops->read_cr == NULL);
3370 if ( (rc = ops->read_cr(4, &cr4, ctxt)) )
3371 goto done;
3372 generate_exception_if((cr4 & CR4_TSD) && !mode_ring0(), EXC_GP, 0);
3373 fail_if(ops->read_msr == NULL);
3374 if ( (rc = ops->read_msr(MSR_TSC, &val, ctxt)) != 0 )
3375 goto done;
3376 _regs.edx = (uint32_t)(val >> 32);
3377 _regs.eax = (uint32_t)(val >> 0);
3378 break;
3381 case 0x32: /* rdmsr */ {
3382 uint64_t val;
3383 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3384 fail_if(ops->read_msr == NULL);
3385 if ( (rc = ops->read_msr((uint32_t)_regs.ecx, &val, ctxt)) != 0 )
3386 goto done;
3387 _regs.edx = (uint32_t)(val >> 32);
3388 _regs.eax = (uint32_t)(val >> 0);
3389 break;
3392 case 0x6f: /* movq mm/m64,mm */ {
3393 uint8_t stub[] = { 0x0f, 0x6f, modrm, 0xc3 };
3394 struct fpu_insn_ctxt fic = { .insn_bytes = sizeof(stub)-1 };
3395 uint64_t val;
3396 if ( ea.type == OP_MEM )
3398 unsigned long lval, hval;
3399 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0, &lval, 4, ctxt)) ||
3400 (rc = ops->read(ea.mem.seg, ea.mem.off+4, &hval, 4, ctxt)) )
3401 goto done;
3402 val = ((uint64_t)hval << 32) | (uint32_t)lval;
3403 stub[2] = modrm & 0x38; /* movq (%eax),%mmN */
3405 get_fpu(X86EMUL_FPU_mmx, &fic);
3406 asm volatile ( "call *%0" : : "r" (stub), "a" (&val) : "memory" );
3407 put_fpu(&fic);
3408 break;
3411 case 0x7f: /* movq mm,mm/m64 */ {
3412 uint8_t stub[] = { 0x0f, 0x7f, modrm, 0xc3 };
3413 struct fpu_insn_ctxt fic = { .insn_bytes = sizeof(stub)-1 };
3414 uint64_t val;
3415 if ( ea.type == OP_MEM )
3416 stub[2] = modrm & 0x38; /* movq %mmN,(%eax) */
3417 get_fpu(X86EMUL_FPU_mmx, &fic);
3418 asm volatile ( "call *%0" : : "r" (stub), "a" (&val) : "memory" );
3419 put_fpu(&fic);
3420 if ( ea.type == OP_MEM )
3422 unsigned long lval = (uint32_t)val, hval = (uint32_t)(val >> 32);
3423 if ( (rc = ops->write(ea.mem.seg, ea.mem.off+0, lval, 4, ctxt)) ||
3424 (rc = ops->write(ea.mem.seg, ea.mem.off+4, hval, 4, ctxt)) )
3425 goto done;
3427 break;
3430 case 0x80 ... 0x8f: /* jcc (near) */ {
3431 int rel = (((op_bytes == 2) && !mode_64bit())
3432 ? (int32_t)insn_fetch_type(int16_t)
3433 : insn_fetch_type(int32_t));
3434 if ( test_cc(b, _regs.eflags) )
3435 jmp_rel(rel);
3436 break;
3439 case 0xa0: /* push %%fs */
3440 src.val = x86_seg_fs;
3441 goto push_seg;
3443 case 0xa1: /* pop %%fs */
3444 src.val = x86_seg_fs;
3445 goto pop_seg;
3447 case 0xa2: /* cpuid */ {
3448 unsigned int eax = _regs.eax, ebx = _regs.ebx;
3449 unsigned int ecx = _regs.ecx, edx = _regs.edx;
3450 fail_if(ops->cpuid == NULL);
3451 if ( (rc = ops->cpuid(&eax, &ebx, &ecx, &edx, ctxt)) != 0 )
3452 goto done;
3453 _regs.eax = eax; _regs.ebx = ebx;
3454 _regs.ecx = ecx; _regs.edx = edx;
3455 break;
3458 case 0xa8: /* push %%gs */
3459 src.val = x86_seg_gs;
3460 goto push_seg;
3462 case 0xa9: /* pop %%gs */
3463 src.val = x86_seg_gs;
3464 goto pop_seg;
3466 case 0xc7: /* Grp9 (cmpxchg8b/cmpxchg16b) */ {
3467 unsigned long old[2], exp[2], new[2];
3468 unsigned int i;
3470 generate_exception_if((modrm_reg & 7) != 1, EXC_UD, -1);
3471 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3472 op_bytes *= 2;
3474 /* Get actual old value. */
3475 for ( i = 0; i < (op_bytes/sizeof(long)); i++ )
3476 if ( (rc = ops->read(ea.mem.seg, ea.mem.off + i*sizeof(long),
3477 &old[i], sizeof(long), ctxt)) != 0 )
3478 goto done;
3480 /* Get expected and proposed values. */
3481 if ( op_bytes == 8 )
3483 ((uint32_t *)exp)[0] = _regs.eax; ((uint32_t *)exp)[1] = _regs.edx;
3484 ((uint32_t *)new)[0] = _regs.ebx; ((uint32_t *)new)[1] = _regs.ecx;
3486 else
3488 exp[0] = _regs.eax; exp[1] = _regs.edx;
3489 new[0] = _regs.ebx; new[1] = _regs.ecx;
3492 if ( memcmp(old, exp, op_bytes) )
3494 /* Expected != actual: store actual to rDX:rAX and clear ZF. */
3495 _regs.eax = (op_bytes == 8) ? ((uint32_t *)old)[0] : old[0];
3496 _regs.edx = (op_bytes == 8) ? ((uint32_t *)old)[1] : old[1];
3497 _regs.eflags &= ~EFLG_ZF;
3499 else
3501 /* Expected == actual: attempt atomic cmpxchg and set ZF. */
3502 if ( (rc = ops->cmpxchg(ea.mem.seg, ea.mem.off, old,
3503 new, op_bytes, ctxt)) != 0 )
3504 goto done;
3505 _regs.eflags |= EFLG_ZF;
3507 break;
3510 case 0xc8 ... 0xcf: /* bswap */
3511 dst.type = OP_REG;
3512 dst.reg = decode_register(
3513 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
3514 switch ( dst.bytes = op_bytes )
3516 default: /* case 2: */
3517 /* Undefined behaviour. Writes zero on all tested CPUs. */
3518 dst.val = 0;
3519 break;
3520 case 4:
3521 #ifdef __x86_64__
3522 asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
3523 break;
3524 case 8:
3525 #endif
3526 asm ( "bswap %0" : "=r" (dst.val) : "0" (*dst.reg) );
3527 break;
3529 break;
3531 goto writeback;
3533 cannot_emulate:
3534 return X86EMUL_UNHANDLEABLE;