ia64/xen-unstable

view xen/include/asm-ia64/vcpu.h @ 10692:306d7857928c

[IA64] Save & restore.

xc_ia64_linux_save.c and xc_ia64_linux_restore.c added.
vcpu context has more registers and states (eg: tr registers).
Per cpu irqs are deallocated when cpu is switched off.
#if/#endif added in reboot.c for ia64.

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Jul 11 12:51:18 2006 -0600 (2006-07-11)
parents 8ad37880564d
children b2abc70be89e
line source
1 #ifndef _XEN_IA64_VCPU_H
2 #define _XEN_IA64_VCPU_H
4 // TODO: Many (or perhaps most) of these should eventually be
5 // static inline functions
7 #include <asm/delay.h>
8 #include <asm/fpu.h>
9 #include <asm/tlb.h>
10 #include <asm/ia64_int.h>
11 #include <asm/time.h>
12 #include <public/arch-ia64.h>
13 typedef unsigned long UINT64;
14 typedef unsigned int UINT;
15 typedef int BOOLEAN;
16 struct vcpu;
17 typedef struct vcpu VCPU;
18 typedef cpu_user_regs_t REGS;
20 /* Note: PSCB stands for Privilegied State Communication Block. */
21 #define VCPU(_v,_x) (_v->arch.privregs->_x)
22 #define PSCB(_v,_x) VCPU(_v,_x)
23 #define PSCBX(_v,_x) (_v->arch._x)
25 #define SPURIOUS_VECTOR 0xf
27 /* general registers */
28 extern UINT64 vcpu_get_gr(VCPU *vcpu, unsigned long reg);
29 extern IA64FAULT vcpu_get_gr_nat(VCPU *vcpu, unsigned long reg, UINT64 *val);
30 extern IA64FAULT vcpu_set_gr(VCPU *vcpu, unsigned long reg, UINT64 value, int nat);
31 extern IA64FAULT vcpu_get_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg *val);
33 extern IA64FAULT vcpu_set_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg *val);
35 /* application registers */
36 extern void vcpu_load_kernel_regs(VCPU *vcpu);
37 extern IA64FAULT vcpu_set_ar(VCPU *vcpu, UINT64 reg, UINT64 val);
38 extern IA64FAULT vcpu_get_ar(VCPU *vcpu, UINT64 reg, UINT64 *val);
39 /* psr */
40 extern BOOLEAN vcpu_get_psr_ic(VCPU *vcpu);
41 extern UINT64 vcpu_get_ipsr_int_state(VCPU *vcpu,UINT64 prevpsr);
42 extern IA64FAULT vcpu_get_psr(VCPU *vcpu, UINT64 *pval);
43 extern IA64FAULT vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm);
44 extern IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm);
45 extern IA64FAULT vcpu_set_psr_l(VCPU *vcpu, UINT64 val);
46 extern IA64FAULT vcpu_set_psr_i(VCPU *vcpu);
47 extern IA64FAULT vcpu_reset_psr_dt(VCPU *vcpu);
48 extern IA64FAULT vcpu_set_psr_dt(VCPU *vcpu);
49 /* control registers */
50 extern IA64FAULT vcpu_set_dcr(VCPU *vcpu, UINT64 val);
51 extern IA64FAULT vcpu_set_itm(VCPU *vcpu, UINT64 val);
52 extern IA64FAULT vcpu_set_iva(VCPU *vcpu, UINT64 val);
53 extern IA64FAULT vcpu_set_pta(VCPU *vcpu, UINT64 val);
54 extern IA64FAULT vcpu_set_ipsr(VCPU *vcpu, UINT64 val);
55 extern IA64FAULT vcpu_set_isr(VCPU *vcpu, UINT64 val);
56 extern IA64FAULT vcpu_set_iip(VCPU *vcpu, UINT64 val);
57 extern IA64FAULT vcpu_set_ifa(VCPU *vcpu, UINT64 val);
58 extern IA64FAULT vcpu_set_itir(VCPU *vcpu, UINT64 val);
59 extern IA64FAULT vcpu_set_iipa(VCPU *vcpu, UINT64 val);
60 extern IA64FAULT vcpu_set_ifs(VCPU *vcpu, UINT64 val);
61 extern IA64FAULT vcpu_set_iim(VCPU *vcpu, UINT64 val);
62 extern IA64FAULT vcpu_set_iha(VCPU *vcpu, UINT64 val);
63 extern IA64FAULT vcpu_set_lid(VCPU *vcpu, UINT64 val);
64 extern IA64FAULT vcpu_set_tpr(VCPU *vcpu, UINT64 val);
65 extern IA64FAULT vcpu_set_eoi(VCPU *vcpu, UINT64 val);
66 extern IA64FAULT vcpu_set_lrr0(VCPU *vcpu, UINT64 val);
67 extern IA64FAULT vcpu_set_lrr1(VCPU *vcpu, UINT64 val);
68 extern IA64FAULT vcpu_get_dcr(VCPU *vcpu, UINT64 *pval);
69 extern IA64FAULT vcpu_get_itm(VCPU *vcpu, UINT64 *pval);
70 extern IA64FAULT vcpu_get_iva(VCPU *vcpu, UINT64 *pval);
71 extern IA64FAULT vcpu_get_pta(VCPU *vcpu, UINT64 *pval);
72 extern IA64FAULT vcpu_get_ipsr(VCPU *vcpu, UINT64 *pval);
73 extern IA64FAULT vcpu_get_isr(VCPU *vcpu, UINT64 *pval);
74 extern IA64FAULT vcpu_get_iip(VCPU *vcpu, UINT64 *pval);
75 extern IA64FAULT vcpu_increment_iip(VCPU *vcpu);
76 extern IA64FAULT vcpu_get_ifa(VCPU *vcpu, UINT64 *pval);
77 extern IA64FAULT vcpu_get_itir(VCPU *vcpu, UINT64 *pval);
78 extern unsigned long vcpu_get_itir_on_fault(VCPU *vcpu, UINT64 ifa);
79 extern IA64FAULT vcpu_get_iipa(VCPU *vcpu, UINT64 *pval);
80 extern IA64FAULT vcpu_get_ifs(VCPU *vcpu, UINT64 *pval);
81 extern IA64FAULT vcpu_get_iim(VCPU *vcpu, UINT64 *pval);
82 extern IA64FAULT vcpu_get_iha(VCPU *vcpu, UINT64 *pval);
83 extern IA64FAULT vcpu_get_lid(VCPU *vcpu, UINT64 *pval);
84 extern IA64FAULT vcpu_get_tpr(VCPU *vcpu, UINT64 *pval);
85 extern IA64FAULT vcpu_get_irr0(VCPU *vcpu, UINT64 *pval);
86 extern IA64FAULT vcpu_get_irr1(VCPU *vcpu, UINT64 *pval);
87 extern IA64FAULT vcpu_get_irr2(VCPU *vcpu, UINT64 *pval);
88 extern IA64FAULT vcpu_get_irr3(VCPU *vcpu, UINT64 *pval);
89 extern IA64FAULT vcpu_get_lrr0(VCPU *vcpu, UINT64 *pval);
90 extern IA64FAULT vcpu_get_lrr1(VCPU *vcpu, UINT64 *pval);
91 /* interrupt registers */
92 extern void vcpu_pend_unspecified_interrupt(VCPU *vcpu);
93 extern UINT64 vcpu_check_pending_interrupts(VCPU *vcpu);
94 extern IA64FAULT vcpu_get_itv(VCPU *vcpu,UINT64 *pval);
95 extern IA64FAULT vcpu_get_pmv(VCPU *vcpu,UINT64 *pval);
96 extern IA64FAULT vcpu_get_cmcv(VCPU *vcpu,UINT64 *pval);
97 extern IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT64 *pval);
98 extern IA64FAULT vcpu_set_itv(VCPU *vcpu, UINT64 val);
99 extern IA64FAULT vcpu_set_pmv(VCPU *vcpu, UINT64 val);
100 extern IA64FAULT vcpu_set_cmcv(VCPU *vcpu, UINT64 val);
101 /* interval timer registers */
102 extern IA64FAULT vcpu_set_itc(VCPU *vcpu,UINT64 val);
103 extern UINT64 vcpu_timer_pending_early(VCPU *vcpu);
104 /* debug breakpoint registers */
105 extern IA64FAULT vcpu_set_ibr(VCPU *vcpu,UINT64 reg,UINT64 val);
106 extern IA64FAULT vcpu_set_dbr(VCPU *vcpu,UINT64 reg,UINT64 val);
107 extern IA64FAULT vcpu_get_ibr(VCPU *vcpu,UINT64 reg,UINT64 *pval);
108 extern IA64FAULT vcpu_get_dbr(VCPU *vcpu,UINT64 reg,UINT64 *pval);
109 /* performance monitor registers */
110 extern IA64FAULT vcpu_set_pmc(VCPU *vcpu,UINT64 reg,UINT64 val);
111 extern IA64FAULT vcpu_set_pmd(VCPU *vcpu,UINT64 reg,UINT64 val);
112 extern IA64FAULT vcpu_get_pmc(VCPU *vcpu,UINT64 reg,UINT64 *pval);
113 extern IA64FAULT vcpu_get_pmd(VCPU *vcpu,UINT64 reg,UINT64 *pval);
114 /* banked general registers */
115 extern IA64FAULT vcpu_bsw0(VCPU *vcpu);
116 extern IA64FAULT vcpu_bsw1(VCPU *vcpu);
117 /* region registers */
118 extern IA64FAULT vcpu_set_rr(VCPU *vcpu,UINT64 reg,UINT64 val);
119 extern IA64FAULT vcpu_get_rr(VCPU *vcpu,UINT64 reg,UINT64 *pval);
120 extern IA64FAULT vcpu_get_rr_ve(VCPU *vcpu,UINT64 vadr);
121 /* protection key registers */
122 extern IA64FAULT vcpu_get_pkr(VCPU *vcpu, UINT64 reg, UINT64 *pval);
123 extern IA64FAULT vcpu_set_pkr(VCPU *vcpu, UINT64 reg, UINT64 val);
124 extern IA64FAULT vcpu_tak(VCPU *vcpu, UINT64 vadr, UINT64 *key);
125 /* TLB */
126 static inline void vcpu_purge_tr_entry(TR_ENTRY *trp)
127 {
128 trp->pte.val = 0;
129 }
130 extern IA64FAULT vcpu_itr_d(VCPU *vcpu, UINT64 slot, UINT64 padr,
131 UINT64 itir, UINT64 ifa);
132 extern IA64FAULT vcpu_itr_i(VCPU *vcpu, UINT64 slot, UINT64 padr,
133 UINT64 itir, UINT64 ifa);
134 extern IA64FAULT vcpu_itc_d(VCPU *vcpu, UINT64 padr, UINT64 itir, UINT64 ifa);
135 extern IA64FAULT vcpu_itc_i(VCPU *vcpu, UINT64 padr, UINT64 itir, UINT64 ifa);
136 extern IA64FAULT vcpu_ptc_l(VCPU *vcpu, UINT64 vadr, UINT64 log_range);
137 extern IA64FAULT vcpu_ptc_e(VCPU *vcpu, UINT64 vadr);
138 extern IA64FAULT vcpu_ptc_g(VCPU *vcpu, UINT64 vadr, UINT64 addr_range);
139 extern IA64FAULT vcpu_ptc_ga(VCPU *vcpu, UINT64 vadr, UINT64 addr_range);
140 extern IA64FAULT vcpu_ptr_d(VCPU *vcpu,UINT64 vadr, UINT64 log_range);
141 extern IA64FAULT vcpu_ptr_i(VCPU *vcpu,UINT64 vadr, UINT64 log_range);
142 union U_IA64_BUNDLE;
143 extern int vcpu_get_domain_bundle(VCPU *vcpu, REGS *regs, UINT64 gip, union U_IA64_BUNDLE *bundle);
144 extern IA64FAULT vcpu_translate(VCPU *vcpu, UINT64 address, BOOLEAN is_data,
145 UINT64 *pteval, UINT64 *itir, UINT64 *iha);
146 extern IA64FAULT vcpu_tpa(VCPU *vcpu, UINT64 vadr, UINT64 *padr);
147 extern IA64FAULT vcpu_force_inst_miss(VCPU *vcpu, UINT64 ifa);
148 extern IA64FAULT vcpu_force_data_miss(VCPU *vcpu, UINT64 ifa);
149 extern IA64FAULT vcpu_fc(VCPU *vcpu, UINT64 vadr);
150 /* misc */
151 extern IA64FAULT vcpu_rfi(VCPU *vcpu);
152 extern IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 vadr, UINT64 *pval);
153 extern IA64FAULT vcpu_cover(VCPU *vcpu);
154 extern IA64FAULT vcpu_ttag(VCPU *vcpu, UINT64 vadr, UINT64 *padr);
155 extern IA64FAULT vcpu_get_cpuid(VCPU *vcpu, UINT64 reg, UINT64 *pval);
157 extern void vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector);
158 extern void vcpu_pend_timer(VCPU *vcpu);
159 extern void vcpu_poke_timer(VCPU *vcpu);
160 extern void vcpu_set_next_timer(VCPU *vcpu);
161 extern BOOLEAN vcpu_timer_expired(VCPU *vcpu);
162 extern UINT64 vcpu_deliverable_interrupts(VCPU *vcpu);
163 extern void vcpu_itc_no_srlz(VCPU *vcpu, UINT64, UINT64, UINT64, UINT64, UINT64);
164 extern UINT64 vcpu_get_tmp(VCPU *, UINT64);
165 extern void vcpu_set_tmp(VCPU *, UINT64, UINT64);
167 extern IA64FAULT vcpu_set_dtr(VCPU *vcpu, u64 slot,
168 u64 pte, u64 itir, u64 ifa, u64 rid);
169 extern IA64FAULT vcpu_set_itr(VCPU *vcpu, u64 slot,
170 u64 pte, u64 itir, u64 ifa, u64 rid);
172 /* Initialize vcpu regs. */
173 extern void vcpu_init_regs (struct vcpu *v);
175 static inline UINT64
176 itir_ps(UINT64 itir)
177 {
178 return ((itir >> 2) & 0x3f);
179 }
181 static inline UINT64
182 itir_mask(UINT64 itir)
183 {
184 return (~((1UL << itir_ps(itir)) - 1));
185 }
187 static inline u64
188 vcpu_get_next_timer_ns(VCPU *vcpu)
189 {
190 return cycle_to_ns(PSCBX(vcpu, domain_itm) - ia64_get_itc()) + NOW();
191 }
193 #define verbose(a...) do {if (vcpu_verbose) printf(a);} while(0)
195 //#define vcpu_quick_region_check(_tr_regions,_ifa) 1
196 #define vcpu_quick_region_check(_tr_regions,_ifa) \
197 (_tr_regions & (1 << ((unsigned long)_ifa >> 61)))
198 #define vcpu_quick_region_set(_tr_regions,_ifa) \
199 do {_tr_regions |= (1 << ((unsigned long)_ifa >> 61)); } while (0)
202 #endif