ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-i386/mach-xen/asm/processor.h @ 13341:3040ba0f2d3d

When booting via xm, only run the bootloader if it's in non-interactive mode:
otherwise we lose the user's named kernel and try to bootload the temporary
file pygrub returned.

Signed-off-by: John Levon <john.levon@sun.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Tue Jan 09 13:24:45 2007 +0000 (2007-01-09)
parents 42a8e3101c6c
children 4fad820a2233
line source
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <asm/msr.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
22 #include <asm/percpu.h>
23 #include <xen/interface/physdev.h>
25 /* flag for disabling the tsc */
26 extern int tsc_disable;
28 struct desc_struct {
29 unsigned long a,b;
30 };
32 #define desc_empty(desc) \
33 (!((desc)->a | (desc)->b))
35 #define desc_equal(desc1, desc2) \
36 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 /*
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
40 */
41 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 /*
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
47 */
49 struct cpuinfo_x86 {
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
52 __u8 x86_model;
53 __u8 x86_mask;
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
56 char hard_math;
57 char rfu;
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
63 call */
64 int x86_cache_alignment; /* In bytes */
65 char fdiv_bug;
66 char f00f_bug;
67 char coma_bug;
68 char pad0;
69 int x86_power;
70 unsigned long loops_per_jiffy;
71 unsigned char x86_max_cores; /* cpuid returned max cores value */
72 unsigned char booted_cores; /* number of cores as seen by OS */
73 unsigned char apicid;
74 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
76 #define X86_VENDOR_INTEL 0
77 #define X86_VENDOR_CYRIX 1
78 #define X86_VENDOR_AMD 2
79 #define X86_VENDOR_UMC 3
80 #define X86_VENDOR_NEXGEN 4
81 #define X86_VENDOR_CENTAUR 5
82 #define X86_VENDOR_RISE 6
83 #define X86_VENDOR_TRANSMETA 7
84 #define X86_VENDOR_NSC 8
85 #define X86_VENDOR_NUM 9
86 #define X86_VENDOR_UNKNOWN 0xff
88 /*
89 * capabilities of CPUs
90 */
92 extern struct cpuinfo_x86 boot_cpu_data;
93 extern struct cpuinfo_x86 new_cpu_data;
94 #ifndef CONFIG_X86_NO_TSS
95 extern struct tss_struct doublefault_tss;
96 DECLARE_PER_CPU(struct tss_struct, init_tss);
97 #endif
99 #ifdef CONFIG_SMP
100 extern struct cpuinfo_x86 cpu_data[];
101 #define current_cpu_data cpu_data[smp_processor_id()]
102 #else
103 #define cpu_data (&boot_cpu_data)
104 #define current_cpu_data boot_cpu_data
105 #endif
107 extern int phys_proc_id[NR_CPUS];
108 extern int cpu_core_id[NR_CPUS];
109 extern char ignore_fpu_irq;
111 extern void identify_cpu(struct cpuinfo_x86 *);
112 extern void print_cpu_info(struct cpuinfo_x86 *);
113 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
115 #ifdef CONFIG_X86_HT
116 extern void detect_ht(struct cpuinfo_x86 *c);
117 #else
118 static inline void detect_ht(struct cpuinfo_x86 *c) {}
119 #endif
121 /*
122 * EFLAGS bits
123 */
124 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
125 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
126 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
127 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
128 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
129 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
130 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
131 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
132 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
133 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
134 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
135 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
136 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
137 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
138 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
139 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
140 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
142 /*
143 * Generic CPUID function
144 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
145 * resulting in stale register contents being returned.
146 */
147 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
148 {
149 __asm__(XEN_CPUID
150 : "=a" (*eax),
151 "=b" (*ebx),
152 "=c" (*ecx),
153 "=d" (*edx)
154 : "0" (op), "c"(0));
155 }
157 /* Some CPUID calls want 'count' to be placed in ecx */
158 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
159 int *edx)
160 {
161 __asm__(XEN_CPUID
162 : "=a" (*eax),
163 "=b" (*ebx),
164 "=c" (*ecx),
165 "=d" (*edx)
166 : "0" (op), "c" (count));
167 }
169 /*
170 * CPUID functions returning a single datum
171 */
172 static inline unsigned int cpuid_eax(unsigned int op)
173 {
174 unsigned int eax;
176 __asm__(XEN_CPUID
177 : "=a" (eax)
178 : "0" (op)
179 : "bx", "cx", "dx");
180 return eax;
181 }
182 static inline unsigned int cpuid_ebx(unsigned int op)
183 {
184 unsigned int eax, ebx;
186 __asm__(XEN_CPUID
187 : "=a" (eax), "=b" (ebx)
188 : "0" (op)
189 : "cx", "dx" );
190 return ebx;
191 }
192 static inline unsigned int cpuid_ecx(unsigned int op)
193 {
194 unsigned int eax, ecx;
196 __asm__(XEN_CPUID
197 : "=a" (eax), "=c" (ecx)
198 : "0" (op)
199 : "bx", "dx" );
200 return ecx;
201 }
202 static inline unsigned int cpuid_edx(unsigned int op)
203 {
204 unsigned int eax, edx;
206 __asm__(XEN_CPUID
207 : "=a" (eax), "=d" (edx)
208 : "0" (op)
209 : "bx", "cx");
210 return edx;
211 }
213 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
215 /*
216 * Intel CPU features in CR4
217 */
218 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
219 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
220 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
221 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
222 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
223 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
224 #define X86_CR4_MCE 0x0040 /* Machine check enable */
225 #define X86_CR4_PGE 0x0080 /* enable global pages */
226 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
227 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
228 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
230 /*
231 * Save the cr4 feature set we're using (ie
232 * Pentium 4MB enable and PPro Global page
233 * enable), so that any CPU's that boot up
234 * after us can get the correct flags.
235 */
236 extern unsigned long mmu_cr4_features;
238 static inline void set_in_cr4 (unsigned long mask)
239 {
240 unsigned cr4;
241 mmu_cr4_features |= mask;
242 cr4 = read_cr4();
243 cr4 |= mask;
244 write_cr4(cr4);
245 }
247 static inline void clear_in_cr4 (unsigned long mask)
248 {
249 unsigned cr4;
250 mmu_cr4_features &= ~mask;
251 cr4 = read_cr4();
252 cr4 &= ~mask;
253 write_cr4(cr4);
254 }
256 /*
257 * NSC/Cyrix CPU configuration register indexes
258 */
260 #define CX86_PCR0 0x20
261 #define CX86_GCR 0xb8
262 #define CX86_CCR0 0xc0
263 #define CX86_CCR1 0xc1
264 #define CX86_CCR2 0xc2
265 #define CX86_CCR3 0xc3
266 #define CX86_CCR4 0xe8
267 #define CX86_CCR5 0xe9
268 #define CX86_CCR6 0xea
269 #define CX86_CCR7 0xeb
270 #define CX86_PCR1 0xf0
271 #define CX86_DIR0 0xfe
272 #define CX86_DIR1 0xff
273 #define CX86_ARR_BASE 0xc4
274 #define CX86_RCR_BASE 0xdc
276 /*
277 * NSC/Cyrix CPU indexed register access macros
278 */
280 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
282 #define setCx86(reg, data) do { \
283 outb((reg), 0x22); \
284 outb((data), 0x23); \
285 } while (0)
287 /* Stop speculative execution */
288 static inline void sync_core(void)
289 {
290 int tmp;
291 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
292 }
294 static inline void __monitor(const void *eax, unsigned long ecx,
295 unsigned long edx)
296 {
297 /* "monitor %eax,%ecx,%edx;" */
298 asm volatile(
299 ".byte 0x0f,0x01,0xc8;"
300 : :"a" (eax), "c" (ecx), "d"(edx));
301 }
303 static inline void __mwait(unsigned long eax, unsigned long ecx)
304 {
305 /* "mwait %eax,%ecx;" */
306 asm volatile(
307 ".byte 0x0f,0x01,0xc9;"
308 : :"a" (eax), "c" (ecx));
309 }
311 /* from system description table in BIOS. Mostly for MCA use, but
312 others may find it useful. */
313 extern unsigned int machine_id;
314 extern unsigned int machine_submodel_id;
315 extern unsigned int BIOS_revision;
316 extern unsigned int mca_pentium_flag;
318 /* Boot loader type from the setup header */
319 extern int bootloader_type;
321 /*
322 * User space process size: 3GB (default).
323 */
324 #define TASK_SIZE (PAGE_OFFSET)
326 /* This decides where the kernel will search for a free chunk of vm
327 * space during mmap's.
328 */
329 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
331 #define HAVE_ARCH_PICK_MMAP_LAYOUT
333 /*
334 * Size of io_bitmap.
335 */
336 #define IO_BITMAP_BITS 65536
337 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
338 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
339 #ifndef CONFIG_X86_NO_TSS
340 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
341 #endif
342 #define INVALID_IO_BITMAP_OFFSET 0x8000
343 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
345 struct i387_fsave_struct {
346 long cwd;
347 long swd;
348 long twd;
349 long fip;
350 long fcs;
351 long foo;
352 long fos;
353 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
354 long status; /* software status information */
355 };
357 struct i387_fxsave_struct {
358 unsigned short cwd;
359 unsigned short swd;
360 unsigned short twd;
361 unsigned short fop;
362 long fip;
363 long fcs;
364 long foo;
365 long fos;
366 long mxcsr;
367 long mxcsr_mask;
368 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
369 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
370 long padding[56];
371 } __attribute__ ((aligned (16)));
373 struct i387_soft_struct {
374 long cwd;
375 long swd;
376 long twd;
377 long fip;
378 long fcs;
379 long foo;
380 long fos;
381 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
382 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
383 struct info *info;
384 unsigned long entry_eip;
385 };
387 union i387_union {
388 struct i387_fsave_struct fsave;
389 struct i387_fxsave_struct fxsave;
390 struct i387_soft_struct soft;
391 };
393 typedef struct {
394 unsigned long seg;
395 } mm_segment_t;
397 struct thread_struct;
399 #ifndef CONFIG_X86_NO_TSS
400 struct tss_struct {
401 unsigned short back_link,__blh;
402 unsigned long esp0;
403 unsigned short ss0,__ss0h;
404 unsigned long esp1;
405 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
406 unsigned long esp2;
407 unsigned short ss2,__ss2h;
408 unsigned long __cr3;
409 unsigned long eip;
410 unsigned long eflags;
411 unsigned long eax,ecx,edx,ebx;
412 unsigned long esp;
413 unsigned long ebp;
414 unsigned long esi;
415 unsigned long edi;
416 unsigned short es, __esh;
417 unsigned short cs, __csh;
418 unsigned short ss, __ssh;
419 unsigned short ds, __dsh;
420 unsigned short fs, __fsh;
421 unsigned short gs, __gsh;
422 unsigned short ldt, __ldth;
423 unsigned short trace, io_bitmap_base;
424 /*
425 * The extra 1 is there because the CPU will access an
426 * additional byte beyond the end of the IO permission
427 * bitmap. The extra byte must be all 1 bits, and must
428 * be within the limit.
429 */
430 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
431 /*
432 * Cache the current maximum and the last task that used the bitmap:
433 */
434 unsigned long io_bitmap_max;
435 struct thread_struct *io_bitmap_owner;
436 /*
437 * pads the TSS to be cacheline-aligned (size is 0x100)
438 */
439 unsigned long __cacheline_filler[35];
440 /*
441 * .. and then another 0x100 bytes for emergency kernel stack
442 */
443 unsigned long stack[64];
444 } __attribute__((packed));
445 #endif
447 #define ARCH_MIN_TASKALIGN 16
449 struct thread_struct {
450 /* cached TLS descriptors. */
451 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
452 unsigned long esp0;
453 unsigned long sysenter_cs;
454 unsigned long eip;
455 unsigned long esp;
456 unsigned long fs;
457 unsigned long gs;
458 /* Hardware debugging registers */
459 unsigned long debugreg[8]; /* %%db0-7 debug registers */
460 /* fault info */
461 unsigned long cr2, trap_no, error_code;
462 /* floating point info */
463 union i387_union i387;
464 /* virtual 86 mode info */
465 struct vm86_struct __user * vm86_info;
466 unsigned long screen_bitmap;
467 unsigned long v86flags, v86mask, saved_esp0;
468 unsigned int saved_fs, saved_gs;
469 /* IO permissions */
470 unsigned long *io_bitmap_ptr;
471 unsigned long iopl;
472 /* max allowed port in the bitmap, in bytes: */
473 unsigned long io_bitmap_max;
474 };
476 #define INIT_THREAD { \
477 .vm86_info = NULL, \
478 .sysenter_cs = __KERNEL_CS, \
479 .io_bitmap_ptr = NULL, \
480 }
482 #ifndef CONFIG_X86_NO_TSS
483 /*
484 * Note that the .io_bitmap member must be extra-big. This is because
485 * the CPU will access an additional byte beyond the end of the IO
486 * permission bitmap. The extra byte must be all 1 bits, and must
487 * be within the limit.
488 */
489 #define INIT_TSS { \
490 .esp0 = sizeof(init_stack) + (long)&init_stack, \
491 .ss0 = __KERNEL_DS, \
492 .ss1 = __KERNEL_CS, \
493 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
494 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
495 }
497 static inline void __load_esp0(struct tss_struct *tss, struct thread_struct *thread)
498 {
499 tss->esp0 = thread->esp0;
500 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
501 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
502 tss->ss1 = thread->sysenter_cs;
503 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
504 }
505 }
506 #define load_esp0(tss, thread) \
507 __load_esp0(tss, thread)
508 #else
509 #define load_esp0(tss, thread) \
510 HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->esp0)
511 #endif
513 #define start_thread(regs, new_eip, new_esp) do { \
514 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
515 set_fs(USER_DS); \
516 regs->xds = __USER_DS; \
517 regs->xes = __USER_DS; \
518 regs->xss = __USER_DS; \
519 regs->xcs = __USER_CS; \
520 regs->eip = new_eip; \
521 regs->esp = new_esp; \
522 } while (0)
524 /*
525 * These special macros can be used to get or set a debugging register
526 */
527 #define get_debugreg(var, register) \
528 (var) = HYPERVISOR_get_debugreg((register))
529 #define set_debugreg(value, register) \
530 HYPERVISOR_set_debugreg((register), (value))
532 /*
533 * Set IOPL bits in EFLAGS from given mask
534 */
535 static inline void set_iopl_mask(unsigned mask)
536 {
537 struct physdev_set_iopl set_iopl;
539 /* Force the change at ring 0. */
540 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
541 HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
542 }
544 /* Forward declaration, a strange C thing */
545 struct task_struct;
546 struct mm_struct;
548 /* Free all resources held by a thread. */
549 extern void release_thread(struct task_struct *);
551 /* Prepare to copy thread state - unlazy all lazy status */
552 extern void prepare_to_copy(struct task_struct *tsk);
554 /*
555 * create a kernel thread without removing it from tasklists
556 */
557 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
559 extern unsigned long thread_saved_pc(struct task_struct *tsk);
560 void show_trace(struct task_struct *task, unsigned long *stack);
562 unsigned long get_wchan(struct task_struct *p);
564 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
565 #define KSTK_TOP(info) \
566 ({ \
567 unsigned long *__ptr = (unsigned long *)(info); \
568 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
569 })
571 /*
572 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
573 * This is necessary to guarantee that the entire "struct pt_regs"
574 * is accessable even if the CPU haven't stored the SS/ESP registers
575 * on the stack (interrupt gate does not save these registers
576 * when switching to the same priv ring).
577 * Therefore beware: accessing the xss/esp fields of the
578 * "struct pt_regs" is possible, but they may contain the
579 * completely wrong values.
580 */
581 #define task_pt_regs(task) \
582 ({ \
583 struct pt_regs *__regs__; \
584 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
585 __regs__ - 1; \
586 })
588 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
589 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
592 struct microcode_header {
593 unsigned int hdrver;
594 unsigned int rev;
595 unsigned int date;
596 unsigned int sig;
597 unsigned int cksum;
598 unsigned int ldrver;
599 unsigned int pf;
600 unsigned int datasize;
601 unsigned int totalsize;
602 unsigned int reserved[3];
603 };
605 struct microcode {
606 struct microcode_header hdr;
607 unsigned int bits[0];
608 };
610 typedef struct microcode microcode_t;
611 typedef struct microcode_header microcode_header_t;
613 /* microcode format is extended from prescott processors */
614 struct extended_signature {
615 unsigned int sig;
616 unsigned int pf;
617 unsigned int cksum;
618 };
620 struct extended_sigtable {
621 unsigned int count;
622 unsigned int cksum;
623 unsigned int reserved[3];
624 struct extended_signature sigs[0];
625 };
626 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
627 #define MICROCODE_IOCFREE _IO('6',0)
629 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
630 static inline void rep_nop(void)
631 {
632 __asm__ __volatile__("rep;nop": : :"memory");
633 }
635 #define cpu_relax() rep_nop()
637 /* generic versions from gas */
638 #define GENERIC_NOP1 ".byte 0x90\n"
639 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
640 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
641 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
642 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
643 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
644 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
645 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
647 /* Opteron nops */
648 #define K8_NOP1 GENERIC_NOP1
649 #define K8_NOP2 ".byte 0x66,0x90\n"
650 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
651 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
652 #define K8_NOP5 K8_NOP3 K8_NOP2
653 #define K8_NOP6 K8_NOP3 K8_NOP3
654 #define K8_NOP7 K8_NOP4 K8_NOP3
655 #define K8_NOP8 K8_NOP4 K8_NOP4
657 /* K7 nops */
658 /* uses eax dependencies (arbitary choice) */
659 #define K7_NOP1 GENERIC_NOP1
660 #define K7_NOP2 ".byte 0x8b,0xc0\n"
661 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
662 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
663 #define K7_NOP5 K7_NOP4 ASM_NOP1
664 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
665 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
666 #define K7_NOP8 K7_NOP7 ASM_NOP1
668 #ifdef CONFIG_MK8
669 #define ASM_NOP1 K8_NOP1
670 #define ASM_NOP2 K8_NOP2
671 #define ASM_NOP3 K8_NOP3
672 #define ASM_NOP4 K8_NOP4
673 #define ASM_NOP5 K8_NOP5
674 #define ASM_NOP6 K8_NOP6
675 #define ASM_NOP7 K8_NOP7
676 #define ASM_NOP8 K8_NOP8
677 #elif defined(CONFIG_MK7)
678 #define ASM_NOP1 K7_NOP1
679 #define ASM_NOP2 K7_NOP2
680 #define ASM_NOP3 K7_NOP3
681 #define ASM_NOP4 K7_NOP4
682 #define ASM_NOP5 K7_NOP5
683 #define ASM_NOP6 K7_NOP6
684 #define ASM_NOP7 K7_NOP7
685 #define ASM_NOP8 K7_NOP8
686 #else
687 #define ASM_NOP1 GENERIC_NOP1
688 #define ASM_NOP2 GENERIC_NOP2
689 #define ASM_NOP3 GENERIC_NOP3
690 #define ASM_NOP4 GENERIC_NOP4
691 #define ASM_NOP5 GENERIC_NOP5
692 #define ASM_NOP6 GENERIC_NOP6
693 #define ASM_NOP7 GENERIC_NOP7
694 #define ASM_NOP8 GENERIC_NOP8
695 #endif
697 #define ASM_NOP_MAX 8
699 /* Prefetch instructions for Pentium III and AMD Athlon */
700 /* It's not worth to care about 3dnow! prefetches for the K6
701 because they are microcoded there and very slow.
702 However we don't do prefetches for pre XP Athlons currently
703 That should be fixed. */
704 #define ARCH_HAS_PREFETCH
705 static inline void prefetch(const void *x)
706 {
707 alternative_input(ASM_NOP4,
708 "prefetchnta (%1)",
709 X86_FEATURE_XMM,
710 "r" (x));
711 }
713 #define ARCH_HAS_PREFETCH
714 #define ARCH_HAS_PREFETCHW
715 #define ARCH_HAS_SPINLOCK_PREFETCH
717 /* 3dnow! prefetch to get an exclusive cache line. Useful for
718 spinlocks to avoid one state transition in the cache coherency protocol. */
719 static inline void prefetchw(const void *x)
720 {
721 alternative_input(ASM_NOP4,
722 "prefetchw (%1)",
723 X86_FEATURE_3DNOW,
724 "r" (x));
725 }
726 #define spin_lock_prefetch(x) prefetchw(x)
728 extern void select_idle_routine(const struct cpuinfo_x86 *c);
730 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
732 extern unsigned long boot_option_idle_override;
733 extern void enable_sep_cpu(void);
734 extern int sysenter_setup(void);
736 #ifdef CONFIG_MTRR
737 extern void mtrr_ap_init(void);
738 extern void mtrr_bp_init(void);
739 #else
740 #define mtrr_ap_init() do {} while (0)
741 #define mtrr_bp_init() do {} while (0)
742 #endif
744 #ifdef CONFIG_X86_MCE
745 extern void mcheck_init(struct cpuinfo_x86 *c);
746 #else
747 #define mcheck_init(c) do {} while(0)
748 #endif
750 #endif /* __ASM_I386_PROCESSOR_H */