ia64/xen-unstable

view xen/include/xen/pci.h @ 19805:2f1fa2215e60

VT-d: pci code cleanup

This patch moves the pci code from iommu.c to pci.c. Instead of setup
pci hierarchy in array bus2bridge in iommu_context_mapping, use
scan_pci_devices once to add all existed PCI devices in system to
alldevs_list and setup pci hierarchy in array bus2bridge. In addition,
implement find_upstream_bridge to find the upstream PCIe-to-PCI/PCIX
bridge or PCI legacy bridge for a PCI device, therefore it's cleanly
to handle context map/unmap for PCI device, even for source-id
setting.

Signed-off-by: Weidong Han <weidong.han@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 19 08:45:20 2009 +0100 (2009-06-19)
parents 42fe00c6f8b4
children
line source
1 /******************************************************************************
2 * pci.h
3 *
4 * PCI access functions.
5 */
7 #ifndef __XEN_PCI_H__
8 #define __XEN_PCI_H__
10 #include <xen/config.h>
11 #include <xen/types.h>
12 #include <xen/list.h>
13 #include <xen/spinlock.h>
15 /*
16 * The PCI interface treats multi-function devices as independent
17 * devices. The slot/function address of each device is encoded
18 * in a single byte as follows:
19 *
20 * 15:8 = bus
21 * 7:3 = slot
22 * 2:0 = function
23 */
24 #define PCI_BUS(bdf) (((bdf) >> 8) & 0xff)
25 #define PCI_SLOT(bdf) (((bdf) >> 3) & 0x1f)
26 #define PCI_FUNC(bdf) ((bdf) & 0x07)
27 #define PCI_DEVFN(d,f) ((((d) & 0x1f) << 3) | ((f) & 0x07))
28 #define PCI_DEVFN2(bdf) ((bdf) & 0xff)
29 #define PCI_BDF(b,d,f) ((((b) & 0xff) << 8) | PCI_DEVFN(d,f))
30 #define PCI_BDF2(b,df) ((((b) & 0xff) << 8) | ((df) & 0xff))
32 #define MAX_MSIX_TABLE_ENTRIES 2048
33 #define MAX_MSIX_TABLE_PAGES 8
34 struct pci_dev_info {
35 unsigned is_extfn;
36 unsigned is_virtfn;
37 struct {
38 u8 bus;
39 u8 devfn;
40 } physfn;
41 };
43 struct pci_dev {
44 struct list_head alldevs_list;
45 struct list_head domain_list;
47 struct list_head msi_list;
48 int msix_table_refcnt[MAX_MSIX_TABLE_PAGES];
49 int msix_table_idx[MAX_MSIX_TABLE_PAGES];
50 spinlock_t msix_table_lock;
52 struct domain *domain;
53 const u8 bus;
54 const u8 devfn;
55 struct pci_dev_info info;
56 };
58 #define for_each_pdev(domain, pdev) \
59 list_for_each_entry(pdev, &(domain->arch.pdev_list), domain_list)
61 /*
62 * The pcidevs_lock protect alldevs_list, and the assignment for the
63 * devices, it also sync the access to the msi capability that is not
64 * interrupt handling related (the mask bit register).
65 */
67 extern spinlock_t pcidevs_lock;
69 enum {
70 DEV_TYPE_PCIe_ENDPOINT,
71 DEV_TYPE_PCIe_BRIDGE, // PCIe root port, switch
72 DEV_TYPE_PCIe2PCI_BRIDGE, // PCIe-to-PCI/PCIx bridge
73 DEV_TYPE_LEGACY_PCI_BRIDGE, // Legacy PCI bridge
74 DEV_TYPE_PCI,
75 };
77 int scan_pci_devices(void);
78 int pdev_type(u8 bus, u8 devfn);
79 int find_upstream_bridge(u8 *bus, u8 *devfn, u8 *secbus);
80 struct pci_dev *alloc_pdev(u8 bus, u8 devfn);
81 void free_pdev(struct pci_dev *pdev);
82 struct pci_dev *pci_lock_pdev(int bus, int devfn);
83 struct pci_dev *pci_lock_domain_pdev(struct domain *d, int bus, int devfn);
85 void pci_release_devices(struct domain *d);
86 int pci_add_device(u8 bus, u8 devfn);
87 int pci_remove_device(u8 bus, u8 devfn);
88 int pci_add_device_ext(u8 bus, u8 devfn, struct pci_dev_info *info);
89 struct pci_dev *pci_get_pdev(int bus, int devfn);
90 struct pci_dev *pci_get_pdev_by_domain(struct domain *d, int bus, int devfn);
92 uint8_t pci_conf_read8(
93 unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg);
94 uint16_t pci_conf_read16(
95 unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg);
96 uint32_t pci_conf_read32(
97 unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg);
98 void pci_conf_write8(
99 unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
100 uint8_t data);
101 void pci_conf_write16(
102 unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
103 uint16_t data);
104 void pci_conf_write32(
105 unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
106 uint32_t data);
107 int pci_mmcfg_read(unsigned int seg, unsigned int bus,
108 unsigned int devfn, int reg, int len, u32 *value);
109 int pci_mmcfg_write(unsigned int seg, unsigned int bus,
110 unsigned int devfn, int reg, int len, u32 value);
111 int pci_find_cap_offset(u8 bus, u8 dev, u8 func, u8 cap);
112 int pci_find_next_cap(u8 bus, unsigned int devfn, u8 pos, int cap);
113 int pci_find_ext_capability(int seg, int bus, int devfn, int cap);
115 int msixtbl_pt_register(struct domain *d, int pirq, uint64_t gtable);
116 void msixtbl_pt_unregister(struct domain *d, int pirq);
118 #endif /* __XEN_PCI_H__ */