ia64/xen-unstable

view xen/arch/ia64/vmx/vmx_minstate.h @ 8370:2d5c57be196d

Remove some unused VTI code segments
Signed-off-by Anthony Xu <anthony.xu@intel.com>
author djm@kirby.fc.hp.com
date Thu Dec 15 16:10:22 2005 -0600 (2005-12-15)
parents 06d84bf87159
children 4834d1e8f26e
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * vmx_minstate.h:
4 * Copyright (c) 2005, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
20 */
22 #include <linux/config.h>
24 #include <asm/asmmacro.h>
25 #include <asm/fpu.h>
26 #include <asm/mmu_context.h>
27 #include <asm/offsets.h>
28 #include <asm/pal.h>
29 #include <asm/pgtable.h>
30 #include <asm/processor.h>
31 #include <asm/ptrace.h>
32 #include <asm/system.h>
33 #include <asm/vmx_pal_vsa.h>
34 #include <asm/vmx_vpd.h>
35 #include <asm/cache.h>
36 #include "entry.h"
38 #define VMX_MINSTATE_START_SAVE_MIN \
39 mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
40 ;; \
41 mov.m r28=ar.rnat; \
42 addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
43 ;; \
44 lfetch.fault.excl.nt1 [r22]; \
45 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
46 mov r23=ar.bspstore; /* save ar.bspstore */ \
47 ;; \
48 mov ar.bspstore=r22; /* switch to kernel RBS */ \
49 ;; \
50 mov r18=ar.bsp; \
51 mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
55 #define VMX_MINSTATE_END_SAVE_MIN \
56 bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
57 ;;
60 #define PAL_VSA_SYNC_READ_CLEANUP_PSR_PL \
61 /* begin to call pal vps sync_read and cleanup psr.pl */ \
62 add r25=IA64_VPD_BASE_OFFSET, r21; \
63 movl r20=__vsa_base; \
64 ;; \
65 ld8 r25=[r25]; /* read vpd base */ \
66 ld8 r20=[r20]; /* read entry point */ \
67 ;; \
68 add r20=PAL_VPS_SYNC_READ,r20; \
69 ;; \
70 { .mii; \
71 add r22=VPD(VPSR),r25; \
72 mov r24=ip; \
73 mov b0=r20; \
74 ;; \
75 }; \
76 { .mmb; \
77 add r24 = 0x20, r24; \
78 mov r16 = cr.ipsr; /* Temp workaround since psr.ic is off */ \
79 br.cond.sptk b0; /* call the service */ \
80 ;; \
81 }; \
82 ld8 r17=[r22]; \
83 /* deposite ipsr bit cpl into vpd.vpsr, since epc will change */ \
84 extr.u r30=r16, IA64_PSR_CPL0_BIT, 2; \
85 ;; \
86 dep r17=r30, r17, IA64_PSR_CPL0_BIT, 2; \
87 extr.u r30=r16, IA64_PSR_BE_BIT, 5; \
88 ;; \
89 dep r17=r30, r17, IA64_PSR_BE_BIT, 5; \
90 extr.u r30=r16, IA64_PSR_RI_BIT, 2; \
91 ;; \
92 dep r17=r30, r17, IA64_PSR_RI_BIT, 2; \
93 ;; \
94 st8 [r22]=r17; \
95 ;;
99 #define IA64_CURRENT_REG IA64_KR(CURRENT) /* r21 is reserved for current pointer */
100 //#define VMX_MINSTATE_GET_CURRENT(reg) mov reg=IA64_CURRENT_REG
101 #define VMX_MINSTATE_GET_CURRENT(reg) mov reg=r21
103 /*
104 * VMX_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
105 * the minimum state necessary that allows us to turn psr.ic back
106 * on.
107 *
108 * Assumed state upon entry:
109 * psr.ic: off
110 * r31: contains saved predicates (pr)
111 *
112 * Upon exit, the state is as follows:
113 * psr.ic: off
114 * r2 = points to &pt_regs.r16
115 * r8 = contents of ar.ccv
116 * r9 = contents of ar.csd
117 * r10 = contents of ar.ssd
118 * r11 = FPSR_DEFAULT
119 * r12 = kernel sp (kernel virtual address)
120 * r13 = points to current task_struct (kernel virtual address)
121 * p15 = TRUE if psr.i is set in cr.ipsr
122 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
123 * preserved
124 *
125 * Note that psr.ic is NOT turned on by this macro. This is so that
126 * we can pass interruption state as arguments to a handler.
127 */
129 #define VMX_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
130 VMX_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
131 mov r27=ar.rsc; /* M */ \
132 mov r20=r1; /* A */ \
133 mov r25=ar.unat; /* M */ \
134 mov r29=cr.ipsr; /* M */ \
135 mov r26=ar.pfs; /* I */ \
136 mov r18=cr.isr; \
137 COVER; /* B;; (or nothing) */ \
138 ;; \
139 tbit.z p6,p0=r29,IA64_PSR_VM_BIT; \
140 ;; \
141 tbit.nz.or p6,p0 = r18,39; \
142 ;; \
143 (p6) br.sptk.few vmx_panic; \
144 tbit.z p0,p15=r29,IA64_PSR_I_BIT; \
145 mov r1=r16; \
146 /* mov r21=r16; */ \
147 /* switch from user to kernel RBS: */ \
148 ;; \
149 invala; /* M */ \
150 SAVE_IFS; \
151 ;; \
152 VMX_MINSTATE_START_SAVE_MIN \
153 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
154 adds r16=PT(CR_IPSR),r1; \
155 ;; \
156 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
157 st8 [r16]=r29; /* save cr.ipsr */ \
158 ;; \
159 lfetch.fault.excl.nt1 [r17]; \
160 tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \
161 mov r29=b0 \
162 ;; \
163 adds r16=PT(R8),r1; /* initialize first base pointer */ \
164 adds r17=PT(R9),r1; /* initialize second base pointer */ \
165 ;; \
166 .mem.offset 0,0; st8.spill [r16]=r8,16; \
167 .mem.offset 8,0; st8.spill [r17]=r9,16; \
168 ;; \
169 .mem.offset 0,0; st8.spill [r16]=r10,24; \
170 .mem.offset 8,0; st8.spill [r17]=r11,24; \
171 ;; \
172 mov r9=cr.iip; /* M */ \
173 mov r10=ar.fpsr; /* M */ \
174 ;; \
175 st8 [r16]=r9,16; /* save cr.iip */ \
176 st8 [r17]=r30,16; /* save cr.ifs */ \
177 sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
178 ;; \
179 st8 [r16]=r25,16; /* save ar.unat */ \
180 st8 [r17]=r26,16; /* save ar.pfs */ \
181 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
182 ;; \
183 st8 [r16]=r27,16; /* save ar.rsc */ \
184 st8 [r17]=r28,16; /* save ar.rnat */ \
185 ;; /* avoid RAW on r16 & r17 */ \
186 st8 [r16]=r23,16; /* save ar.bspstore */ \
187 st8 [r17]=r31,16; /* save predicates */ \
188 ;; \
189 st8 [r16]=r29,16; /* save b0 */ \
190 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
191 ;; \
192 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
193 .mem.offset 8,0; st8.spill [r17]=r12,16; \
194 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
195 ;; \
196 .mem.offset 0,0; st8.spill [r16]=r13,16; \
197 .mem.offset 8,0; st8.spill [r17]=r10,16; /* save ar.fpsr */ \
198 mov r13=r21; /* establish `current' */ \
199 ;; \
200 .mem.offset 0,0; st8.spill [r16]=r15,16; \
201 .mem.offset 8,0; st8.spill [r17]=r14,16; \
202 ;; \
203 .mem.offset 0,0; st8.spill [r16]=r2,16; \
204 .mem.offset 8,0; st8.spill [r17]=r3,16; \
205 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
206 ;; \
207 adds r16=IA64_VCPU_IIPA_OFFSET,r13; \
208 adds r17=IA64_VCPU_ISR_OFFSET,r13; \
209 mov r26=cr.iipa; \
210 mov r27=cr.isr; \
211 ;; \
212 st8 [r16]=r26; \
213 st8 [r17]=r27; \
214 ;; \
215 EXTRA; \
216 mov r8=ar.ccv; \
217 mov r9=ar.csd; \
218 mov r10=ar.ssd; \
219 movl r11=FPSR_DEFAULT; /* L-unit */ \
220 movl r1=__gp; /* establish kernel global pointer */ \
221 ;; \
222 PAL_VSA_SYNC_READ_CLEANUP_PSR_PL \
223 VMX_MINSTATE_END_SAVE_MIN
225 /*
226 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
227 *
228 * Assumed state upon entry:
229 * psr.ic: on
230 * r2: points to &pt_regs.f6
231 * r3: points to &pt_regs.f7
232 * r8: contents of ar.ccv
233 * r9: contents of ar.csd
234 * r10: contents of ar.ssd
235 * r11: FPSR_DEFAULT
236 *
237 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
238 */
239 #define VMX_SAVE_REST \
240 .mem.offset 0,0; st8.spill [r2]=r16,16; \
241 .mem.offset 8,0; st8.spill [r3]=r17,16; \
242 ;; \
243 .mem.offset 0,0; st8.spill [r2]=r18,16; \
244 .mem.offset 8,0; st8.spill [r3]=r19,16; \
245 ;; \
246 .mem.offset 0,0; st8.spill [r2]=r20,16; \
247 .mem.offset 8,0; st8.spill [r3]=r21,16; \
248 mov r18=b6; \
249 ;; \
250 .mem.offset 0,0; st8.spill [r2]=r22,16; \
251 .mem.offset 8,0; st8.spill [r3]=r23,16; \
252 mov r19=b7; \
253 ;; \
254 .mem.offset 0,0; st8.spill [r2]=r24,16; \
255 .mem.offset 8,0; st8.spill [r3]=r25,16; \
256 ;; \
257 .mem.offset 0,0; st8.spill [r2]=r26,16; \
258 .mem.offset 8,0; st8.spill [r3]=r27,16; \
259 ;; \
260 .mem.offset 0,0; st8.spill [r2]=r28,16; \
261 .mem.offset 8,0; st8.spill [r3]=r29,16; \
262 ;; \
263 .mem.offset 0,0; st8.spill [r2]=r30,16; \
264 .mem.offset 8,0; st8.spill [r3]=r31,32; \
265 ;; \
266 mov ar.fpsr=r11; \
267 st8 [r2]=r8,8; \
268 adds r24=PT(B6)-PT(F7),r3; \
269 ;; \
270 stf.spill [r2]=f6,32; \
271 stf.spill [r3]=f7,32; \
272 ;; \
273 stf.spill [r2]=f8,32; \
274 stf.spill [r3]=f9,32; \
275 ;; \
276 stf.spill [r2]=f10,32; \
277 stf.spill [r3]=f11,24; \
278 ;; \
279 .mem.offset 0,0; st8.spill [r2]=r4,16; \
280 .mem.offset 8,0; st8.spill [r3]=r5,16; \
281 ;; \
282 .mem.offset 0,0; st8.spill [r2]=r6,16; \
283 .mem.offset 8,0; st8.spill [r3]=r7; \
284 adds r25=PT(B7)-PT(R7),r3; \
285 ;; \
286 st8 [r24]=r18,16; /* b6 */ \
287 st8 [r25]=r19,16; /* b7 */ \
288 ;; \
289 st8 [r24]=r9; /* ar.csd */ \
290 mov r26=ar.unat; \
291 ;; \
292 st8 [r25]=r10; /* ar.ssd */ \
293 st8 [r2]=r26; /* eml_unat */ \
294 ;;
296 #define VMX_SAVE_MIN_WITH_COVER VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,)
297 #define VMX_SAVE_MIN_WITH_COVER_R19 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19)
298 #define VMX_SAVE_MIN VMX_DO_SAVE_MIN( , mov r30=r0, )