ia64/xen-unstable

view linux-2.6.9-xen-sparse/include/asm-xen/asm-i386/pgtable.h @ 3004:2bebf77dc30e

bitkeeper revision 1.1159.175.1 (419a9b9dCZLKnt1tKvFYyV5cDeDbmQ)

Clean up drivers/char/mem.c patch.
author iap10@labyrinth.cl.cam.ac.uk
date Wed Nov 17 00:30:21 2004 +0000 (2004-11-17)
parents 145b7783c604
children d3865a06ff71
line source
1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
4 #include <linux/config.h>
5 #include <asm-xen/hypervisor.h>
7 /*
8 * The Linux memory management assumes a three-level page table setup. On
9 * the i386, we use that, but "fold" the mid level into the top-level page
10 * table, so that we physically have the same two-level page table as the
11 * i386 mmu expects.
12 *
13 * This file contains the functions and defines necessary to modify and use
14 * the i386 page table tree.
15 */
16 #ifndef __ASSEMBLY__
17 #include <asm/processor.h>
18 #include <asm/fixmap.h>
19 #include <linux/threads.h>
21 #ifndef _I386_BITOPS_H
22 #include <asm/bitops.h>
23 #endif
25 #include <linux/slab.h>
26 #include <linux/list.h>
27 #include <linux/spinlock.h>
29 /*
30 * ZERO_PAGE is a global shared page that is always zero: used
31 * for zero-mapped memory areas etc..
32 */
33 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
34 extern unsigned long empty_zero_page[1024];
35 extern pgd_t swapper_pg_dir[1024];
36 extern kmem_cache_t *pgd_cache;
37 extern kmem_cache_t *pmd_cache;
38 extern kmem_cache_t *pte_cache;
39 extern spinlock_t pgd_lock;
40 extern struct page *pgd_list;
42 void pte_ctor(void *, kmem_cache_t *, unsigned long);
43 void pte_dtor(void *, kmem_cache_t *, unsigned long);
44 void pmd_ctor(void *, kmem_cache_t *, unsigned long);
45 void pgd_ctor(void *, kmem_cache_t *, unsigned long);
46 void pgd_dtor(void *, kmem_cache_t *, unsigned long);
47 void pgtable_cache_init(void);
48 void paging_init(void);
50 /*
51 * The Linux x86 paging architecture is 'compile-time dual-mode', it
52 * implements both the traditional 2-level x86 page tables and the
53 * newer 3-level PAE-mode page tables.
54 */
55 #ifdef CONFIG_X86_PAE
56 # include <asm/pgtable-3level-defs.h>
57 #else
58 # include <asm/pgtable-2level-defs.h>
59 #endif
61 #define PMD_SIZE (1UL << PMD_SHIFT)
62 #define PMD_MASK (~(PMD_SIZE-1))
63 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
64 #define PGDIR_MASK (~(PGDIR_SIZE-1))
66 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
67 #define FIRST_USER_PGD_NR 0
69 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
70 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
72 #define TWOLEVEL_PGDIR_SHIFT 22
73 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
74 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
76 /* Just any arbitrary offset to the start of the vmalloc VM area: the
77 * current 8MB value just means that there will be a 8MB "hole" after the
78 * physical memory until the kernel virtual memory starts. That means that
79 * any out-of-bounds memory accesses will hopefully be caught.
80 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
81 * area for the same reason. ;)
82 */
83 #define VMALLOC_OFFSET (8*1024*1024)
84 #define VMALLOC_START (((unsigned long) high_memory + vmalloc_earlyreserve + \
85 2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1))
86 #ifdef CONFIG_HIGHMEM
87 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
88 #else
89 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
90 #endif
92 extern void * high_memory;
93 extern unsigned long vmalloc_earlyreserve;
95 /*
96 * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
97 * of the Pentium details, but assuming intel did the straightforward
98 * thing, this bit set in the page directory entry just means that
99 * the page directory entry points directly to a 4MB-aligned block of
100 * memory.
101 */
102 #define _PAGE_BIT_PRESENT 0
103 #define _PAGE_BIT_RW 1
104 #define _PAGE_BIT_USER 2
105 #define _PAGE_BIT_PWT 3
106 #define _PAGE_BIT_PCD 4
107 #define _PAGE_BIT_ACCESSED 5
108 #define _PAGE_BIT_DIRTY 6
109 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
110 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
111 #define _PAGE_BIT_UNUSED1 9 /* available for programmer */
112 #define _PAGE_BIT_UNUSED2 10
113 #define _PAGE_BIT_UNUSED3 11
114 #define _PAGE_BIT_NX 63
116 #define _PAGE_PRESENT 0x001
117 #define _PAGE_RW 0x002
118 #define _PAGE_USER 0x004
119 #define _PAGE_PWT 0x008
120 #define _PAGE_PCD 0x010
121 #define _PAGE_ACCESSED 0x020
122 #define _PAGE_DIRTY 0x040
123 #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
124 #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
125 #define _PAGE_UNUSED1 0x200 /* available for programmer */
126 #define _PAGE_UNUSED2 0x400
127 #define _PAGE_UNUSED3 0x800
129 #define _PAGE_FILE 0x040 /* set:pagecache unset:swap */
130 #define _PAGE_PROTNONE 0x080 /* If not present */
131 #ifdef CONFIG_X86_PAE
132 #define _PAGE_NX (1ULL<<_PAGE_BIT_NX)
133 #else
134 #define _PAGE_NX 0
135 #endif
137 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
138 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
139 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
141 #define PAGE_NONE \
142 __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
143 #define PAGE_SHARED \
144 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
146 #define PAGE_SHARED_EXEC \
147 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
148 #define PAGE_COPY_NOEXEC \
149 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
150 #define PAGE_COPY_EXEC \
151 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
152 #define PAGE_COPY \
153 PAGE_COPY_NOEXEC
154 #define PAGE_READONLY \
155 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
156 #define PAGE_READONLY_EXEC \
157 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
159 #define _PAGE_KERNEL \
160 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
161 #define _PAGE_KERNEL_EXEC \
162 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
164 extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
165 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
166 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD)
167 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
168 #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
170 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
171 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
172 #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
173 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
174 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
175 #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
177 /*
178 * The i386 can't do page protection for execute, and considers that
179 * the same are read. Also, write permissions imply read permissions.
180 * This is the closest we can get..
181 */
182 #define __P000 PAGE_NONE
183 #define __P001 PAGE_READONLY
184 #define __P010 PAGE_COPY
185 #define __P011 PAGE_COPY
186 #define __P100 PAGE_READONLY_EXEC
187 #define __P101 PAGE_READONLY_EXEC
188 #define __P110 PAGE_COPY_EXEC
189 #define __P111 PAGE_COPY_EXEC
191 #define __S000 PAGE_NONE
192 #define __S001 PAGE_READONLY
193 #define __S010 PAGE_SHARED
194 #define __S011 PAGE_SHARED
195 #define __S100 PAGE_READONLY_EXEC
196 #define __S101 PAGE_READONLY_EXEC
197 #define __S110 PAGE_SHARED_EXEC
198 #define __S111 PAGE_SHARED_EXEC
200 /*
201 * Define this if things work differently on an i386 and an i486:
202 * it will (on an i486) warn about kernel memory accesses that are
203 * done without a 'verify_area(VERIFY_WRITE,..)'
204 */
205 #undef TEST_VERIFY_AREA
207 /* The boot page tables (all created as a single array) */
208 extern unsigned long pg0[];
210 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
211 #define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
213 #define pmd_none(x) (!pmd_val(x))
214 /* pmd_present doesn't just test the _PAGE_PRESENT bit since wr.p.t.
215 can temporarily clear it. */
216 #define pmd_present(x) (pmd_val(x))
217 /* pmd_clear below */
218 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER & ~_PAGE_PRESENT)) != (_KERNPG_TABLE & ~_PAGE_PRESENT))
221 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
223 /*
224 * The following only work if pte_present() is true.
225 * Undefined behaviour if not..
226 */
227 static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
228 static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
229 static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
230 static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
231 static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
233 /*
234 * The following only works if pte_present() is not true.
235 */
236 static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
238 static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
239 static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
240 static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
241 static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
242 static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
243 static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
244 static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
245 static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
246 static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
247 static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
249 #ifdef CONFIG_X86_PAE
250 # include <asm/pgtable-3level.h>
251 #else
252 # include <asm/pgtable-2level.h>
253 #endif
255 static inline int ptep_test_and_clear_dirty(pte_t *ptep)
256 {
257 pte_t pte = *ptep;
258 int ret = pte_dirty(pte);
259 if (ret)
260 xen_l1_entry_update(ptep, pte_mkclean(pte).pte_low);
261 return ret;
262 }
264 static inline int ptep_test_and_clear_young(pte_t *ptep)
265 {
266 pte_t pte = *ptep;
267 int ret = pte_young(pte);
268 if (ret)
269 xen_l1_entry_update(ptep, pte_mkold(pte).pte_low);
270 return ret;
271 }
273 static inline void ptep_set_wrprotect(pte_t *ptep)
274 {
275 pte_t pte = *ptep;
276 if (pte_write(pte))
277 set_pte(ptep, pte_wrprotect(pte));
278 }
279 static inline void ptep_mkdirty(pte_t *ptep)
280 {
281 pte_t pte = *ptep;
282 if (!pte_dirty(pte))
283 xen_l1_entry_update(ptep, pte_mkdirty(pte).pte_low);
284 }
286 /*
287 * Macro to mark a page protection value as "uncacheable". On processors which do not support
288 * it, this is a no-op.
289 */
290 #define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \
291 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
293 /*
294 * Conversion functions: convert a page and protection to a page entry,
295 * and a page entry and page directory to the page they refer to.
296 */
298 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
299 #define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
301 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
302 {
303 pte.pte_low &= _PAGE_CHG_MASK;
304 pte.pte_low |= pgprot_val(newprot);
305 #ifdef CONFIG_X86_PAE
306 /*
307 * Chop off the NX bit (if present), and add the NX portion of
308 * the newprot (if present):
309 */
310 pte.pte_high &= ~(1 << (_PAGE_BIT_NX - 32));
311 pte.pte_high |= (pgprot_val(newprot) >> 32) & \
312 (__supported_pte_mask >> 32);
313 #endif
314 return pte;
315 }
317 #define page_pte(page) page_pte_prot(page, __pgprot(0))
319 #define pmd_page_kernel(pmd) \
320 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
322 #define pmd_clear(xp) do { \
323 set_pmd(xp, __pmd(0)); \
324 xen_flush_page_update_queue(); \
325 } while (0)
327 #ifndef CONFIG_DISCONTIGMEM
328 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
329 #endif /* !CONFIG_DISCONTIGMEM */
331 #define pmd_large(pmd) \
332 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
334 /*
335 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
336 *
337 * this macro returns the index of the entry in the pgd page which would
338 * control the given virtual address
339 */
340 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
342 /*
343 * pgd_offset() returns a (pgd_t *)
344 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
345 */
346 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
348 /*
349 * a shortcut which implies the use of the kernel's pgd, instead
350 * of a process's
351 */
352 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
354 /*
355 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
356 *
357 * this macro returns the index of the entry in the pmd page which would
358 * control the given virtual address
359 */
360 #define pmd_index(address) \
361 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
363 /*
364 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
365 *
366 * this macro returns the index of the entry in the pte page which would
367 * control the given virtual address
368 */
369 #define pte_index(address) \
370 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
371 #define pte_offset_kernel(dir, address) \
372 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
374 /*
375 * Helper function that returns the kernel pagetable entry controlling
376 * the virtual address 'address'. NULL means no pagetable entry present.
377 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
378 * as a pte too.
379 */
380 extern pte_t *lookup_address(unsigned long address);
382 /*
383 * Make a given kernel text page executable/non-executable.
384 * Returns the previous executability setting of that page (which
385 * is used to restore the previous state). Used by the SMP bootup code.
386 * NOTE: this is an __init function for security reasons.
387 */
388 #ifdef CONFIG_X86_PAE
389 extern int set_kernel_exec(unsigned long vaddr, int enable);
390 #else
391 static inline int set_kernel_exec(unsigned long vaddr, int enable) { return 0;}
392 #endif
394 #if defined(CONFIG_HIGHPTE)
395 #define pte_offset_map(dir, address) \
396 ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE0) + \
397 pte_index(address))
398 #define pte_offset_map_nested(dir, address) \
399 ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE1) + \
400 pte_index(address))
401 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
402 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
403 #else
404 #define pte_offset_map(dir, address) \
405 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
406 #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
407 #define pte_unmap(pte) do { } while (0)
408 #define pte_unmap_nested(pte) do { } while (0)
409 #endif
411 /*
412 * The i386 doesn't have any external MMU info: the kernel page
413 * tables contain all the necessary information.
414 *
415 * Also, we only update the dirty/accessed state if we set
416 * the dirty bit by hand in the kernel, since the hardware
417 * will do the accessed bit for us, and we don't want to
418 * race with other CPU's that might be updating the dirty
419 * bit at the same time.
420 */
421 #define update_mmu_cache(vma,address,pte) do { } while (0)
422 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
424 #if 0
425 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
426 do { \
427 if (__dirty) { \
428 queue_l1_entry_update((__ptep), (__entry).pte_low); \
429 flush_tlb_page(__vma, __address); \
430 xen_flush_page_update_queue(); \
431 } \
432 } while (0)
433 #else
434 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
435 do { \
436 if (__dirty) { \
437 if ( likely(vma->vm_mm == current->mm) ) { \
438 xen_flush_page_update_queue(); \
439 HYPERVISOR_update_va_mapping(address>>PAGE_SHIFT, entry, UVMF_INVLPG); \
440 } else { \
441 xen_l1_entry_update((__ptep), (__entry).pte_low); \
442 flush_tlb_page(__vma, __address); \
443 } \
444 } \
445 } while (0)
447 #endif
449 #define __HAVE_ARCH_PTEP_ESTABLISH
450 #define ptep_establish(__vma, __address, __ptep, __entry) \
451 do { \
452 ptep_set_access_flags(__vma, __address, __ptep, __entry, 1); \
453 } while (0)
455 #define __HAVE_ARCH_PTEP_ESTABLISH_NEW
456 #define ptep_establish_new(__vma, __address, __ptep, __entry) \
457 do { \
458 if ( likely((__vma)->vm_mm == current->mm) ) { \
459 xen_flush_page_update_queue(); \
460 HYPERVISOR_update_va_mapping((__address)>>PAGE_SHIFT, \
461 __entry, 0); \
462 } else { \
463 xen_l1_entry_update((__ptep), (__entry).pte_low); \
464 } \
465 } while (0)
467 /* NOTE: make_page* callers must call flush_page_update_queue() */
468 static inline void __make_page_readonly(void *va)
469 {
470 pgd_t *pgd = pgd_offset_k((unsigned long)va);
471 pmd_t *pmd = pmd_offset(pgd, (unsigned long)va);
472 pte_t *pte = pte_offset_kernel(pmd, (unsigned long)va);
473 queue_l1_entry_update(pte, (*(unsigned long *)pte)&~_PAGE_RW);
474 }
476 static inline void __make_page_writable(void *va)
477 {
478 pgd_t *pgd = pgd_offset_k((unsigned long)va);
479 pmd_t *pmd = pmd_offset(pgd, (unsigned long)va);
480 pte_t *pte = pte_offset_kernel(pmd, (unsigned long)va);
481 queue_l1_entry_update(pte, (*(unsigned long *)pte)|_PAGE_RW);
482 }
484 static inline void make_page_readonly(void *va)
485 {
486 pgd_t *pgd = pgd_offset_k((unsigned long)va);
487 pmd_t *pmd = pmd_offset(pgd, (unsigned long)va);
488 pte_t *pte = pte_offset_kernel(pmd, (unsigned long)va);
489 queue_l1_entry_update(pte, (*(unsigned long *)pte)&~_PAGE_RW);
490 if ( (unsigned long)va >= VMALLOC_START )
491 __make_page_readonly(machine_to_virt(
492 *(unsigned long *)pte&PAGE_MASK));
493 }
495 static inline void make_page_writable(void *va)
496 {
497 pgd_t *pgd = pgd_offset_k((unsigned long)va);
498 pmd_t *pmd = pmd_offset(pgd, (unsigned long)va);
499 pte_t *pte = pte_offset_kernel(pmd, (unsigned long)va);
500 queue_l1_entry_update(pte, (*(unsigned long *)pte)|_PAGE_RW);
501 if ( (unsigned long)va >= VMALLOC_START )
502 __make_page_writable(machine_to_virt(
503 *(unsigned long *)pte&PAGE_MASK));
504 }
506 static inline void make_pages_readonly(void *va, unsigned int nr)
507 {
508 while ( nr-- != 0 )
509 {
510 make_page_readonly(va);
511 va = (void *)((unsigned long)va + PAGE_SIZE);
512 }
513 }
515 static inline void make_pages_writable(void *va, unsigned int nr)
516 {
517 while ( nr-- != 0 )
518 {
519 make_page_writable(va);
520 va = (void *)((unsigned long)va + PAGE_SIZE);
521 }
522 }
524 static inline unsigned long arbitrary_virt_to_phys(void *va)
525 {
526 pgd_t *pgd = pgd_offset_k((unsigned long)va);
527 pmd_t *pmd = pmd_offset(pgd, (unsigned long)va);
528 pte_t *pte = pte_offset_kernel(pmd, (unsigned long)va);
529 unsigned long pa = (*(unsigned long *)pte) & PAGE_MASK;
530 return pa | ((unsigned long)va & (PAGE_SIZE-1));
531 }
533 #endif /* !__ASSEMBLY__ */
535 #ifndef CONFIG_DISCONTIGMEM
536 #define kern_addr_valid(addr) (1)
537 #endif /* !CONFIG_DISCONTIGMEM */
539 #define io_remap_page_range(vma,from,phys,size,prot) \
540 direct_remap_area_pages(vma->vm_mm,from,phys,size,prot,DOMID_IO)
542 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
543 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
544 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
545 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
546 #define __HAVE_ARCH_PTEP_MKDIRTY
547 #define __HAVE_ARCH_PTE_SAME
548 #include <asm-generic/pgtable.h>
550 #endif /* _I386_PGTABLE_H */