ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/pal.h @ 13905:2b3dd681dbce

[IA64] Fix I&D cache incoherency after vcpu migration

Windows on HVM ocasionally crashes with BSOD especially on boot time.
I finally found out the cause is PAL_CACHE_FLUSH(cache_type=4).
The cache_type means an argument of PAL_CACHE_FLUSH and cache_type=4
makes local instruction caches coherent with the data caches.
See SDM vol2 11.10.3, PAL_CACHE_FLUSH.
FYI, Linux never uses cache_type=4.

Currently PAL_CACHE_FLUSH is called on only local cpu and caches on the
other cpus are still incoherent.

Attached patch does:
- When cache_type=1,2,3 that means flushing caches on local cpus,
caches on the other cpus becomes to be flushed also.
It might be overkill and not efficient. But I think it's permissive
since these cache_type are seldom used.

- When cache_type=4, the actual PAL call to the other cpus is deferred
until the vcpu migration occurs or the cpu becomes idle.
Since Windows uses cache_type=4 quite often and many vcpus on SMP
environment call PAL_CACHE_FLUSH simultaneously.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author awilliam@xenbuild2.aw
date Thu Feb 15 10:25:33 2007 -0700 (2007-02-15)
parents 8643b4d778f5
children b235b68a0f4f
line source
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
4 /*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
21 * 00/05/25 eranian Support for stack calls, and static physical calls
22 * 00/06/18 eranian Support for stacked physical calls
23 */
25 /*
26 * Note that some of these calls use a static-register only calling
27 * convention which has nothing to do with the regular calling
28 * convention.
29 */
30 #define PAL_CACHE_FLUSH 1 /* flush i/d cache */
31 #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
32 #define PAL_CACHE_INIT 3 /* initialize i/d cache */
33 #define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */
34 #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
35 #define PAL_PTCE_INFO 6 /* purge TLB info */
36 #define PAL_VM_INFO 7 /* return supported virtual memory features */
37 #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
38 #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
39 #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
40 #define PAL_DEBUG_INFO 11 /* get number of debug registers */
41 #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
42 #define PAL_FREQ_BASE 13 /* base frequency of the platform */
43 #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
44 #define PAL_PERF_MON_INFO 15 /* return performance monitor info */
45 #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
46 #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
47 #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
48 #define PAL_RSE_INFO 19 /* return rse information */
49 #define PAL_VERSION 20 /* return version of PAL code */
50 #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
51 #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
52 #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
53 #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
54 #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
55 #define PAL_MC_RESUME 26 /* Return to interrupted process */
56 #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
57 #define PAL_HALT 28 /* enter the low power HALT state */
58 #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
59 #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
60 #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
61 #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
62 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
63 #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
65 #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
66 #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
67 #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
68 #define PAL_SHUTDOWN 40 /* enter processor shutdown state */
69 #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
70 #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
72 #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
73 #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
74 #define PAL_TEST_PROC 258 /* perform late processor self-test */
75 #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
76 #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
77 #define PAL_VM_TR_READ 261 /* read contents of translation register */
79 #ifndef __ASSEMBLY__
81 #include <linux/types.h>
82 #include <asm/fpu.h>
84 /*
85 * Data types needed to pass information into PAL procedures and
86 * interpret information returned by them.
87 */
89 /* Return status from the PAL procedure */
90 typedef s64 pal_status_t;
92 #define PAL_STATUS_SUCCESS 0 /* No error */
93 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
94 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
95 #define PAL_STATUS_ERROR (-3) /* Error */
96 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
97 * specified level and type of
98 * cache without sideeffects
99 * and "restrict" was 1
100 */
102 /* Processor cache level in the heirarchy */
103 typedef u64 pal_cache_level_t;
104 #define PAL_CACHE_LEVEL_L0 0 /* L0 */
105 #define PAL_CACHE_LEVEL_L1 1 /* L1 */
106 #define PAL_CACHE_LEVEL_L2 2 /* L2 */
109 /* Processor cache type at a particular level in the heirarchy */
111 typedef u64 pal_cache_type_t;
112 #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
113 #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
114 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
115 #ifdef XEN
116 #define PAL_CACHE_TYPE_COHERENT 4 /* Make I&D-cache coherent */
117 #endif
120 #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
121 #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
123 /* Processor cache line size in bytes */
124 typedef int pal_cache_line_size_t;
126 /* Processor cache line state */
127 typedef u64 pal_cache_line_state_t;
128 #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
129 #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
130 #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
131 #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
133 typedef struct pal_freq_ratio {
134 u64 den : 32, num : 32; /* numerator & denominator */
135 } itc_ratio, proc_ratio;
137 typedef union pal_cache_config_info_1_s {
138 struct {
139 u64 u : 1, /* 0 Unified cache ? */
140 at : 2, /* 2-1 Cache mem attr*/
141 reserved : 5, /* 7-3 Reserved */
142 associativity : 8, /* 16-8 Associativity*/
143 line_size : 8, /* 23-17 Line size */
144 stride : 8, /* 31-24 Stride */
145 store_latency : 8, /*39-32 Store latency*/
146 load_latency : 8, /* 47-40 Load latency*/
147 store_hints : 8, /* 55-48 Store hints*/
148 load_hints : 8; /* 63-56 Load hints */
149 } pcci1_bits;
150 u64 pcci1_data;
151 } pal_cache_config_info_1_t;
153 typedef union pal_cache_config_info_2_s {
154 struct {
155 u64 cache_size : 32, /*cache size in bytes*/
158 alias_boundary : 8, /* 39-32 aliased addr
159 * separation for max
160 * performance.
161 */
162 tag_ls_bit : 8, /* 47-40 LSb of addr*/
163 tag_ms_bit : 8, /* 55-48 MSb of addr*/
164 reserved : 8; /* 63-56 Reserved */
165 } pcci2_bits;
166 u64 pcci2_data;
167 } pal_cache_config_info_2_t;
170 typedef struct pal_cache_config_info_s {
171 pal_status_t pcci_status;
172 pal_cache_config_info_1_t pcci_info_1;
173 pal_cache_config_info_2_t pcci_info_2;
174 u64 pcci_reserved;
175 } pal_cache_config_info_t;
177 #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
178 #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
179 #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
180 #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
181 #define pcci_stride pcci_info_1.pcci1_bits.stride
182 #define pcci_line_size pcci_info_1.pcci1_bits.line_size
183 #define pcci_assoc pcci_info_1.pcci1_bits.associativity
184 #define pcci_cache_attr pcci_info_1.pcci1_bits.at
185 #define pcci_unified pcci_info_1.pcci1_bits.u
186 #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
187 #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
188 #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
189 #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
193 /* Possible values for cache attributes */
195 #define PAL_CACHE_ATTR_WT 0 /* Write through cache */
196 #define PAL_CACHE_ATTR_WB 1 /* Write back cache */
197 #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
198 * back depending on TLB
199 * memory attributes
200 */
203 /* Possible values for cache hints */
205 #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
206 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
207 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
209 /* Processor cache protection information */
210 typedef union pal_cache_protection_element_u {
211 u32 pcpi_data;
212 struct {
213 u32 data_bits : 8, /* # data bits covered by
214 * each unit of protection
215 */
217 tagprot_lsb : 6, /* Least -do- */
218 tagprot_msb : 6, /* Most Sig. tag address
219 * bit that this
220 * protection covers.
221 */
222 prot_bits : 6, /* # of protection bits */
223 method : 4, /* Protection method */
224 t_d : 2; /* Indicates which part
225 * of the cache this
226 * protection encoding
227 * applies.
228 */
229 } pcp_info;
230 } pal_cache_protection_element_t;
232 #define pcpi_cache_prot_part pcp_info.t_d
233 #define pcpi_prot_method pcp_info.method
234 #define pcpi_prot_bits pcp_info.prot_bits
235 #define pcpi_tagprot_msb pcp_info.tagprot_msb
236 #define pcpi_tagprot_lsb pcp_info.tagprot_lsb
237 #define pcpi_data_bits pcp_info.data_bits
239 /* Processor cache part encodings */
240 #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
241 #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
242 #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
243 * more significant )
244 */
245 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
246 * more significant )
247 */
248 #define PAL_CACHE_PROT_PART_MAX 6
251 typedef struct pal_cache_protection_info_s {
252 pal_status_t pcpi_status;
253 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
254 } pal_cache_protection_info_t;
257 /* Processor cache protection method encodings */
258 #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
259 #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
260 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
261 #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
264 /* Processor cache line identification in the heirarchy */
265 typedef union pal_cache_line_id_u {
266 u64 pclid_data;
267 struct {
268 u64 cache_type : 8, /* 7-0 cache type */
269 level : 8, /* 15-8 level of the
270 * cache in the
271 * heirarchy.
272 */
273 way : 8, /* 23-16 way in the set
274 */
275 part : 8, /* 31-24 part of the
276 * cache
277 */
278 reserved : 32; /* 63-32 is reserved*/
279 } pclid_info_read;
280 struct {
281 u64 cache_type : 8, /* 7-0 cache type */
282 level : 8, /* 15-8 level of the
283 * cache in the
284 * heirarchy.
285 */
286 way : 8, /* 23-16 way in the set
287 */
288 part : 8, /* 31-24 part of the
289 * cache
290 */
291 mesi : 8, /* 39-32 cache line
292 * state
293 */
294 start : 8, /* 47-40 lsb of data to
295 * invert
296 */
297 length : 8, /* 55-48 #bits to
298 * invert
299 */
300 trigger : 8; /* 63-56 Trigger error
301 * by doing a load
302 * after the write
303 */
305 } pclid_info_write;
306 } pal_cache_line_id_u_t;
308 #define pclid_read_part pclid_info_read.part
309 #define pclid_read_way pclid_info_read.way
310 #define pclid_read_level pclid_info_read.level
311 #define pclid_read_cache_type pclid_info_read.cache_type
313 #define pclid_write_trigger pclid_info_write.trigger
314 #define pclid_write_length pclid_info_write.length
315 #define pclid_write_start pclid_info_write.start
316 #define pclid_write_mesi pclid_info_write.mesi
317 #define pclid_write_part pclid_info_write.part
318 #define pclid_write_way pclid_info_write.way
319 #define pclid_write_level pclid_info_write.level
320 #define pclid_write_cache_type pclid_info_write.cache_type
322 /* Processor cache line part encodings */
323 #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
324 #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
325 #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
326 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
327 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
328 * protection
329 */
330 typedef struct pal_cache_line_info_s {
331 pal_status_t pcli_status; /* Return status of the read cache line
332 * info call.
333 */
334 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
335 u64 pcli_data_len; /* data length in bits */
336 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
338 } pal_cache_line_info_t;
341 /* Machine Check related crap */
343 /* Pending event status bits */
344 typedef u64 pal_mc_pending_events_t;
346 #define PAL_MC_PENDING_MCA (1 << 0)
347 #define PAL_MC_PENDING_INIT (1 << 1)
349 /* Error information type */
350 typedef u64 pal_mc_info_index_t;
352 #define PAL_MC_INFO_PROCESSOR 0 /* Processor */
353 #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
354 #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
355 #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
356 #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
357 #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
358 #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
359 #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
360 * dependent
361 */
364 typedef struct pal_process_state_info_s {
365 u64 reserved1 : 2,
366 rz : 1, /* PAL_CHECK processor
367 * rendezvous
368 * successful.
369 */
371 ra : 1, /* PAL_CHECK attempted
372 * a rendezvous.
373 */
374 me : 1, /* Distinct multiple
375 * errors occurred
376 */
378 mn : 1, /* Min. state save
379 * area has been
380 * registered with PAL
381 */
383 sy : 1, /* Storage integrity
384 * synched
385 */
388 co : 1, /* Continuable */
389 ci : 1, /* MC isolated */
390 us : 1, /* Uncontained storage
391 * damage.
392 */
395 hd : 1, /* Non-essential hw
396 * lost (no loss of
397 * functionality)
398 * causing the
399 * processor to run in
400 * degraded mode.
401 */
403 tl : 1, /* 1 => MC occurred
404 * after an instr was
405 * executed but before
406 * the trap that
407 * resulted from instr
408 * execution was
409 * generated.
410 * (Trap Lost )
411 */
412 mi : 1, /* More information available
413 * call PAL_MC_ERROR_INFO
414 */
415 pi : 1, /* Precise instruction pointer */
416 pm : 1, /* Precise min-state save area */
418 dy : 1, /* Processor dynamic
419 * state valid
420 */
423 in : 1, /* 0 = MC, 1 = INIT */
424 rs : 1, /* RSE valid */
425 cm : 1, /* MC corrected */
426 ex : 1, /* MC is expected */
427 cr : 1, /* Control regs valid*/
428 pc : 1, /* Perf cntrs valid */
429 dr : 1, /* Debug regs valid */
430 tr : 1, /* Translation regs
431 * valid
432 */
433 rr : 1, /* Region regs valid */
434 ar : 1, /* App regs valid */
435 br : 1, /* Branch regs valid */
436 pr : 1, /* Predicate registers
437 * valid
438 */
440 fp : 1, /* fp registers valid*/
441 b1 : 1, /* Preserved bank one
442 * general registers
443 * are valid
444 */
445 b0 : 1, /* Preserved bank zero
446 * general registers
447 * are valid
448 */
449 gr : 1, /* General registers
450 * are valid
451 * (excl. banked regs)
452 */
453 dsize : 16, /* size of dynamic
454 * state returned
455 * by the processor
456 */
458 reserved2 : 11,
459 cc : 1, /* Cache check */
460 tc : 1, /* TLB check */
461 bc : 1, /* Bus check */
462 rc : 1, /* Register file check */
463 uc : 1; /* Uarch check */
465 } pal_processor_state_info_t;
467 typedef struct pal_cache_check_info_s {
468 u64 op : 4, /* Type of cache
469 * operation that
470 * caused the machine
471 * check.
472 */
473 level : 2, /* Cache level */
474 reserved1 : 2,
475 dl : 1, /* Failure in data part
476 * of cache line
477 */
478 tl : 1, /* Failure in tag part
479 * of cache line
480 */
481 dc : 1, /* Failure in dcache */
482 ic : 1, /* Failure in icache */
483 mesi : 3, /* Cache line state */
484 mv : 1, /* mesi valid */
485 way : 5, /* Way in which the
486 * error occurred
487 */
488 wiv : 1, /* Way field valid */
489 reserved2 : 10,
491 index : 20, /* Cache line index */
492 reserved3 : 2,
494 is : 1, /* instruction set (1 == ia32) */
495 iv : 1, /* instruction set field valid */
496 pl : 2, /* privilege level */
497 pv : 1, /* privilege level field valid */
498 mcc : 1, /* Machine check corrected */
499 tv : 1, /* Target address
500 * structure is valid
501 */
502 rq : 1, /* Requester identifier
503 * structure is valid
504 */
505 rp : 1, /* Responder identifier
506 * structure is valid
507 */
508 pi : 1; /* Precise instruction pointer
509 * structure is valid
510 */
511 } pal_cache_check_info_t;
513 typedef struct pal_tlb_check_info_s {
515 u64 tr_slot : 8, /* Slot# of TR where
516 * error occurred
517 */
518 trv : 1, /* tr_slot field is valid */
519 reserved1 : 1,
520 level : 2, /* TLB level where failure occurred */
521 reserved2 : 4,
522 dtr : 1, /* Fail in data TR */
523 itr : 1, /* Fail in inst TR */
524 dtc : 1, /* Fail in data TC */
525 itc : 1, /* Fail in inst. TC */
526 op : 4, /* Cache operation */
527 reserved3 : 30,
529 is : 1, /* instruction set (1 == ia32) */
530 iv : 1, /* instruction set field valid */
531 pl : 2, /* privilege level */
532 pv : 1, /* privilege level field valid */
533 mcc : 1, /* Machine check corrected */
534 tv : 1, /* Target address
535 * structure is valid
536 */
537 rq : 1, /* Requester identifier
538 * structure is valid
539 */
540 rp : 1, /* Responder identifier
541 * structure is valid
542 */
543 pi : 1; /* Precise instruction pointer
544 * structure is valid
545 */
546 } pal_tlb_check_info_t;
548 typedef struct pal_bus_check_info_s {
549 u64 size : 5, /* Xaction size */
550 ib : 1, /* Internal bus error */
551 eb : 1, /* External bus error */
552 cc : 1, /* Error occurred
553 * during cache-cache
554 * transfer.
555 */
556 type : 8, /* Bus xaction type*/
557 sev : 5, /* Bus error severity*/
558 hier : 2, /* Bus hierarchy level */
559 reserved1 : 1,
560 bsi : 8, /* Bus error status
561 * info
562 */
563 reserved2 : 22,
565 is : 1, /* instruction set (1 == ia32) */
566 iv : 1, /* instruction set field valid */
567 pl : 2, /* privilege level */
568 pv : 1, /* privilege level field valid */
569 mcc : 1, /* Machine check corrected */
570 tv : 1, /* Target address
571 * structure is valid
572 */
573 rq : 1, /* Requester identifier
574 * structure is valid
575 */
576 rp : 1, /* Responder identifier
577 * structure is valid
578 */
579 pi : 1; /* Precise instruction pointer
580 * structure is valid
581 */
582 } pal_bus_check_info_t;
584 typedef struct pal_reg_file_check_info_s {
585 u64 id : 4, /* Register file identifier */
586 op : 4, /* Type of register
587 * operation that
588 * caused the machine
589 * check.
590 */
591 reg_num : 7, /* Register number */
592 rnv : 1, /* reg_num valid */
593 reserved2 : 38,
595 is : 1, /* instruction set (1 == ia32) */
596 iv : 1, /* instruction set field valid */
597 pl : 2, /* privilege level */
598 pv : 1, /* privilege level field valid */
599 mcc : 1, /* Machine check corrected */
600 reserved3 : 3,
601 pi : 1; /* Precise instruction pointer
602 * structure is valid
603 */
604 } pal_reg_file_check_info_t;
606 typedef struct pal_uarch_check_info_s {
607 u64 sid : 5, /* Structure identification */
608 level : 3, /* Level of failure */
609 array_id : 4, /* Array identification */
610 op : 4, /* Type of
611 * operation that
612 * caused the machine
613 * check.
614 */
615 way : 6, /* Way of structure */
616 wv : 1, /* way valid */
617 xv : 1, /* index valid */
618 reserved1 : 8,
619 index : 8, /* Index or set of the uarch
620 * structure that failed.
621 */
622 reserved2 : 24,
624 is : 1, /* instruction set (1 == ia32) */
625 iv : 1, /* instruction set field valid */
626 pl : 2, /* privilege level */
627 pv : 1, /* privilege level field valid */
628 mcc : 1, /* Machine check corrected */
629 tv : 1, /* Target address
630 * structure is valid
631 */
632 rq : 1, /* Requester identifier
633 * structure is valid
634 */
635 rp : 1, /* Responder identifier
636 * structure is valid
637 */
638 pi : 1; /* Precise instruction pointer
639 * structure is valid
640 */
641 } pal_uarch_check_info_t;
643 typedef union pal_mc_error_info_u {
644 u64 pmei_data;
645 pal_processor_state_info_t pme_processor;
646 pal_cache_check_info_t pme_cache;
647 pal_tlb_check_info_t pme_tlb;
648 pal_bus_check_info_t pme_bus;
649 pal_reg_file_check_info_t pme_reg_file;
650 pal_uarch_check_info_t pme_uarch;
651 } pal_mc_error_info_t;
653 #define pmci_proc_unknown_check pme_processor.uc
654 #define pmci_proc_bus_check pme_processor.bc
655 #define pmci_proc_tlb_check pme_processor.tc
656 #define pmci_proc_cache_check pme_processor.cc
657 #define pmci_proc_dynamic_state_size pme_processor.dsize
658 #define pmci_proc_gpr_valid pme_processor.gr
659 #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
660 #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
661 #define pmci_proc_fp_valid pme_processor.fp
662 #define pmci_proc_predicate_regs_valid pme_processor.pr
663 #define pmci_proc_branch_regs_valid pme_processor.br
664 #define pmci_proc_app_regs_valid pme_processor.ar
665 #define pmci_proc_region_regs_valid pme_processor.rr
666 #define pmci_proc_translation_regs_valid pme_processor.tr
667 #define pmci_proc_debug_regs_valid pme_processor.dr
668 #define pmci_proc_perf_counters_valid pme_processor.pc
669 #define pmci_proc_control_regs_valid pme_processor.cr
670 #define pmci_proc_machine_check_expected pme_processor.ex
671 #define pmci_proc_machine_check_corrected pme_processor.cm
672 #define pmci_proc_rse_valid pme_processor.rs
673 #define pmci_proc_machine_check_or_init pme_processor.in
674 #define pmci_proc_dynamic_state_valid pme_processor.dy
675 #define pmci_proc_operation pme_processor.op
676 #define pmci_proc_trap_lost pme_processor.tl
677 #define pmci_proc_hardware_damage pme_processor.hd
678 #define pmci_proc_uncontained_storage_damage pme_processor.us
679 #define pmci_proc_machine_check_isolated pme_processor.ci
680 #define pmci_proc_continuable pme_processor.co
681 #define pmci_proc_storage_intergrity_synced pme_processor.sy
682 #define pmci_proc_min_state_save_area_regd pme_processor.mn
683 #define pmci_proc_distinct_multiple_errors pme_processor.me
684 #define pmci_proc_pal_attempted_rendezvous pme_processor.ra
685 #define pmci_proc_pal_rendezvous_complete pme_processor.rz
688 #define pmci_cache_level pme_cache.level
689 #define pmci_cache_line_state pme_cache.mesi
690 #define pmci_cache_line_state_valid pme_cache.mv
691 #define pmci_cache_line_index pme_cache.index
692 #define pmci_cache_instr_cache_fail pme_cache.ic
693 #define pmci_cache_data_cache_fail pme_cache.dc
694 #define pmci_cache_line_tag_fail pme_cache.tl
695 #define pmci_cache_line_data_fail pme_cache.dl
696 #define pmci_cache_operation pme_cache.op
697 #define pmci_cache_way_valid pme_cache.wv
698 #define pmci_cache_target_address_valid pme_cache.tv
699 #define pmci_cache_way pme_cache.way
700 #define pmci_cache_mc pme_cache.mc
702 #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
703 #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
704 #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
705 #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
706 #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
707 #define pmci_tlb_mc pme_tlb.mc
709 #define pmci_bus_status_info pme_bus.bsi
710 #define pmci_bus_req_address_valid pme_bus.rq
711 #define pmci_bus_resp_address_valid pme_bus.rp
712 #define pmci_bus_target_address_valid pme_bus.tv
713 #define pmci_bus_error_severity pme_bus.sev
714 #define pmci_bus_transaction_type pme_bus.type
715 #define pmci_bus_cache_cache_transfer pme_bus.cc
716 #define pmci_bus_transaction_size pme_bus.size
717 #define pmci_bus_internal_error pme_bus.ib
718 #define pmci_bus_external_error pme_bus.eb
719 #define pmci_bus_mc pme_bus.mc
721 /*
722 * NOTE: this min_state_save area struct only includes the 1KB
723 * architectural state save area. The other 3 KB is scratch space
724 * for PAL.
725 */
727 typedef struct pal_min_state_area_s {
728 u64 pmsa_nat_bits; /* nat bits for saved GRs */
729 u64 pmsa_gr[15]; /* GR1 - GR15 */
730 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
731 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
732 u64 pmsa_pr; /* predicate registers */
733 u64 pmsa_br0; /* branch register 0 */
734 u64 pmsa_rsc; /* ar.rsc */
735 u64 pmsa_iip; /* cr.iip */
736 u64 pmsa_ipsr; /* cr.ipsr */
737 u64 pmsa_ifs; /* cr.ifs */
738 u64 pmsa_xip; /* previous iip */
739 u64 pmsa_xpsr; /* previous psr */
740 u64 pmsa_xfs; /* previous ifs */
741 u64 pmsa_br1; /* branch register 1 */
742 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
743 } pal_min_state_area_t;
746 struct ia64_pal_retval {
747 /*
748 * A zero status value indicates call completed without error.
749 * A negative status value indicates reason of call failure.
750 * A positive status value indicates success but an
751 * informational value should be printed (e.g., "reboot for
752 * change to take effect").
753 */
754 s64 status;
755 u64 v0;
756 u64 v1;
757 u64 v2;
758 };
760 /*
761 * Note: Currently unused PAL arguments are generally labeled
762 * "reserved" so the value specified in the PAL documentation
763 * (generally 0) MUST be passed. Reserved parameters are not optional
764 * parameters.
765 */
766 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
767 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
768 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
769 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
770 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
771 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
773 #define PAL_CALL(iprv,a0,a1,a2,a3) do { \
774 struct ia64_fpreg fr[6]; \
775 ia64_save_scratch_fpregs(fr); \
776 iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
777 ia64_load_scratch_fpregs(fr); \
778 } while (0)
780 #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do { \
781 struct ia64_fpreg fr[6]; \
782 ia64_save_scratch_fpregs(fr); \
783 iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
784 ia64_load_scratch_fpregs(fr); \
785 } while (0)
787 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
788 struct ia64_fpreg fr[6]; \
789 ia64_save_scratch_fpregs(fr); \
790 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
791 ia64_load_scratch_fpregs(fr); \
792 } while (0)
794 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
795 struct ia64_fpreg fr[6]; \
796 ia64_save_scratch_fpregs(fr); \
797 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
798 ia64_load_scratch_fpregs(fr); \
799 } while (0)
801 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
802 struct ia64_fpreg fr[6]; \
803 ia64_save_scratch_fpregs(fr); \
804 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
805 ia64_load_scratch_fpregs(fr); \
806 } while (0)
808 typedef int (*ia64_pal_handler) (u64, ...);
809 extern ia64_pal_handler ia64_pal;
810 extern void ia64_pal_handler_init (void *);
812 extern ia64_pal_handler ia64_pal;
814 extern pal_cache_config_info_t l0d_cache_config_info;
815 extern pal_cache_config_info_t l0i_cache_config_info;
816 extern pal_cache_config_info_t l1_cache_config_info;
817 extern pal_cache_config_info_t l2_cache_config_info;
819 extern pal_cache_protection_info_t l0d_cache_protection_info;
820 extern pal_cache_protection_info_t l0i_cache_protection_info;
821 extern pal_cache_protection_info_t l1_cache_protection_info;
822 extern pal_cache_protection_info_t l2_cache_protection_info;
824 extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
825 pal_cache_type_t);
827 extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
828 pal_cache_type_t);
831 extern void pal_error(int);
834 /* Useful wrappers for the current list of pal procedures */
836 typedef union pal_bus_features_u {
837 u64 pal_bus_features_val;
838 struct {
839 u64 pbf_reserved1 : 29;
840 u64 pbf_req_bus_parking : 1;
841 u64 pbf_bus_lock_mask : 1;
842 u64 pbf_enable_half_xfer_rate : 1;
843 u64 pbf_reserved2 : 22;
844 u64 pbf_disable_xaction_queueing : 1;
845 u64 pbf_disable_resp_err_check : 1;
846 u64 pbf_disable_berr_check : 1;
847 u64 pbf_disable_bus_req_internal_err_signal : 1;
848 u64 pbf_disable_bus_req_berr_signal : 1;
849 u64 pbf_disable_bus_init_event_check : 1;
850 u64 pbf_disable_bus_init_event_signal : 1;
851 u64 pbf_disable_bus_addr_err_check : 1;
852 u64 pbf_disable_bus_addr_err_signal : 1;
853 u64 pbf_disable_bus_data_err_check : 1;
854 } pal_bus_features_s;
855 } pal_bus_features_u_t;
857 extern void pal_bus_features_print (u64);
859 /* Provide information about configurable processor bus features */
860 static inline s64
861 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
862 pal_bus_features_u_t *features_status,
863 pal_bus_features_u_t *features_control)
864 {
865 struct ia64_pal_retval iprv;
866 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
867 if (features_avail)
868 features_avail->pal_bus_features_val = iprv.v0;
869 if (features_status)
870 features_status->pal_bus_features_val = iprv.v1;
871 if (features_control)
872 features_control->pal_bus_features_val = iprv.v2;
873 return iprv.status;
874 }
876 /* Enables/disables specific processor bus features */
877 static inline s64
878 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
879 {
880 struct ia64_pal_retval iprv;
881 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
882 return iprv.status;
883 }
885 /* Get detailed cache information */
886 static inline s64
887 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
888 {
889 struct ia64_pal_retval iprv;
891 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
893 if (iprv.status == 0) {
894 conf->pcci_status = iprv.status;
895 conf->pcci_info_1.pcci1_data = iprv.v0;
896 conf->pcci_info_2.pcci2_data = iprv.v1;
897 conf->pcci_reserved = iprv.v2;
898 }
899 return iprv.status;
901 }
903 /* Get detailed cche protection information */
904 static inline s64
905 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
906 {
907 struct ia64_pal_retval iprv;
909 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
911 if (iprv.status == 0) {
912 prot->pcpi_status = iprv.status;
913 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
914 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
915 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
916 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
917 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
918 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
919 }
920 return iprv.status;
921 }
923 /*
924 * Flush the processor instruction or data caches. *PROGRESS must be
925 * initialized to zero before calling this for the first time..
926 */
927 static inline s64
928 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
929 {
930 struct ia64_pal_retval iprv;
931 #ifdef XEN /* fix a bug in Linux... PAL has changed */
932 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
933 #else
934 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
935 #endif
936 if (vector)
937 *vector = iprv.v0;
938 *progress = iprv.v1;
939 return iprv.status;
940 }
943 /* Initialize the processor controlled caches */
944 static inline s64
945 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
946 {
947 struct ia64_pal_retval iprv;
948 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
949 return iprv.status;
950 }
952 /* Initialize the tags and data of a data or unified cache line of
953 * processor controlled cache to known values without the availability
954 * of backing memory.
955 */
956 static inline s64
957 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
958 {
959 struct ia64_pal_retval iprv;
960 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
961 return iprv.status;
962 }
965 /* Read the data and tag of a processor controlled cache line for diags */
966 static inline s64
967 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
968 {
969 struct ia64_pal_retval iprv;
970 PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
971 return iprv.status;
972 }
974 /* Return summary information about the heirarchy of caches controlled by the processor */
975 static inline s64
976 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
977 {
978 struct ia64_pal_retval iprv;
979 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
980 if (cache_levels)
981 *cache_levels = iprv.v0;
982 if (unique_caches)
983 *unique_caches = iprv.v1;
984 return iprv.status;
985 }
987 /* Write the data and tag of a processor-controlled cache line for diags */
988 static inline s64
989 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
990 {
991 struct ia64_pal_retval iprv;
992 PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
993 return iprv.status;
994 }
997 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
998 static inline s64
999 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1000 u64 *buffer_size, u64 *buffer_align)
1002 struct ia64_pal_retval iprv;
1003 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1004 if (buffer_size)
1005 *buffer_size = iprv.v0;
1006 if (buffer_align)
1007 *buffer_align = iprv.v1;
1008 return iprv.status;
1011 /* Copy relocatable PAL procedures from ROM to memory */
1012 static inline s64
1013 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1015 struct ia64_pal_retval iprv;
1016 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1017 if (pal_proc_offset)
1018 *pal_proc_offset = iprv.v0;
1019 return iprv.status;
1022 /* Return the number of instruction and data debug register pairs */
1023 static inline s64
1024 ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1026 struct ia64_pal_retval iprv;
1027 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1028 if (inst_regs)
1029 *inst_regs = iprv.v0;
1030 if (data_regs)
1031 *data_regs = iprv.v1;
1033 return iprv.status;
1036 #ifdef TBD
1037 /* Switch from IA64-system environment to IA-32 system environment */
1038 static inline s64
1039 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1041 struct ia64_pal_retval iprv;
1042 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1043 return iprv.status;
1045 #endif
1047 /* Get unique geographical address of this processor on its bus */
1048 static inline s64
1049 ia64_pal_fixed_addr (u64 *global_unique_addr)
1051 struct ia64_pal_retval iprv;
1052 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1053 if (global_unique_addr)
1054 *global_unique_addr = iprv.v0;
1055 return iprv.status;
1058 /* Get base frequency of the platform if generated by the processor */
1059 static inline s64
1060 ia64_pal_freq_base (u64 *platform_base_freq)
1062 struct ia64_pal_retval iprv;
1063 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1064 if (platform_base_freq)
1065 *platform_base_freq = iprv.v0;
1066 return iprv.status;
1069 /*
1070 * Get the ratios for processor frequency, bus frequency and interval timer to
1071 * to base frequency of the platform
1072 */
1073 static inline s64
1074 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1075 struct pal_freq_ratio *itc_ratio)
1077 struct ia64_pal_retval iprv;
1078 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1079 if (proc_ratio)
1080 *(u64 *)proc_ratio = iprv.v0;
1081 if (bus_ratio)
1082 *(u64 *)bus_ratio = iprv.v1;
1083 if (itc_ratio)
1084 *(u64 *)itc_ratio = iprv.v2;
1085 return iprv.status;
1088 /* Make the processor enter HALT or one of the implementation dependent low
1089 * power states where prefetching and execution are suspended and cache and
1090 * TLB coherency is not maintained.
1091 */
1092 static inline s64
1093 ia64_pal_halt (u64 halt_state)
1095 struct ia64_pal_retval iprv;
1096 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1097 return iprv.status;
1100 typedef union pal_power_mgmt_info_u {
1101 u64 ppmi_data;
1102 struct {
1103 u64 exit_latency : 16,
1104 entry_latency : 16,
1105 power_consumption : 28,
1106 im : 1,
1107 co : 1,
1108 reserved : 2;
1109 } pal_power_mgmt_info_s;
1110 } pal_power_mgmt_info_u_t;
1112 /* Return information about processor's optional power management capabilities. */
1113 static inline s64
1114 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1116 struct ia64_pal_retval iprv;
1117 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1118 return iprv.status;
1121 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1122 * suspended, but cache and TLB coherency is maintained.
1123 */
1124 static inline s64
1125 ia64_pal_halt_light (void)
1127 struct ia64_pal_retval iprv;
1128 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1129 return iprv.status;
1132 /* Clear all the processor error logging registers and reset the indicator that allows
1133 * the error logging registers to be written. This procedure also checks the pending
1134 * machine check bit and pending INIT bit and reports their states.
1135 */
1136 static inline s64
1137 ia64_pal_mc_clear_log (u64 *pending_vector)
1139 struct ia64_pal_retval iprv;
1140 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1141 if (pending_vector)
1142 *pending_vector = iprv.v0;
1143 return iprv.status;
1146 /* Ensure that all outstanding transactions in a processor are completed or that any
1147 * MCA due to thes outstanding transaction is taken.
1148 */
1149 static inline s64
1150 ia64_pal_mc_drain (void)
1152 struct ia64_pal_retval iprv;
1153 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1154 return iprv.status;
1157 /* Return the machine check dynamic processor state */
1158 static inline s64
1159 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1161 struct ia64_pal_retval iprv;
1162 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1163 if (size)
1164 *size = iprv.v0;
1165 if (pds)
1166 *pds = iprv.v1;
1167 return iprv.status;
1170 /* Return processor machine check information */
1171 static inline s64
1172 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1174 struct ia64_pal_retval iprv;
1175 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1176 if (size)
1177 *size = iprv.v0;
1178 if (error_info)
1179 *error_info = iprv.v1;
1180 return iprv.status;
1183 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1184 * attempt to correct any expected machine checks.
1185 */
1186 static inline s64
1187 ia64_pal_mc_expected (u64 expected, u64 *previous)
1189 struct ia64_pal_retval iprv;
1190 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1191 if (previous)
1192 *previous = iprv.v0;
1193 return iprv.status;
1196 /* Register a platform dependent location with PAL to which it can save
1197 * minimal processor state in the event of a machine check or initialization
1198 * event.
1199 */
1200 static inline s64
1201 ia64_pal_mc_register_mem (u64 physical_addr)
1203 struct ia64_pal_retval iprv;
1204 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1205 return iprv.status;
1208 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1209 * and resume execution
1210 */
1211 static inline s64
1212 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1214 struct ia64_pal_retval iprv;
1215 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1216 return iprv.status;
1219 /* Return the memory attributes implemented by the processor */
1220 static inline s64
1221 ia64_pal_mem_attrib (u64 *mem_attrib)
1223 struct ia64_pal_retval iprv;
1224 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1225 if (mem_attrib)
1226 *mem_attrib = iprv.v0 & 0xff;
1227 return iprv.status;
1230 /* Return the amount of memory needed for second phase of processor
1231 * self-test and the required alignment of memory.
1232 */
1233 static inline s64
1234 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1236 struct ia64_pal_retval iprv;
1237 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1238 if (bytes_needed)
1239 *bytes_needed = iprv.v0;
1240 if (alignment)
1241 *alignment = iprv.v1;
1242 return iprv.status;
1245 typedef union pal_perf_mon_info_u {
1246 u64 ppmi_data;
1247 struct {
1248 u64 generic : 8,
1249 width : 8,
1250 cycles : 8,
1251 retired : 8,
1252 reserved : 32;
1253 } pal_perf_mon_info_s;
1254 } pal_perf_mon_info_u_t;
1256 /* Return the performance monitor information about what can be counted
1257 * and how to configure the monitors to count the desired events.
1258 */
1259 static inline s64
1260 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1262 struct ia64_pal_retval iprv;
1263 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1264 if (pm_info)
1265 pm_info->ppmi_data = iprv.v0;
1266 return iprv.status;
1269 /* Specifies the physical address of the processor interrupt block
1270 * and I/O port space.
1271 */
1272 static inline s64
1273 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1275 struct ia64_pal_retval iprv;
1276 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1277 return iprv.status;
1280 /* Set the SAL PMI entrypoint in memory */
1281 static inline s64
1282 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1284 struct ia64_pal_retval iprv;
1285 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1286 return iprv.status;
1289 struct pal_features_s;
1290 /* Provide information about configurable processor features */
1291 static inline s64
1292 ia64_pal_proc_get_features (u64 *features_avail,
1293 u64 *features_status,
1294 u64 *features_control)
1296 struct ia64_pal_retval iprv;
1297 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1298 if (iprv.status == 0) {
1299 *features_avail = iprv.v0;
1300 *features_status = iprv.v1;
1301 *features_control = iprv.v2;
1303 return iprv.status;
1306 /* Enable/disable processor dependent features */
1307 static inline s64
1308 ia64_pal_proc_set_features (u64 feature_select)
1310 struct ia64_pal_retval iprv;
1311 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1312 return iprv.status;
1315 /*
1316 * Put everything in a struct so we avoid the global offset table whenever
1317 * possible.
1318 */
1319 typedef struct ia64_ptce_info_s {
1320 u64 base;
1321 u32 count[2];
1322 u32 stride[2];
1323 } ia64_ptce_info_t;
1325 /* Return the information required for the architected loop used to purge
1326 * (initialize) the entire TC
1327 */
1328 static inline s64
1329 ia64_get_ptce (ia64_ptce_info_t *ptce)
1331 struct ia64_pal_retval iprv;
1333 if (!ptce)
1334 return -1;
1336 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1337 if (iprv.status == 0) {
1338 ptce->base = iprv.v0;
1339 ptce->count[0] = iprv.v1 >> 32;
1340 ptce->count[1] = iprv.v1 & 0xffffffff;
1341 ptce->stride[0] = iprv.v2 >> 32;
1342 ptce->stride[1] = iprv.v2 & 0xffffffff;
1344 return iprv.status;
1347 /* Return info about implemented application and control registers. */
1348 static inline s64
1349 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1351 struct ia64_pal_retval iprv;
1352 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1353 if (reg_info_1)
1354 *reg_info_1 = iprv.v0;
1355 if (reg_info_2)
1356 *reg_info_2 = iprv.v1;
1357 return iprv.status;
1360 typedef union pal_hints_u {
1361 u64 ph_data;
1362 struct {
1363 u64 si : 1,
1364 li : 1,
1365 reserved : 62;
1366 } pal_hints_s;
1367 } pal_hints_u_t;
1369 /* Return information about the register stack and RSE for this processor
1370 * implementation.
1371 */
1372 static inline s64
1373 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1375 struct ia64_pal_retval iprv;
1376 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1377 if (num_phys_stacked)
1378 *num_phys_stacked = iprv.v0;
1379 if (hints)
1380 hints->ph_data = iprv.v1;
1381 return iprv.status;
1384 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1385 * suspended, but cause cache and TLB coherency to be maintained.
1386 * This is usually called in IA-32 mode.
1387 */
1388 static inline s64
1389 ia64_pal_shutdown (void)
1391 struct ia64_pal_retval iprv;
1392 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1393 return iprv.status;
1396 /* Perform the second phase of processor self-test. */
1397 static inline s64
1398 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1400 struct ia64_pal_retval iprv;
1401 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1402 if (self_test_state)
1403 *self_test_state = iprv.v0;
1404 return iprv.status;
1407 typedef union pal_version_u {
1408 u64 pal_version_val;
1409 struct {
1410 u64 pv_pal_b_rev : 8;
1411 u64 pv_pal_b_model : 8;
1412 u64 pv_reserved1 : 8;
1413 u64 pv_pal_vendor : 8;
1414 u64 pv_pal_a_rev : 8;
1415 u64 pv_pal_a_model : 8;
1416 u64 pv_reserved2 : 16;
1417 } pal_version_s;
1418 } pal_version_u_t;
1421 /* Return PAL version information */
1422 static inline s64
1423 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1425 struct ia64_pal_retval iprv;
1426 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1427 if (pal_min_version)
1428 pal_min_version->pal_version_val = iprv.v0;
1430 if (pal_cur_version)
1431 pal_cur_version->pal_version_val = iprv.v1;
1433 return iprv.status;
1436 typedef union pal_tc_info_u {
1437 u64 pti_val;
1438 struct {
1439 u64 num_sets : 8,
1440 associativity : 8,
1441 num_entries : 16,
1442 pf : 1,
1443 unified : 1,
1444 reduce_tr : 1,
1445 reserved : 29;
1446 } pal_tc_info_s;
1447 } pal_tc_info_u_t;
1449 #define tc_reduce_tr pal_tc_info_s.reduce_tr
1450 #define tc_unified pal_tc_info_s.unified
1451 #define tc_pf pal_tc_info_s.pf
1452 #define tc_num_entries pal_tc_info_s.num_entries
1453 #define tc_associativity pal_tc_info_s.associativity
1454 #define tc_num_sets pal_tc_info_s.num_sets
1457 /* Return information about the virtual memory characteristics of the processor
1458 * implementation.
1459 */
1460 static inline s64
1461 ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1463 struct ia64_pal_retval iprv;
1464 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1465 if (tc_info)
1466 tc_info->pti_val = iprv.v0;
1467 if (tc_pages)
1468 *tc_pages = iprv.v1;
1469 return iprv.status;
1472 /* Get page size information about the virtual memory characteristics of the processor
1473 * implementation.
1474 */
1475 static inline s64
1476 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1478 struct ia64_pal_retval iprv;
1479 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1480 if (tr_pages)
1481 *tr_pages = iprv.v0;
1482 if (vw_pages)
1483 *vw_pages = iprv.v1;
1484 return iprv.status;
1487 typedef union pal_vm_info_1_u {
1488 u64 pvi1_val;
1489 struct {
1490 u64 vw : 1,
1491 phys_add_size : 7,
1492 key_size : 8,
1493 max_pkr : 8,
1494 hash_tag_id : 8,
1495 max_dtr_entry : 8,
1496 max_itr_entry : 8,
1497 max_unique_tcs : 8,
1498 num_tc_levels : 8;
1499 } pal_vm_info_1_s;
1500 } pal_vm_info_1_u_t;
1502 typedef union pal_vm_info_2_u {
1503 u64 pvi2_val;
1504 struct {
1505 u64 impl_va_msb : 8,
1506 rid_size : 8,
1507 reserved : 48;
1508 } pal_vm_info_2_s;
1509 } pal_vm_info_2_u_t;
1511 /* Get summary information about the virtual memory characteristics of the processor
1512 * implementation.
1513 */
1514 static inline s64
1515 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1517 struct ia64_pal_retval iprv;
1518 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1519 if (vm_info_1)
1520 vm_info_1->pvi1_val = iprv.v0;
1521 if (vm_info_2)
1522 vm_info_2->pvi2_val = iprv.v1;
1523 return iprv.status;
1526 typedef union pal_itr_valid_u {
1527 u64 piv_val;
1528 struct {
1529 u64 access_rights_valid : 1,
1530 priv_level_valid : 1,
1531 dirty_bit_valid : 1,
1532 mem_attr_valid : 1,
1533 reserved : 60;
1534 } pal_tr_valid_s;
1535 } pal_tr_valid_u_t;
1537 /* Read a translation register */
1538 static inline s64
1539 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1541 struct ia64_pal_retval iprv;
1542 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1543 if (tr_valid)
1544 tr_valid->piv_val = iprv.v0;
1545 return iprv.status;
1548 /*
1549 * PAL_PREFETCH_VISIBILITY transaction types
1550 */
1551 #define PAL_VISIBILITY_VIRTUAL 0
1552 #define PAL_VISIBILITY_PHYSICAL 1
1554 /*
1555 * PAL_PREFETCH_VISIBILITY return codes
1556 */
1557 #define PAL_VISIBILITY_OK 1
1558 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1559 #define PAL_VISIBILITY_INVAL_ARG -2
1560 #define PAL_VISIBILITY_ERROR -3
1562 static inline s64
1563 ia64_pal_prefetch_visibility (s64 trans_type)
1565 struct ia64_pal_retval iprv;
1566 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1567 return iprv.status;
1570 /* data structure for getting information on logical to physical mappings */
1571 typedef union pal_log_overview_u {
1572 struct {
1573 u64 num_log :16, /* Total number of logical
1574 * processors on this die
1575 */
1576 tpc :8, /* Threads per core */
1577 reserved3 :8, /* Reserved */
1578 cpp :8, /* Cores per processor */
1579 reserved2 :8, /* Reserved */
1580 ppid :8, /* Physical processor ID */
1581 reserved1 :8; /* Reserved */
1582 } overview_bits;
1583 u64 overview_data;
1584 } pal_log_overview_t;
1586 typedef union pal_proc_n_log_info1_u{
1587 struct {
1588 u64 tid :16, /* Thread id */
1589 reserved2 :16, /* Reserved */
1590 cid :16, /* Core id */
1591 reserved1 :16; /* Reserved */
1592 } ppli1_bits;
1593 u64 ppli1_data;
1594 } pal_proc_n_log_info1_t;
1596 typedef union pal_proc_n_log_info2_u {
1597 struct {
1598 u64 la :16, /* Logical address */
1599 reserved :48; /* Reserved */
1600 } ppli2_bits;
1601 u64 ppli2_data;
1602 } pal_proc_n_log_info2_t;
1604 typedef struct pal_logical_to_physical_s
1606 pal_log_overview_t overview;
1607 pal_proc_n_log_info1_t ppli1;
1608 pal_proc_n_log_info2_t ppli2;
1609 } pal_logical_to_physical_t;
1611 #define overview_num_log overview.overview_bits.num_log
1612 #define overview_tpc overview.overview_bits.tpc
1613 #define overview_cpp overview.overview_bits.cpp
1614 #define overview_ppid overview.overview_bits.ppid
1615 #define log1_tid ppli1.ppli1_bits.tid
1616 #define log1_cid ppli1.ppli1_bits.cid
1617 #define log2_la ppli2.ppli2_bits.la
1619 /* Get information on logical to physical processor mappings. */
1620 static inline s64
1621 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1623 struct ia64_pal_retval iprv;
1625 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1627 if (iprv.status == PAL_STATUS_SUCCESS)
1629 if (proc_number == 0)
1630 mapping->overview.overview_data = iprv.v0;
1631 mapping->ppli1.ppli1_data = iprv.v1;
1632 mapping->ppli2.ppli2_data = iprv.v2;
1635 return iprv.status;
1637 #ifdef XEN
1638 #include <asm/vmx_pal.h>
1639 #endif
1640 #endif /* __ASSEMBLY__ */
1642 #endif /* _ASM_IA64_PAL_H */