ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/pgtable.h @ 10876:27ccf13dc3b7

[IA64] boot windows server 2003: support 8k guest pagesize

Make HASH VTLB support 8K page size which is used by windows

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
[whitespace and masking cleanups]
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild.aw
date Tue Aug 01 14:44:04 2006 -0600 (2006-08-01)
parents 86e5d8458c08
children 5727c3c4070e
line source
1 #ifndef _ASM_IA64_PGTABLE_H
2 #define _ASM_IA64_PGTABLE_H
4 /*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h>.
10 *
11 * Copyright (C) 1998-2005 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 */
15 #include <linux/config.h>
17 #include <asm/mman.h>
18 #include <asm/page.h>
19 #include <asm/processor.h>
20 #include <asm/system.h>
21 #include <asm/types.h>
22 #ifdef XEN
23 #ifndef __ASSEMBLY__
24 #include <xen/sched.h> /* needed for mm_struct (via asm/domain.h) */
25 #endif
26 #endif
28 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
30 /*
31 * First, define the various bits in a PTE. Note that the PTE format
32 * matches the VHPT short format, the firt doubleword of the VHPD long
33 * format, and the first doubleword of the TLB insertion format.
34 */
35 #define _PAGE_P_BIT 0
36 #define _PAGE_A_BIT 5
37 #define _PAGE_D_BIT 6
39 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
40 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
41 #ifdef XEN
42 #define _PAGE_MA_ST (0x1 << 2) /* is reserved for software use */
43 #endif
44 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
45 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
46 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
47 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
48 #define _PAGE_MA_MASK (0x7 << 2)
49 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
50 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
51 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
52 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
53 #define _PAGE_PL_MASK (3 << 7)
54 #define _PAGE_AR_R (0 << 9) /* read only */
55 #define _PAGE_AR_RX (1 << 9) /* read & execute */
56 #define _PAGE_AR_RW (2 << 9) /* read & write */
57 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
58 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
59 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
60 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
61 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
62 #define _PAGE_AR_MASK (7 << 9)
63 #define _PAGE_AR_SHIFT 9
64 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
65 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
66 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
67 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
68 #ifdef XEN
69 #define _PAGE_VIRT_D (__IA64_UL(1) << 53) /* Virtual dirty bit */
70 #define _PAGE_PROTNONE 0
71 #else
72 #define _PAGE_PROTNONE (__IA64_UL(1) << 63)
73 #endif
75 /* Valid only for a PTE with the present bit cleared: */
76 #define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
78 #define _PFN_MASK _PAGE_PPN_MASK
79 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
80 #define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
82 #define _PAGE_SIZE_4K 12
83 #define _PAGE_SIZE_8K 13
84 #define _PAGE_SIZE_16K 14
85 #define _PAGE_SIZE_64K 16
86 #define _PAGE_SIZE_256K 18
87 #define _PAGE_SIZE_1M 20
88 #define _PAGE_SIZE_4M 22
89 #define _PAGE_SIZE_16M 24
90 #define _PAGE_SIZE_64M 26
91 #define _PAGE_SIZE_256M 28
92 #define _PAGE_SIZE_1G 30
93 #define _PAGE_SIZE_4G 32
95 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
96 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
97 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
99 /*
100 * Definitions for first level:
101 *
102 * PGDIR_SHIFT determines what a first-level page table entry can map.
103 */
104 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
105 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
106 #define PGDIR_MASK (~(PGDIR_SIZE-1))
107 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
108 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
109 #define FIRST_USER_ADDRESS 0
111 /*
112 * Definitions for second level:
113 *
114 * PMD_SHIFT determines the size of the area a second-level page table
115 * can map.
116 */
117 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
118 #define PMD_SIZE (1UL << PMD_SHIFT)
119 #define PMD_MASK (~(PMD_SIZE-1))
120 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
122 /*
123 * Definitions for third level:
124 */
125 #define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
127 /*
128 * All the normal masks have the "page accessed" bits on, as any time
129 * they are used, the page is accessed. They are cleared only by the
130 * page-out routines.
131 */
132 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
133 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
134 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
135 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
136 #define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
137 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
138 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
139 #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
141 # ifndef __ASSEMBLY__
143 #include <asm/bitops.h>
144 #include <asm/cacheflush.h>
145 #include <asm/mmu_context.h>
146 #include <asm/processor.h>
148 /*
149 * Next come the mappings that determine how mmap() protection bits
150 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
151 * _P version gets used for a private shared memory segment, the _S
152 * version gets used for a shared memory segment with MAP_SHARED on.
153 * In a private shared memory segment, we do a copy-on-write if a task
154 * attempts to write to the page.
155 */
156 /* xwr */
157 #define __P000 PAGE_NONE
158 #define __P001 PAGE_READONLY
159 #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
160 #define __P011 PAGE_READONLY /* ditto */
161 #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
162 #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
163 #define __P110 PAGE_COPY_EXEC
164 #define __P111 PAGE_COPY_EXEC
166 #define __S000 PAGE_NONE
167 #define __S001 PAGE_READONLY
168 #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
169 #define __S011 PAGE_SHARED
170 #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
171 #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
172 #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
173 #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
175 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
176 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
177 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
180 /*
181 * Some definitions to translate between mem_map, PTEs, and page addresses:
182 */
185 /* Quick test to see if ADDR is a (potentially) valid physical address. */
186 static inline long
187 ia64_phys_addr_valid (unsigned long addr)
188 {
189 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
190 }
192 /*
193 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
194 * memory. For the return value to be meaningful, ADDR must be >=
195 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
196 * require a hash-, or multi-level tree-lookup or something of that
197 * sort) but it guarantees to return TRUE only if accessing the page
198 * at that address does not cause an error. Note that there may be
199 * addresses for which kern_addr_valid() returns FALSE even though an
200 * access would not cause an error (e.g., this is typically true for
201 * memory mapped I/O regions.
202 *
203 * XXX Need to implement this for IA-64.
204 */
205 #define kern_addr_valid(addr) (1)
208 /*
209 * Now come the defines and routines to manage and access the three-level
210 * page table.
211 */
213 /*
214 * On some architectures, special things need to be done when setting
215 * the PTE in a page table. Nothing special needs to be on IA-64.
216 */
217 #define set_pte(ptep, pteval) (*(ptep) = (pteval))
218 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
219 #ifdef XEN
220 static inline void
221 set_pte_rel(volatile pte_t* ptep, pte_t pteval)
222 {
223 #if CONFIG_SMP
224 asm volatile ("st8.rel [%0]=%1" ::
225 "r"(&pte_val(*ptep)), "r"(pte_val(pteval)) :
226 "memory");
227 #else
228 set_pte(ptep, pteval);
229 #endif
230 }
231 #endif
233 #define RGN_SIZE (1UL << 61)
234 #define RGN_KERNEL 7
236 #define VMALLOC_START 0xa000000200000000UL
237 #ifdef CONFIG_VIRTUAL_MEM_MAP
238 # define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
239 # define VMALLOC_END vmalloc_end
240 extern unsigned long vmalloc_end;
241 #else
242 # define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
243 #endif
245 /* fs/proc/kcore.c */
246 #define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL)
247 #define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL)
249 /*
250 * Conversion functions: convert page frame number (pfn) and a protection value to a page
251 * table entry (pte).
252 */
253 #define pfn_pte(pfn, pgprot) \
254 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
256 /* Extract pfn from pte. */
257 #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
259 #define mk_pte(page, pgprot) pfn_pte(page_to_mfn(page), (pgprot))
261 /* This takes a physical page address that is used by the remapping functions */
262 #define mk_pte_phys(physpage, pgprot) \
263 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
265 #define pte_modify(_pte, newprot) \
266 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
268 #define page_pte_prot(page,prot) mk_pte(page, prot)
269 #define page_pte(page) page_pte_prot(page, __pgprot(0))
271 #define pte_none(pte) (!pte_val(pte))
272 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
273 #define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
274 /* pte_page() returns the "struct page *" corresponding to the PTE: */
275 #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
277 #define pmd_none(pmd) (!pmd_val(pmd))
278 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
279 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
280 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
281 #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
282 #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
284 #define pud_none(pud) (!pud_val(pud))
285 #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
286 #define pud_present(pud) (pud_val(pud) != 0UL)
287 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
289 #define pud_page(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
291 /*
292 * The following have defined behavior only work if pte_present() is true.
293 */
294 #define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3)
295 #define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
296 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
297 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
298 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
299 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
300 #define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
301 #ifdef XEN
302 #define pte_mem(pte) \
303 (!(pte_val(pte) & (GPFN_IO_MASK | GPFN_INV_MASK)) && !pte_none(pte))
304 #endif
305 /*
306 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
307 * access rights:
308 */
309 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
310 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
311 #define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX))
312 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
313 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
314 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
315 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
316 #define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_P))
318 /*
319 * Macro to a page protection value as "uncacheable". Note that "protection" is really a
320 * misnomer here as the protection value contains the memory attribute bits, dirty bits,
321 * and various other bits as well.
322 */
323 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
325 /*
326 * Macro to make mark a page protection value as "write-combining".
327 * Note that "protection" is really a misnomer here as the protection
328 * value contains the memory attribute bits, dirty bits, and various
329 * other bits as well. Accesses through a write-combining translation
330 * works bypasses the caches, but does allow for consecutive writes to
331 * be combined into single (but larger) write transactions.
332 */
333 #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
335 static inline unsigned long
336 pgd_index (unsigned long address)
337 {
338 unsigned long region = address >> 61;
339 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
341 return (region << (PAGE_SHIFT - 6)) | l1index;
342 }
344 /* The offset in the 1-level directory is given by the 3 region bits
345 (61..63) and the level-1 bits. */
346 static inline pgd_t*
347 pgd_offset (struct mm_struct *mm, unsigned long address)
348 {
349 return mm->pgd + pgd_index(address);
350 }
352 /* In the kernel's mapped region we completely ignore the region number
353 (since we know it's in region number 5). */
354 #define pgd_offset_k(addr) \
355 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
357 /* Look up a pgd entry in the gate area. On IA-64, the gate-area
358 resides in the kernel-mapped segment, hence we use pgd_offset_k()
359 here. */
360 #define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
362 /* Find an entry in the second-level page table.. */
363 #define pmd_offset(dir,addr) \
364 ((pmd_t *) pud_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
366 /*
367 * Find an entry in the third-level page table. This looks more complicated than it
368 * should be because some platforms place page tables in high memory.
369 */
370 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
371 #define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
372 #define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
373 #define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
374 #define pte_unmap(pte) do { } while (0)
375 #define pte_unmap_nested(pte) do { } while (0)
377 #ifndef XEN
378 /* atomic versions of the some PTE manipulations: */
380 static inline int
381 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
382 {
383 #ifdef CONFIG_SMP
384 if (!pte_young(*ptep))
385 return 0;
386 return test_and_clear_bit(_PAGE_A_BIT, ptep);
387 #else
388 pte_t pte = *ptep;
389 if (!pte_young(pte))
390 return 0;
391 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
392 return 1;
393 #endif
394 }
396 static inline int
397 ptep_test_and_clear_dirty (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
398 {
399 #ifdef CONFIG_SMP
400 if (!pte_dirty(*ptep))
401 return 0;
402 return test_and_clear_bit(_PAGE_D_BIT, ptep);
403 #else
404 pte_t pte = *ptep;
405 if (!pte_dirty(pte))
406 return 0;
407 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
408 return 1;
409 #endif
410 }
411 #endif
413 #ifdef XEN
414 static inline pte_t
415 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
416 volatile pte_t *ptep)
417 #else
418 static inline pte_t
419 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
420 #endif
421 {
422 #ifdef CONFIG_SMP
423 return __pte(xchg((long *) ptep, 0));
424 #else
425 pte_t pte = *ptep;
426 pte_clear(mm, addr, ptep);
427 return pte;
428 #endif
429 }
431 #ifdef XEN
432 static inline pte_t
433 ptep_xchg(struct mm_struct *mm, unsigned long addr,
434 volatile pte_t *ptep, pte_t npte)
435 {
436 #ifdef CONFIG_SMP
437 return __pte(xchg((long *) ptep, pte_val(npte)));
438 #else
439 pte_t pte = *ptep;
440 set_pte (ptep, npte);
441 return pte;
442 #endif
443 }
445 static inline pte_t
446 ptep_cmpxchg_rel(struct mm_struct *mm, unsigned long addr,
447 volatile pte_t *ptep, pte_t old_pte, pte_t new_pte)
448 {
449 #ifdef CONFIG_SMP
450 return __pte(cmpxchg_rel(&pte_val(*ptep),
451 pte_val(old_pte), pte_val(new_pte)));
452 #else
453 pte_t pte = *ptep;
454 if (pte_val(pte) == pte_val(old_pte)) {
455 set_pte(ptep, npte);
456 }
457 return pte;
458 #endif
459 }
460 #endif
462 #ifndef XEN
463 static inline void
464 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
465 {
466 #ifdef CONFIG_SMP
467 unsigned long new, old;
469 do {
470 old = pte_val(*ptep);
471 new = pte_val(pte_wrprotect(__pte (old)));
472 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
473 #else
474 pte_t old_pte = *ptep;
475 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
476 #endif
477 }
479 static inline int
480 pte_same (pte_t a, pte_t b)
481 {
482 return pte_val(a) == pte_val(b);
483 }
485 #define update_mmu_cache(vma, address, pte) do { } while (0)
486 #endif /* XEN */
488 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
489 extern void paging_init (void);
491 /*
492 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
493 * bits in the swap-type field of the swap pte. It would be nice to
494 * enforce that, but we can't easily include <linux/swap.h> here.
495 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
496 *
497 * Format of swap pte:
498 * bit 0 : present bit (must be zero)
499 * bit 1 : _PAGE_FILE (must be zero)
500 * bits 2- 8: swap-type
501 * bits 9-62: swap offset
502 * bit 63 : _PAGE_PROTNONE bit
503 *
504 * Format of file pte:
505 * bit 0 : present bit (must be zero)
506 * bit 1 : _PAGE_FILE (must be one)
507 * bits 2-62: file_offset/PAGE_SIZE
508 * bit 63 : _PAGE_PROTNONE bit
509 */
510 #define __swp_type(entry) (((entry).val >> 2) & 0x7f)
511 #define __swp_offset(entry) (((entry).val << 1) >> 10)
512 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
513 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
514 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
516 #define PTE_FILE_MAX_BITS 61
517 #define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
518 #define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
520 /* XXX is this right? */
521 #define io_remap_page_range(vma, vaddr, paddr, size, prot) \
522 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
524 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
525 remap_pfn_range(vma, vaddr, pfn, size, prot)
527 #define MK_IOSPACE_PFN(space, pfn) (pfn)
528 #define GET_IOSPACE(pfn) 0
529 #define GET_PFN(pfn) (pfn)
531 /*
532 * ZERO_PAGE is a global shared page that is always zero: used
533 * for zero-mapped memory areas etc..
534 */
535 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
536 #ifndef XEN
537 extern struct page *zero_page_memmap_ptr;
538 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
539 #endif
541 /* We provide our own get_unmapped_area to cope with VA holes for userland */
542 #define HAVE_ARCH_UNMAPPED_AREA
544 #ifdef CONFIG_HUGETLB_PAGE
545 #define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
546 #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
547 #define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
548 struct mmu_gather;
549 void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr,
550 unsigned long end, unsigned long floor, unsigned long ceiling);
551 #endif
553 /*
554 * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
555 * information. However, we use this routine to take care of any (delayed) i-cache
556 * flushing that may be necessary.
557 */
558 extern void lazy_mmu_prot_update (pte_t pte);
560 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
561 /*
562 * Update PTEP with ENTRY, which is guaranteed to be a less
563 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
564 * WRITABLE bits turned on, when the value at PTEP did not. The
565 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
566 *
567 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
568 * having to worry about races. On SMP machines, there are only two
569 * cases where this is true:
570 *
571 * (1) *PTEP has the PRESENT bit turned OFF
572 * (2) ENTRY has the DIRTY bit turned ON
573 *
574 * On ia64, we could implement this routine with a cmpxchg()-loop
575 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
576 * However, like on x86, we can get a more streamlined version by
577 * observing that it is OK to drop ACCESSED bit updates when
578 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
579 * result in an extra Access-bit fault, which would then turn on the
580 * ACCESSED bit in the low-level fault handler (iaccess_bit or
581 * daccess_bit in ivt.S).
582 */
583 #ifdef CONFIG_SMP
584 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
585 do { \
586 if (__safely_writable) { \
587 set_pte(__ptep, __entry); \
588 flush_tlb_page(__vma, __addr); \
589 } \
590 } while (0)
591 #else
592 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
593 ptep_establish(__vma, __addr, __ptep, __entry)
594 #endif
596 # ifdef CONFIG_VIRTUAL_MEM_MAP
597 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
598 # define __HAVE_ARCH_MEMMAP_INIT
599 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
600 unsigned long start_pfn);
601 # endif /* CONFIG_VIRTUAL_MEM_MAP */
602 # endif /* !__ASSEMBLY__ */
604 /*
605 * Identity-mapped regions use a large page size. We'll call such large pages
606 * "granules". If you can think of a better name that's unambiguous, let me
607 * know...
608 */
609 #if defined(CONFIG_IA64_GRANULE_64MB)
610 # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
611 #elif defined(CONFIG_IA64_GRANULE_16MB)
612 # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
613 #endif
614 #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
615 /*
616 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
617 */
618 #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
619 #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
621 /*
622 * No page table caches to initialise
623 */
624 #define pgtable_cache_init() do { } while (0)
626 /* These tell get_user_pages() that the first gate page is accessible from user-level. */
627 #define FIXADDR_USER_START GATE_ADDR
628 #ifdef HAVE_BUGGY_SEGREL
629 # define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
630 #else
631 # define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
632 #endif
634 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
635 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
636 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
637 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
638 #define __HAVE_ARCH_PTE_SAME
639 #define __HAVE_ARCH_PGD_OFFSET_GATE
640 #define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
642 #include <asm-generic/pgtable-nopud.h>
643 #include <asm-generic/pgtable.h>
645 #endif /* _ASM_IA64_PGTABLE_H */