ia64/xen-unstable

view tools/firmware/vmxassist/setup.c @ 12773:275a8f9a0710

Remove useless segments push/pop in VMXAssist.
According to Intel Spec, segments registors are cleared when exiting
virtual-8086 mode through trap or interrupts gate, so it's no need to
save their values in stack.
Signed-off-by: Xin Li <xin.b.li@intel.com>
author kfraser@localhost.localdomain
date Mon Dec 04 09:20:12 2006 +0000 (2006-12-04)
parents 45e34f00a78f
children 44319e9dc0c5
line source
1 /*
2 * setup.c: Setup the world for vmxassist.
3 *
4 * Leendert van Doorn, leendert@watson.ibm.com
5 * Copyright (c) 2005, International Business Machines Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 */
20 #include "vm86.h"
21 #include "util.h"
22 #include "machine.h"
24 #if (VMXASSIST_BASE != TEXTADDR)
25 #error VMXAssist base mismatch
26 #endif
28 #define NR_PGD (PGSIZE / sizeof(unsigned))
30 #define min(a, b) ((a) > (b) ? (b) : (a))
32 /* Which CPU are we booting, and what is the initial CS segment? */
33 int booting_cpu, booting_vector;
35 unsigned long long gdt[] __attribute__ ((aligned(32))) = {
36 0x0000000000000000ULL, /* 0x00: reserved */
37 0x0000890000000000ULL, /* 0x08: 32-bit TSS */
38 0x00CF9A000000FFFFULL, /* 0x10: CS 32-bit */
39 0x00CF92000000FFFFULL, /* 0x18: DS 32-bit */
40 };
42 struct dtr gdtr = { sizeof(gdt)-1, (unsigned long) &gdt };
44 struct tss tss __attribute__ ((aligned(4)));
46 unsigned long long idt[NR_TRAPS] __attribute__ ((aligned(32)));
48 struct dtr idtr = { sizeof(idt)-1, (unsigned long) &idt };
50 #ifdef TEST
51 unsigned pgd[NR_PGD] __attribute__ ((aligned(PGSIZE))) = { 0 };
53 struct e820entry e820map[] = {
54 { 0x0000000000000000ULL, 0x000000000009F800ULL, E820_RAM },
55 { 0x000000000009F800ULL, 0x0000000000000800ULL, E820_RESERVED },
56 { 0x00000000000C0000ULL, 0x0000000000040000ULL, E820_RESERVED },
57 { 0x0000000000100000ULL, 0x0000000000000000ULL, E820_RAM },
58 { 0x0000000000000000ULL, 0x0000000000003000ULL, E820_NVS },
59 { 0x0000000000003000ULL, 0x000000000000A000ULL, E820_ACPI },
60 };
61 #endif /* TEST */
63 struct vmx_assist_context oldctx;
64 struct vmx_assist_context newctx;
66 unsigned long memory_size;
67 int initialize_real_mode;
69 extern char stack_top[];
70 extern unsigned trap_handlers[];
72 void
73 banner(void)
74 {
75 printf("VMXAssist (%s)\n", __DATE__);
77 /* Bochs its way to convey memory size */
78 memory_size = ((get_cmos(0x35) << 8) | get_cmos(0x34)) << 6;
79 if (memory_size > 0x3bc000)
80 memory_size = 0x3bc000;
81 memory_size = (memory_size << 10) + 0xF00000;
82 if (memory_size <= 0xF00000)
83 memory_size =
84 (((get_cmos(0x31) << 8) | get_cmos(0x30)) + 0x400) << 10;
85 memory_size += 0x400 << 10; /* + 1MB */
87 #ifdef TEST
88 /* Create an SMAP for our debug environment */
89 e820map[4].size = memory_size - e820map[4].addr - PGSIZE;
90 e820map[5].addr = memory_size - PGSIZE;
91 e820map[6].addr = memory_size;
92 e820map[7].addr += memory_size;
94 *E820_MAP_NR = sizeof(e820map)/sizeof(e820map[0]);
95 memcpy(E820_MAP, e820map, sizeof(e820map));
96 #endif
98 printf("Memory size %ld MB\n", memory_size >> 20);
99 printf("E820 map:\n");
100 print_e820_map(E820_MAP, *E820_MAP_NR);
101 printf("\n");
102 }
104 #ifdef TEST
105 void
106 setup_paging(void)
107 {
108 unsigned long i;
110 if (((unsigned)pgd & ~PGMASK) != 0)
111 panic("PGD not page aligned");
112 set_cr4(get_cr4() | CR4_PSE);
113 for (i = 0; i < NR_PGD; i++)
114 pgd[i] = (i * LPGSIZE)| PTE_PS | PTE_US | PTE_RW | PTE_P;
115 set_cr3((unsigned) pgd);
116 set_cr0(get_cr0() | (CR0_PE|CR0_PG));
117 }
118 #endif /* TEST */
120 void
121 setup_gdt(void)
122 {
123 unsigned long long addr = (unsigned long long) &tss;
125 /* setup task state segment */
126 memset(&tss, 0, sizeof(tss));
127 tss.ss0 = DATA_SELECTOR;
128 tss.esp0 = (unsigned) stack_top - 4*4;
129 tss.iomap_base = offsetof(struct tss, iomap);
131 /* initialize gdt's tss selector */
132 gdt[TSS_SELECTOR / sizeof(gdt[0])] |=
133 ((addr & 0xFF000000) << (56-24)) |
134 ((addr & 0x00FF0000) << (32-16)) |
135 ((addr & 0x0000FFFF) << (16)) |
136 (sizeof(tss) - 1);
138 /* switch to our own gdt and set current tss */
139 __asm__ __volatile__ ("lgdt %0" : : "m" (gdtr));
140 __asm__ __volatile__ ("movl %%eax,%%ds;"
141 "movl %%eax,%%es;"
142 "movl %%eax,%%fs;"
143 "movl %%eax,%%gs;"
144 "movl %%eax,%%ss" : : "a" (DATA_SELECTOR));
146 __asm__ __volatile__ ("ljmp %0,$1f; 1:" : : "i" (CODE_SELECTOR));
148 __asm__ __volatile__ ("ltr %%ax" : : "a" (TSS_SELECTOR));
149 }
151 void
152 set_intr_gate(int i, unsigned handler)
153 {
154 unsigned long long addr = handler;
156 idt[i] = ((addr & 0xFFFF0000ULL) << 32) | (0x8E00ULL << 32) |
157 (addr & 0xFFFFULL) | (CODE_SELECTOR << 16);
158 }
160 void
161 setup_idt(void)
162 {
163 int i;
165 for (i = 0; i < NR_TRAPS; i++)
166 set_intr_gate(i, trap_handlers[i]);
167 __asm__ __volatile__ ("lidt %0" : : "m" (idtr));
168 }
170 void
171 setup_pic(void)
172 {
173 /* mask all interrupts */
174 outb(PIC_MASTER + PIC_IMR, 0xFF);
175 outb(PIC_SLAVE + PIC_IMR, 0xFF);
177 /* setup master PIC */
178 outb(PIC_MASTER + PIC_CMD, 0x11); /* edge triggered, cascade, ICW4 */
179 outb(PIC_MASTER + PIC_IMR, NR_EXCEPTION_HANDLER);
180 outb(PIC_MASTER + PIC_IMR, 1 << 2); /* slave on channel 2 */
181 outb(PIC_MASTER + PIC_IMR, 0x01);
183 /* setup slave PIC */
184 outb(PIC_SLAVE + PIC_CMD, 0x11); /* edge triggered, cascade, ICW4 */
185 outb(PIC_SLAVE + PIC_IMR, NR_EXCEPTION_HANDLER + 8);
186 outb(PIC_SLAVE + PIC_IMR, 0x02); /* slave identity is 2 */
187 outb(PIC_SLAVE + PIC_IMR, 0x01);
189 /* enable all interrupts */
190 outb(PIC_MASTER + PIC_IMR, 0);
191 outb(PIC_SLAVE + PIC_IMR, 0);
192 }
194 void
195 setiomap(int port)
196 {
197 tss.iomap[port >> 3] |= 1 << (port & 7);
198 }
200 void
201 enter_real_mode(struct regs *regs)
202 {
203 /* mask off TSS busy bit */
204 gdt[TSS_SELECTOR / sizeof(gdt[0])] &= ~0x0000020000000000ULL;
206 /* start 8086 emulation of BIOS */
207 if (initialize_real_mode) {
208 initialize_real_mode = 0;
209 regs->eflags |= EFLAGS_VM | 0x02;
210 regs->ves = regs->vds = regs->vfs = regs->vgs = 0xF000;
211 if (booting_cpu == 0) {
212 regs->cs = 0xF000; /* ROM BIOS POST entry point */
213 #ifdef TEST
214 regs->eip = 0xFFE0;
215 #else
216 regs->eip = 0xFFF0;
217 #endif
218 } else {
219 regs->cs = booting_vector << 8; /* AP entry point */
220 regs->eip = 0;
221 }
223 regs->uesp = regs->uss = 0;
224 regs->eax = regs->ecx = regs->edx = regs->ebx = 0;
225 regs->esp = regs->ebp = regs->esi = regs->edi = 0;
227 /* intercept accesses to the PIC */
228 setiomap(PIC_MASTER+PIC_CMD);
229 setiomap(PIC_MASTER+PIC_IMR);
230 setiomap(PIC_SLAVE+PIC_CMD);
231 setiomap(PIC_SLAVE+PIC_IMR);
233 printf("Starting emulated 16-bit real-mode: ip=%04x:%04x\n",
234 regs->cs, regs->eip);
236 mode = VM86_REAL; /* becomes previous mode */
237 set_mode(regs, VM86_REAL);
239 /* this should get us into 16-bit mode */
240 return;
241 }
243 /* go from protected to real mode */
244 regs->eflags |= EFLAGS_VM;
245 set_mode(regs, VM86_PROTECTED_TO_REAL);
246 emulate(regs);
247 }
249 /*
250 * Setup the environment for VMX assist.
251 * This environment consists of flat segments (code and data),
252 * its own gdt, idt, and tr.
253 */
254 void
255 setup_ctx(void)
256 {
257 struct vmx_assist_context *c = &newctx;
259 memset(c, 0, sizeof(*c));
260 c->eip = (unsigned long) switch_to_real_mode;
261 c->esp = (unsigned) stack_top - 4*4;
262 c->eflags = 0x2; /* no interrupts, please */
264 /*
265 * Obviously, vmx assist is not running with CR0_PE disabled.
266 * The reason why the vmx assist cr0 has CR0.PE disabled is
267 * that a transtion to CR0.PE causes a world switch. It seems
268 * more natural to enable CR0.PE to cause a world switch to
269 * protected mode rather than disabling it.
270 */
271 #ifdef TEST
272 c->cr0 = (get_cr0() | CR0_NE | CR0_PG) & ~CR0_PE;
273 c->cr3 = (unsigned long) pgd;
274 #else
275 c->cr0 = (get_cr0() | CR0_NE) & ~CR0_PE;
276 c->cr3 = 0;
277 #endif
278 c->cr4 = get_cr4();
280 c->idtr_limit = sizeof(idt)-1;
281 c->idtr_base = (unsigned long) &idt;
283 c->gdtr_limit = sizeof(gdt)-1;
284 c->gdtr_base = (unsigned long) &gdt;
286 c->cs_sel = CODE_SELECTOR;
287 c->cs_limit = 0xFFFFFFFF;
288 c->cs_base = 0;
289 c->cs_arbytes.fields.seg_type = 0xb;
290 c->cs_arbytes.fields.s = 1;
291 c->cs_arbytes.fields.dpl = 0;
292 c->cs_arbytes.fields.p = 1;
293 c->cs_arbytes.fields.avl = 0;
294 c->cs_arbytes.fields.default_ops_size = 1;
295 c->cs_arbytes.fields.g = 1;
297 c->ds_sel = DATA_SELECTOR;
298 c->ds_limit = 0xFFFFFFFF;
299 c->ds_base = 0;
300 c->ds_arbytes = c->cs_arbytes;
301 c->ds_arbytes.fields.seg_type = 0x3;
303 c->es_sel = DATA_SELECTOR;
304 c->es_limit = 0xFFFFFFFF;
305 c->es_base = 0;
306 c->es_arbytes = c->ds_arbytes;
308 c->ss_sel = DATA_SELECTOR;
309 c->ss_limit = 0xFFFFFFFF;
310 c->ss_base = 0;
311 c->ss_arbytes = c->ds_arbytes;
313 c->fs_sel = DATA_SELECTOR;
314 c->fs_limit = 0xFFFFFFFF;
315 c->fs_base = 0;
316 c->fs_arbytes = c->ds_arbytes;
318 c->gs_sel = DATA_SELECTOR;
319 c->gs_limit = 0xFFFFFFFF;
320 c->gs_base = 0;
321 c->gs_arbytes = c->ds_arbytes;
323 c->tr_sel = TSS_SELECTOR;
324 c->tr_limit = sizeof(tss) - 1;
325 c->tr_base = (unsigned long) &tss;
326 c->tr_arbytes.fields.seg_type = 0xb; /* 0x9 | 0x2 (busy) */
327 c->tr_arbytes.fields.s = 0;
328 c->tr_arbytes.fields.dpl = 0;
329 c->tr_arbytes.fields.p = 1;
330 c->tr_arbytes.fields.avl = 0;
331 c->tr_arbytes.fields.default_ops_size = 0;
332 c->tr_arbytes.fields.g = 0;
334 c->ldtr_sel = 0;
335 c->ldtr_limit = 0;
336 c->ldtr_base = 0;
337 c->ldtr_arbytes = c->ds_arbytes;
338 c->ldtr_arbytes.fields.seg_type = 0x2;
339 c->ldtr_arbytes.fields.s = 0;
340 c->ldtr_arbytes.fields.dpl = 0;
341 c->ldtr_arbytes.fields.p = 1;
342 c->ldtr_arbytes.fields.avl = 0;
343 c->ldtr_arbytes.fields.default_ops_size = 0;
344 c->ldtr_arbytes.fields.g = 0;
345 }
347 /*
348 * Start BIOS by causing a world switch to vmxassist, which causes
349 * VM8086 to be enabled and control is transfered to F000:FFF0.
350 */
351 void
352 start_bios(void)
353 {
354 if (booting_cpu == 0)
355 printf("Start BIOS ...\n");
356 else
357 printf("Start AP %d from %08x ...\n",
358 booting_cpu, booting_vector << 12);
360 initialize_real_mode = 1;
361 set_cr0(get_cr0() & ~CR0_PE);
362 panic("vmxassist returned"); /* "cannot happen" */
363 }
365 int
366 main(void)
367 {
368 if (booting_cpu == 0)
369 banner();
371 #ifdef TEST
372 setup_paging();
373 #endif
375 setup_gdt();
376 setup_idt();
378 #ifndef TEST
379 set_cr4(get_cr4() | CR4_VME);
380 #endif
382 setup_ctx();
384 if (booting_cpu == 0)
385 setup_pic();
387 start_bios();
389 return 0;
390 }