ia64/xen-unstable

view tools/misc/cpuperf/cpuperf.c @ 7537:26fc51079f5f

Remove a non-portable and unused error.h, and use signal.h not
sys/signal.h (in tools/misc).
author kaf24@firebug.cl.cam.ac.uk
date Thu Oct 27 17:16:48 2005 +0100 (2005-10-27)
parents 06d84bf87159
children
line source
1 /*
2 * User mode program to program performance counters.
3 *
4 * JRB/IAP October 2003.
5 *
6 * $Id: cpuperf.c,v 1.2 2003/10/14 11:00:59 jrb44 Exp $
7 *
8 * $Log: cpuperf.c,v $
9 * Revision 1.2 2003/10/14 11:00:59 jrb44
10 * Added dcefault CPU. Added NONE CCCR.
11 *
12 * Revision 1.1 2003/10/13 16:49:44 jrb44
13 * Initial revision
14 *
15 */
17 #include <sys/types.h>
18 #include <sched.h>
19 #include <stdio.h>
20 #include <unistd.h>
21 #include <stdlib.h>
22 #include <string.h>
23 #include <errno.h>
25 #include "p4perf.h"
27 static inline void cpus_wrmsr(int cpu_mask,
28 int msr,
29 unsigned int low,
30 unsigned int high )
31 {
32 fprintf(stderr, "No backend to write MSR 0x%x <= 0x%08x%08x on %08x\n",
33 msr, high, low, cpu_mask);
34 }
36 static inline unsigned long long cpus_rdmsr( int cpu_mask, int msr )
37 {
38 fprintf(stderr, "No backend to read MSR 0x%x on %08x\n", msr, cpu_mask);
39 return 0;
40 }
42 #ifdef PERFCNTR
43 #include "cpuperf_perfcntr.h"
44 #define cpus_wrmsr perfcntr_wrmsr
45 #define cpus_rdmsr perfcntr_rdmsr
46 #endif
48 #ifdef XENO
49 #include "cpuperf_xeno.h"
50 #define cpus_wrmsr dom0_wrmsr
51 #define cpus_rdmsr dom0_rdmsr
52 #endif
54 struct macros {
55 char *name;
56 unsigned long msr_addr;
57 int number;
58 };
60 #define NO_CCCR 0xfffffffe
62 struct macros msr[] = {
63 {"BPU_COUNTER0", 0x300, 0},
64 {"BPU_COUNTER1", 0x301, 1},
65 {"BPU_COUNTER2", 0x302, 2},
66 {"BPU_COUNTER3", 0x303, 3},
67 {"MS_COUNTER0", 0x304, 4},
68 {"MS_COUNTER1", 0x305, 5},
69 {"MS_COUNTER2", 0x306, 6},
70 {"MS_COUNTER3", 0x307, 7},
71 {"FLAME_COUNTER0", 0x308, 8},
72 {"FLAME_COUNTER1", 0x309, 9},
73 {"FLAME_COUNTER2", 0x30a, 10},
74 {"FLAME_COUNTER3", 0x30b, 11},
75 {"IQ_COUNTER0", 0x30c, 12},
76 {"IQ_COUNTER1", 0x30d, 13},
77 {"IQ_COUNTER2", 0x30e, 14},
78 {"IQ_COUNTER3", 0x30f, 15},
79 {"IQ_COUNTER4", 0x310, 16},
80 {"IQ_COUNTER5", 0x311, 17},
81 {"BPU_CCCR0", 0x360, 0},
82 {"BPU_CCCR1", 0x361, 1},
83 {"BPU_CCCR2", 0x362, 2},
84 {"BPU_CCCR3", 0x363, 3},
85 {"MS_CCCR0", 0x364, 4},
86 {"MS_CCCR1", 0x365, 5},
87 {"MS_CCCR2", 0x366, 6},
88 {"MS_CCCR3", 0x367, 7},
89 {"FLAME_CCCR0", 0x368, 8},
90 {"FLAME_CCCR1", 0x369, 9},
91 {"FLAME_CCCR2", 0x36a, 10},
92 {"FLAME_CCCR3", 0x36b, 11},
93 {"IQ_CCCR0", 0x36c, 12},
94 {"IQ_CCCR1", 0x36d, 13},
95 {"IQ_CCCR2", 0x36e, 14},
96 {"IQ_CCCR3", 0x36f, 15},
97 {"IQ_CCCR4", 0x370, 16},
98 {"IQ_CCCR5", 0x371, 17},
99 {"BSU_ESCR0", 0x3a0, 7},
100 {"BSU_ESCR1", 0x3a1, 7},
101 {"FSB_ESCR0", 0x3a2, 6},
102 {"FSB_ESCR1", 0x3a3, 6},
103 {"MOB_ESCR0", 0x3aa, 2},
104 {"MOB_ESCR1", 0x3ab, 2},
105 {"PMH_ESCR0", 0x3ac, 4},
106 {"PMH_ESCR1", 0x3ad, 4},
107 {"BPU_ESCR0", 0x3b2, 0},
108 {"BPU_ESCR1", 0x3b3, 0},
109 {"IS_ESCR0", 0x3b4, 1},
110 {"IS_ESCR1", 0x3b5, 1},
111 {"ITLB_ESCR0", 0x3b6, 3},
112 {"ITLB_ESCR1", 0x3b7, 3},
113 {"IX_ESCR0", 0x3c8, 5},
114 {"IX_ESCR1", 0x3c9, 5},
115 {"MS_ESCR0", 0x3c0, 0},
116 {"MS_ESCR1", 0x3c1, 0},
117 {"TBPU_ESCR0", 0x3c2, 2},
118 {"TBPU_ESCR1", 0x3c3, 2},
119 {"TC_ESCR0", 0x3c4, 1},
120 {"TC_ESCR1", 0x3c5, 1},
121 {"FIRM_ESCR0", 0x3a4, 1},
122 {"FIRM_ESCR1", 0x3a5, 1},
123 {"FLAME_ESCR0", 0x3a6, 0},
124 {"FLAME_ESCR1", 0x3a7, 0},
125 {"DAC_ESCR0", 0x3a8, 5},
126 {"DAC_ESCR1", 0x3a9, 5},
127 {"SAAT_ESCR0", 0x3ae, 2},
128 {"SAAT_ESCR1", 0x3af, 2},
129 {"U2L_ESCR0", 0x3b0, 3},
130 {"U2L_ESCR1", 0x3b1, 3},
131 {"CRU_ESCR0", 0x3b8, 4},
132 {"CRU_ESCR1", 0x3b9, 4},
133 {"CRU_ESCR2", 0x3cc, 5},
134 {"CRU_ESCR3", 0x3cd, 5},
135 {"CRU_ESCR4", 0x3e0, 6},
136 {"CRU_ESCR5", 0x3e1, 6},
137 {"IQ_ESCR0", 0x3ba, 0},
138 {"IQ_ESCR1", 0x3bb, 0},
139 {"RAT_ESCR0", 0x3bc, 2},
140 {"RAT_ESCR1", 0x3bd, 2},
141 {"SSU_ESCR0", 0x3be, 3},
142 {"SSU_ESCR1", 0x3bf, 3},
143 {"ALF_ESCR0", 0x3ca, 1},
144 {"ALF_ESCR1", 0x3cb, 1},
145 {"PEBS_ENABLE", 0x3f1, 0},
146 {"PEBS_MATRIX_VERT", 0x3f2, 0},
147 {"NONE", NO_CCCR, 0},
148 {NULL, 0, 0}
149 };
151 struct macros *lookup_macro(char *str)
152 {
153 struct macros *m;
155 m = msr;
156 while (m->name) {
157 if (strcmp(m->name, str) == 0)
158 return m;
159 m++;
160 }
161 return NULL;
162 }
164 int main(int argc, char **argv)
165 {
166 int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
167 unsigned int cpu_mask = 1;
168 struct macros *escr = NULL, *cccr = NULL;
169 unsigned long escr_val, cccr_val;
170 int debug = 0;
171 unsigned long pebs = 0, pebs_vert = 0;
172 int pebs_x = 0, pebs_vert_x = 0;
173 int read = 0;
174 int compare = 0;
175 int complement = 0;
176 int edge = 0;
178 #ifdef XENO
179 xen_init();
180 #endif
183 while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:rkng")) != -1) {
184 switch((char)c) {
185 case 'P':
186 pebs |= 1 << atoi(optarg);
187 pebs_x = 1;
188 break;
189 case 'V':
190 pebs_vert |= 1 << atoi(optarg);
191 pebs_vert_x = 1;
192 break;
193 case 'd':
194 debug = 1;
195 break;
196 case 'c':
197 {
198 int cpu = atoi(optarg);
199 cpu_mask = (cpu == -1)?(~0):(1<<cpu);
200 }
201 break;
202 case 't': // ESCR thread bits
203 t = atoi(optarg);
204 break;
205 case 'e': // eventsel
206 es = atoi(optarg);
207 break;
208 case 'm': // eventmask
209 em = atoi(optarg);
210 break;
211 case 'T': // tag value
212 tv = atoi(optarg);
213 te = 1;
214 break;
215 case 'E':
216 escr = lookup_macro(optarg);
217 if (!escr) {
218 fprintf(stderr, "Macro '%s' not found.\n", optarg);
219 exit(1);
220 }
221 break;
222 case 'C':
223 cccr = lookup_macro(optarg);
224 if (!cccr) {
225 fprintf(stderr, "Macro '%s' not found.\n", optarg);
226 exit(1);
227 }
228 break;
229 case 'r':
230 read = 1;
231 break;
232 case 'k':
233 compare = 1;
234 break;
235 case 'n':
236 complement = 1;
237 break;
238 case 'g':
239 edge = 1;
240 break;
241 }
242 }
244 if (read) {
245 int i;
246 for (i=0x300;i<0x312;i++)
247 printf("%010llu ",cpus_rdmsr( cpu_mask, i ) );
248 printf("\n");
249 exit(1);
250 }
252 if (!escr) {
253 fprintf(stderr, "Need an ESCR.\n");
254 exit(1);
255 }
256 if (!cccr) {
257 fprintf(stderr, "Need a counter number.\n");
258 exit(1);
259 }
261 escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
262 P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
263 cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
264 ((compare)?P4_CCCR_COMPARE:0) |
265 ((complement)?P4_CCCR_COMPLEMENT:0) |
266 ((edge)?P4_CCCR_EDGE:0) |
267 P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
269 if (debug) {
270 fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
271 if (cccr->msr_addr != NO_CCCR)
272 fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
273 cccr->msr_addr, cccr_val, cccr->number);
274 if (pebs_x)
275 fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
276 MSR_P4_PEBS_ENABLE, pebs);
277 if (pebs_vert_x)
278 fprintf(stderr, "PMV 0x%x <= 0x%08lx\n",
279 MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
280 }
282 cpus_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
283 if (cccr->msr_addr != NO_CCCR)
284 cpus_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
286 if (pebs_x)
287 cpus_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
289 if (pebs_vert_x)
290 cpus_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
292 return 0;
293 }
295 // End of $RCSfile: cpuperf.c,v $