ia64/xen-unstable

view xen/arch/x86/io_apic.c @ 5374:22e42640bcff

bitkeeper revision 1.1691.1.8 (42a6fb21d3oJwpLmOxa2jKHRJ-8fJg)

First phase of removing IRQ numbers from Xen (transitioning to
IRQ addressing by 'legacy ISA IRQ', 'interrupt vector', and
'I/O APIC address + pin' as appropriate). Overall plan is to move
I/O APIC parsing and setup out of Xen (so we start DOM0 in virtual wire
mode).
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Jun 08 14:05:21 2005 +0000 (2005-06-08)
parents 731cd57862e5
children 0be846d7d261
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/init.h>
26 #include <xen/irq.h>
27 #include <xen/delay.h>
28 #include <xen/sched.h>
29 #include <xen/acpi.h>
30 #include <asm/io.h>
31 #include <asm/mc146818rtc.h>
32 #include <asm/smp.h>
33 #include <asm/desc.h>
34 #include <mach_apic.h>
35 #include <io_ports.h>
37 int (*ioapic_renumber_irq)(int ioapic, int irq);
38 atomic_t irq_mis_count;
40 static DEFINE_SPINLOCK(ioapic_lock);
42 int skip_ioapic_setup;
44 /*
45 * # of IRQ routing registers
46 */
47 int nr_ioapic_registers[MAX_IO_APICS];
49 /*
50 * Rough estimation of how many shared IRQs there are, can
51 * be changed anytime.
52 */
53 #define MAX_PLUS_SHARED_IRQS NR_IRQS
54 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
56 /*
57 * This is performance-critical, we want to do it O(1)
58 *
59 * the indexing order of this array favors 1:1 mappings
60 * between pins and IRQs.
61 */
63 static struct irq_pin_list {
64 int apic, pin, next;
65 } irq_2_pin[PIN_MAP_SIZE];
67 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
68 #if 0
69 #ifdef CONFIG_PCI_MSI
70 #define vector_to_irq(vector) \
71 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
72 #else
73 #define vector_to_irq(vector) (vector)
74 #endif
75 #endif
77 /*
78 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
79 * shared ISA-space IRQs, so we have to support them. We are super
80 * fast in the common case, and fast for shared ISA-space IRQs.
81 */
82 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
83 {
84 static int first_free_entry = NR_IRQS;
85 struct irq_pin_list *entry = irq_2_pin + irq;
87 while (entry->next)
88 entry = irq_2_pin + entry->next;
90 if (entry->pin != -1) {
91 entry->next = first_free_entry;
92 entry = irq_2_pin + entry->next;
93 if (++first_free_entry >= PIN_MAP_SIZE)
94 panic("io_apic.c: whoops");
95 }
96 entry->apic = apic;
97 entry->pin = pin;
98 }
100 /*
101 * Reroute an IRQ to a different pin.
102 */
103 static void __init replace_pin_at_irq(unsigned int irq,
104 int oldapic, int oldpin,
105 int newapic, int newpin)
106 {
107 struct irq_pin_list *entry = irq_2_pin + irq;
109 while (1) {
110 if (entry->apic == oldapic && entry->pin == oldpin) {
111 entry->apic = newapic;
112 entry->pin = newpin;
113 }
114 if (!entry->next)
115 break;
116 entry = irq_2_pin + entry->next;
117 }
118 }
120 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
121 {
122 struct irq_pin_list *entry = irq_2_pin + irq;
123 unsigned int pin, reg;
125 for (;;) {
126 pin = entry->pin;
127 if (pin == -1)
128 break;
129 reg = io_apic_read(entry->apic, 0x10 + pin*2);
130 reg &= ~disable;
131 reg |= enable;
132 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
133 if (!entry->next)
134 break;
135 entry = irq_2_pin + entry->next;
136 }
137 }
139 /* mask = 1 */
140 static void __mask_IO_APIC_irq (unsigned int irq)
141 {
142 __modify_IO_APIC_irq(irq, 0x00010000, 0);
143 }
145 /* mask = 0 */
146 static void __unmask_IO_APIC_irq (unsigned int irq)
147 {
148 __modify_IO_APIC_irq(irq, 0, 0x00010000);
149 }
151 /* trigger = 0 */
152 static void __edge_IO_APIC_irq (unsigned int irq)
153 {
154 __modify_IO_APIC_irq(irq, 0, 0x00008000);
155 }
157 /* trigger = 1 */
158 static void __level_IO_APIC_irq (unsigned int irq)
159 {
160 __modify_IO_APIC_irq(irq, 0x00008000, 0);
161 }
163 static void mask_IO_APIC_irq (unsigned int irq)
164 {
165 unsigned long flags;
167 spin_lock_irqsave(&ioapic_lock, flags);
168 __mask_IO_APIC_irq(irq);
169 spin_unlock_irqrestore(&ioapic_lock, flags);
170 }
172 static void unmask_IO_APIC_irq (unsigned int irq)
173 {
174 unsigned long flags;
176 spin_lock_irqsave(&ioapic_lock, flags);
177 __unmask_IO_APIC_irq(irq);
178 spin_unlock_irqrestore(&ioapic_lock, flags);
179 }
181 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
182 {
183 struct IO_APIC_route_entry entry;
184 unsigned long flags;
186 /* Check delivery_mode to be sure we're not clearing an SMI pin */
187 spin_lock_irqsave(&ioapic_lock, flags);
188 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
189 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
190 spin_unlock_irqrestore(&ioapic_lock, flags);
191 if (entry.delivery_mode == dest_SMI)
192 return;
194 /*
195 * Disable it in the IO-APIC irq-routing table:
196 */
197 memset(&entry, 0, sizeof(entry));
198 entry.mask = 1;
199 spin_lock_irqsave(&ioapic_lock, flags);
200 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
201 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
202 spin_unlock_irqrestore(&ioapic_lock, flags);
203 }
205 static void clear_IO_APIC (void)
206 {
207 int apic, pin;
209 for (apic = 0; apic < nr_ioapics; apic++)
210 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
211 clear_IO_APIC_pin(apic, pin);
212 }
214 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
215 {
216 unsigned long flags;
217 int pin;
218 struct irq_pin_list *entry = irq_2_pin + irq;
219 unsigned int apicid_value;
221 apicid_value = cpu_mask_to_apicid(cpumask);
222 /* Prepare to do the io_apic_write */
223 apicid_value = apicid_value << 24;
224 spin_lock_irqsave(&ioapic_lock, flags);
225 for (;;) {
226 pin = entry->pin;
227 if (pin == -1)
228 break;
229 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
230 if (!entry->next)
231 break;
232 entry = irq_2_pin + entry->next;
233 }
234 spin_unlock_irqrestore(&ioapic_lock, flags);
235 }
237 /*
238 * Find the IRQ entry number of a certain pin.
239 */
240 static int find_irq_entry(int apic, int pin, int type)
241 {
242 int i;
244 for (i = 0; i < mp_irq_entries; i++)
245 if (mp_irqs[i].mpc_irqtype == type &&
246 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
247 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
248 mp_irqs[i].mpc_dstirq == pin)
249 return i;
251 return -1;
252 }
254 /*
255 * Find the pin to which IRQ[irq] (ISA) is connected
256 */
257 static int find_isa_irq_pin(int irq, int type)
258 {
259 int i;
261 for (i = 0; i < mp_irq_entries; i++) {
262 int lbus = mp_irqs[i].mpc_srcbus;
264 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
265 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
266 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
267 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
268 ) &&
269 (mp_irqs[i].mpc_irqtype == type) &&
270 (mp_irqs[i].mpc_srcbusirq == irq))
272 return mp_irqs[i].mpc_dstirq;
273 }
274 return -1;
275 }
277 /*
278 * Find a specific PCI IRQ entry.
279 * Not an __init, possibly needed by modules
280 */
281 static int pin_2_irq(int idx, int apic, int pin);
283 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
284 {
285 int apic, i, best_guess = -1;
287 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
288 "slot:%d, pin:%d.\n", bus, slot, pin);
289 if (mp_bus_id_to_pci_bus[bus] == -1) {
290 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
291 return -1;
292 }
293 for (i = 0; i < mp_irq_entries; i++) {
294 int lbus = mp_irqs[i].mpc_srcbus;
296 for (apic = 0; apic < nr_ioapics; apic++)
297 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
298 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
299 break;
301 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
302 !mp_irqs[i].mpc_irqtype &&
303 (bus == lbus) &&
304 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
305 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
307 if (!(apic || IO_APIC_IRQ(irq)))
308 continue;
310 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
311 return irq;
312 /*
313 * Use the first all-but-pin matching entry as a
314 * best-guess fuzzy result for broken mptables.
315 */
316 if (best_guess < 0)
317 best_guess = irq;
318 }
319 }
320 return best_guess;
321 }
323 /*
324 * This function currently is only a helper for the i386 smp boot process where
325 * we need to reprogram the ioredtbls to cater for the cpus which have come online
326 * so mask in all cases should simply be TARGET_CPUS
327 */
328 void __init setup_ioapic_dest(void)
329 {
330 int pin, ioapic, irq, irq_entry;
332 if (skip_ioapic_setup == 1)
333 return;
335 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
336 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
337 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
338 if (irq_entry == -1)
339 continue;
340 irq = pin_2_irq(irq_entry, ioapic, pin);
341 set_ioapic_affinity_irq(irq, TARGET_CPUS);
342 }
344 }
345 }
347 /*
348 * EISA Edge/Level control register, ELCR
349 */
350 static int EISA_ELCR(unsigned int irq)
351 {
352 if (irq < 16) {
353 unsigned int port = 0x4d0 + (irq >> 3);
354 return (inb(port) >> (irq & 7)) & 1;
355 }
356 apic_printk(APIC_VERBOSE, KERN_INFO
357 "Broken MPtable reports ISA irq %d\n", irq);
358 return 0;
359 }
361 /* EISA interrupts are always polarity zero and can be edge or level
362 * trigger depending on the ELCR value. If an interrupt is listed as
363 * EISA conforming in the MP table, that means its trigger type must
364 * be read in from the ELCR */
366 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
367 #define default_EISA_polarity(idx) (0)
369 /* ISA interrupts are always polarity zero edge triggered,
370 * when listed as conforming in the MP table. */
372 #define default_ISA_trigger(idx) (0)
373 #define default_ISA_polarity(idx) (0)
375 /* PCI interrupts are always polarity one level triggered,
376 * when listed as conforming in the MP table. */
378 #define default_PCI_trigger(idx) (1)
379 #define default_PCI_polarity(idx) (1)
381 /* MCA interrupts are always polarity zero level triggered,
382 * when listed as conforming in the MP table. */
384 #define default_MCA_trigger(idx) (1)
385 #define default_MCA_polarity(idx) (0)
387 /* NEC98 interrupts are always polarity zero edge triggered,
388 * when listed as conforming in the MP table. */
390 #define default_NEC98_trigger(idx) (0)
391 #define default_NEC98_polarity(idx) (0)
393 static int __init MPBIOS_polarity(int idx)
394 {
395 int bus = mp_irqs[idx].mpc_srcbus;
396 int polarity;
398 /*
399 * Determine IRQ line polarity (high active or low active):
400 */
401 switch (mp_irqs[idx].mpc_irqflag & 3)
402 {
403 case 0: /* conforms, ie. bus-type dependent polarity */
404 {
405 switch (mp_bus_id_to_type[bus])
406 {
407 case MP_BUS_ISA: /* ISA pin */
408 {
409 polarity = default_ISA_polarity(idx);
410 break;
411 }
412 case MP_BUS_EISA: /* EISA pin */
413 {
414 polarity = default_EISA_polarity(idx);
415 break;
416 }
417 case MP_BUS_PCI: /* PCI pin */
418 {
419 polarity = default_PCI_polarity(idx);
420 break;
421 }
422 case MP_BUS_MCA: /* MCA pin */
423 {
424 polarity = default_MCA_polarity(idx);
425 break;
426 }
427 case MP_BUS_NEC98: /* NEC 98 pin */
428 {
429 polarity = default_NEC98_polarity(idx);
430 break;
431 }
432 default:
433 {
434 printk(KERN_WARNING "broken BIOS!!\n");
435 polarity = 1;
436 break;
437 }
438 }
439 break;
440 }
441 case 1: /* high active */
442 {
443 polarity = 0;
444 break;
445 }
446 case 2: /* reserved */
447 {
448 printk(KERN_WARNING "broken BIOS!!\n");
449 polarity = 1;
450 break;
451 }
452 case 3: /* low active */
453 {
454 polarity = 1;
455 break;
456 }
457 default: /* invalid */
458 {
459 printk(KERN_WARNING "broken BIOS!!\n");
460 polarity = 1;
461 break;
462 }
463 }
464 return polarity;
465 }
467 static int MPBIOS_trigger(int idx)
468 {
469 int bus = mp_irqs[idx].mpc_srcbus;
470 int trigger;
472 /*
473 * Determine IRQ trigger mode (edge or level sensitive):
474 */
475 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
476 {
477 case 0: /* conforms, ie. bus-type dependent */
478 {
479 switch (mp_bus_id_to_type[bus])
480 {
481 case MP_BUS_ISA: /* ISA pin */
482 {
483 trigger = default_ISA_trigger(idx);
484 break;
485 }
486 case MP_BUS_EISA: /* EISA pin */
487 {
488 trigger = default_EISA_trigger(idx);
489 break;
490 }
491 case MP_BUS_PCI: /* PCI pin */
492 {
493 trigger = default_PCI_trigger(idx);
494 break;
495 }
496 case MP_BUS_MCA: /* MCA pin */
497 {
498 trigger = default_MCA_trigger(idx);
499 break;
500 }
501 case MP_BUS_NEC98: /* NEC 98 pin */
502 {
503 trigger = default_NEC98_trigger(idx);
504 break;
505 }
506 default:
507 {
508 printk(KERN_WARNING "broken BIOS!!\n");
509 trigger = 1;
510 break;
511 }
512 }
513 break;
514 }
515 case 1: /* edge */
516 {
517 trigger = 0;
518 break;
519 }
520 case 2: /* reserved */
521 {
522 printk(KERN_WARNING "broken BIOS!!\n");
523 trigger = 1;
524 break;
525 }
526 case 3: /* level */
527 {
528 trigger = 1;
529 break;
530 }
531 default: /* invalid */
532 {
533 printk(KERN_WARNING "broken BIOS!!\n");
534 trigger = 0;
535 break;
536 }
537 }
538 return trigger;
539 }
541 static inline int irq_polarity(int idx)
542 {
543 return MPBIOS_polarity(idx);
544 }
546 static inline int irq_trigger(int idx)
547 {
548 return MPBIOS_trigger(idx);
549 }
551 static int pin_2_irq(int idx, int apic, int pin)
552 {
553 int irq, i;
554 int bus = mp_irqs[idx].mpc_srcbus;
556 /*
557 * Debugging check, we are in big trouble if this message pops up!
558 */
559 if (mp_irqs[idx].mpc_dstirq != pin)
560 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
562 switch (mp_bus_id_to_type[bus])
563 {
564 case MP_BUS_ISA: /* ISA pin */
565 case MP_BUS_EISA:
566 case MP_BUS_MCA:
567 case MP_BUS_NEC98:
568 {
569 irq = mp_irqs[idx].mpc_srcbusirq;
570 break;
571 }
572 case MP_BUS_PCI: /* PCI pin */
573 {
574 /*
575 * PCI IRQs are mapped in order
576 */
577 i = irq = 0;
578 while (i < apic)
579 irq += nr_ioapic_registers[i++];
580 irq += pin;
582 /*
583 * For MPS mode, so far only needed by ES7000 platform
584 */
585 if (ioapic_renumber_irq)
586 irq = ioapic_renumber_irq(apic, irq);
588 break;
589 }
590 default:
591 {
592 printk(KERN_ERR "unknown bus type %d.\n",bus);
593 irq = 0;
594 break;
595 }
596 }
598 return irq;
599 }
601 static inline int IO_APIC_irq_trigger(int irq)
602 {
603 int apic, idx, pin;
605 for (apic = 0; apic < nr_ioapics; apic++) {
606 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
607 idx = find_irq_entry(apic,pin,mp_INT);
608 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
609 return irq_trigger(idx);
610 }
611 }
612 /*
613 * nonexistent IRQs are edge default
614 */
615 return 0;
616 }
618 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
619 u8 irq_vector[NR_IRQ_VECTORS];
621 int assign_irq_vector(int irq)
622 {
623 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
625 BUG_ON(irq >= NR_IRQ_VECTORS);
626 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
627 return IO_APIC_VECTOR(irq);
628 next:
629 current_vector += 8;
631 /* Skip the hypercall vector. */
632 if (current_vector == HYPERCALL_VECTOR)
633 goto next;
635 /* Skip the Linux/BSD fast-trap vector. */
636 if (current_vector == 0x80)
637 goto next;
639 if (current_vector >= FIRST_SYSTEM_VECTOR) {
640 offset++;
641 if (!(offset%8))
642 return -ENOSPC;
643 current_vector = FIRST_DEVICE_VECTOR + offset;
644 }
646 vector_irq[current_vector] = irq;
647 if (irq != AUTO_ASSIGN)
648 IO_APIC_VECTOR(irq) = current_vector;
650 return current_vector;
651 }
653 static struct hw_interrupt_type ioapic_level_type;
654 static struct hw_interrupt_type ioapic_edge_type;
656 #define IOAPIC_AUTO -1
657 #define IOAPIC_EDGE 0
658 #define IOAPIC_LEVEL 1
660 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
661 {
662 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
663 trigger == IOAPIC_LEVEL)
664 irq_desc[vector].handler = &ioapic_level_type;
665 else
666 irq_desc[vector].handler = &ioapic_edge_type;
667 }
669 void __init setup_IO_APIC_irqs(void)
670 {
671 struct IO_APIC_route_entry entry;
672 int apic, pin, idx, irq, first_notcon = 1, vector;
673 unsigned long flags;
675 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
677 for (apic = 0; apic < nr_ioapics; apic++) {
678 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
680 /*
681 * add it to the IO-APIC irq-routing table:
682 */
683 memset(&entry,0,sizeof(entry));
685 entry.delivery_mode = INT_DELIVERY_MODE;
686 entry.dest_mode = INT_DEST_MODE;
687 entry.mask = 0; /* enable IRQ */
688 entry.dest.logical.logical_dest =
689 cpu_mask_to_apicid(TARGET_CPUS);
691 idx = find_irq_entry(apic,pin,mp_INT);
692 if (idx == -1) {
693 if (first_notcon) {
694 apic_printk(APIC_VERBOSE, KERN_DEBUG
695 " IO-APIC (apicid-pin) %d-%d",
696 mp_ioapics[apic].mpc_apicid,
697 pin);
698 first_notcon = 0;
699 } else
700 apic_printk(APIC_VERBOSE, ", %d-%d",
701 mp_ioapics[apic].mpc_apicid, pin);
702 continue;
703 }
705 entry.trigger = irq_trigger(idx);
706 entry.polarity = irq_polarity(idx);
708 if (irq_trigger(idx)) {
709 entry.trigger = 1;
710 entry.mask = 1;
711 }
713 irq = pin_2_irq(idx, apic, pin);
714 /*
715 * skip adding the timer int on secondary nodes, which causes
716 * a small but painful rift in the time-space continuum
717 */
718 if (multi_timer_check(apic, irq))
719 continue;
720 else
721 add_pin_to_irq(irq, apic, pin);
723 if (!apic && !IO_APIC_IRQ(irq))
724 continue;
726 if (IO_APIC_IRQ(irq)) {
727 vector = assign_irq_vector(irq);
728 entry.vector = vector;
729 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
731 if (!apic && (irq < 16))
732 disable_8259A_irq(irq);
733 }
734 spin_lock_irqsave(&ioapic_lock, flags);
735 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
736 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
737 spin_unlock_irqrestore(&ioapic_lock, flags);
738 }
739 }
741 if (!first_notcon)
742 apic_printk(APIC_VERBOSE, " not connected.\n");
743 }
745 /*
746 * Set up the 8259A-master output pin:
747 */
748 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
749 {
750 struct IO_APIC_route_entry entry;
751 unsigned long flags;
753 memset(&entry,0,sizeof(entry));
755 disable_8259A_irq(0);
757 /* mask LVT0 */
758 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
760 /*
761 * We use logical delivery to get the timer IRQ
762 * to the first CPU.
763 */
764 entry.dest_mode = INT_DEST_MODE;
765 entry.mask = 0; /* unmask IRQ now */
766 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
767 entry.delivery_mode = INT_DELIVERY_MODE;
768 entry.polarity = 0;
769 entry.trigger = 0;
770 entry.vector = vector;
772 /*
773 * The timer IRQ doesn't have to know that behind the
774 * scene we have a 8259A-master in AEOI mode ...
775 */
776 irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
778 /*
779 * Add it to the IO-APIC irq-routing table:
780 */
781 spin_lock_irqsave(&ioapic_lock, flags);
782 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
783 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
784 spin_unlock_irqrestore(&ioapic_lock, flags);
786 enable_8259A_irq(0);
787 }
789 static inline void UNEXPECTED_IO_APIC(void)
790 {
791 }
793 void __init print_IO_APIC(void)
794 {
795 int apic, i;
796 union IO_APIC_reg_00 reg_00;
797 union IO_APIC_reg_01 reg_01;
798 union IO_APIC_reg_02 reg_02;
799 union IO_APIC_reg_03 reg_03;
800 unsigned long flags;
802 if (apic_verbosity == APIC_QUIET)
803 return;
805 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
806 for (i = 0; i < nr_ioapics; i++)
807 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
808 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
810 /*
811 * We are a bit conservative about what we expect. We have to
812 * know about every hardware change ASAP.
813 */
814 printk(KERN_INFO "testing the IO APIC.......................\n");
816 for (apic = 0; apic < nr_ioapics; apic++) {
818 spin_lock_irqsave(&ioapic_lock, flags);
819 reg_00.raw = io_apic_read(apic, 0);
820 reg_01.raw = io_apic_read(apic, 1);
821 if (reg_01.bits.version >= 0x10)
822 reg_02.raw = io_apic_read(apic, 2);
823 if (reg_01.bits.version >= 0x20)
824 reg_03.raw = io_apic_read(apic, 3);
825 spin_unlock_irqrestore(&ioapic_lock, flags);
827 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
828 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
829 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
830 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
831 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
832 if (reg_00.bits.ID >= get_physical_broadcast())
833 UNEXPECTED_IO_APIC();
834 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
835 UNEXPECTED_IO_APIC();
837 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
838 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
839 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
840 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
841 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
842 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
843 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
844 (reg_01.bits.entries != 0x2E) &&
845 (reg_01.bits.entries != 0x3F)
846 )
847 UNEXPECTED_IO_APIC();
849 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
850 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
851 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
852 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
853 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
854 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
855 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
856 )
857 UNEXPECTED_IO_APIC();
858 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
859 UNEXPECTED_IO_APIC();
861 /*
862 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
863 * but the value of reg_02 is read as the previous read register
864 * value, so ignore it if reg_02 == reg_01.
865 */
866 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
867 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
868 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
869 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
870 UNEXPECTED_IO_APIC();
871 }
873 /*
874 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
875 * or reg_03, but the value of reg_0[23] is read as the previous read
876 * register value, so ignore it if reg_03 == reg_0[12].
877 */
878 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
879 reg_03.raw != reg_01.raw) {
880 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
881 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
882 if (reg_03.bits.__reserved_1)
883 UNEXPECTED_IO_APIC();
884 }
886 printk(KERN_DEBUG ".... IRQ redirection table:\n");
888 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
889 " Stat Dest Deli Vect: \n");
891 for (i = 0; i <= reg_01.bits.entries; i++) {
892 struct IO_APIC_route_entry entry;
894 spin_lock_irqsave(&ioapic_lock, flags);
895 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
896 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
897 spin_unlock_irqrestore(&ioapic_lock, flags);
899 printk(KERN_DEBUG " %02x %03X %02X ",
900 i,
901 entry.dest.logical.logical_dest,
902 entry.dest.physical.physical_dest
903 );
905 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
906 entry.mask,
907 entry.trigger,
908 entry.irr,
909 entry.polarity,
910 entry.delivery_status,
911 entry.dest_mode,
912 entry.delivery_mode,
913 entry.vector
914 );
915 }
916 }
917 if (use_pci_vector())
918 printk(KERN_INFO "Using vector-based indexing\n");
919 printk(KERN_DEBUG "IRQ to pin mappings:\n");
920 for (i = 0; i < NR_IRQS; i++) {
921 struct irq_pin_list *entry = irq_2_pin + i;
922 if (entry->pin < 0)
923 continue;
924 if (use_pci_vector() && !platform_legacy_irq(i))
925 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
926 else
927 printk(KERN_DEBUG "IRQ%d ", i);
928 for (;;) {
929 printk("-> %d:%d", entry->apic, entry->pin);
930 if (!entry->next)
931 break;
932 entry = irq_2_pin + entry->next;
933 }
934 printk("\n");
935 }
937 printk(KERN_INFO ".................................... done.\n");
939 return;
940 }
942 static void __init enable_IO_APIC(void)
943 {
944 union IO_APIC_reg_01 reg_01;
945 int i;
946 unsigned long flags;
948 for (i = 0; i < PIN_MAP_SIZE; i++) {
949 irq_2_pin[i].pin = -1;
950 irq_2_pin[i].next = 0;
951 }
953 /*
954 * The number of IO-APIC IRQ registers (== #pins):
955 */
956 for (i = 0; i < nr_ioapics; i++) {
957 spin_lock_irqsave(&ioapic_lock, flags);
958 reg_01.raw = io_apic_read(i, 1);
959 spin_unlock_irqrestore(&ioapic_lock, flags);
960 nr_ioapic_registers[i] = reg_01.bits.entries+1;
961 }
963 /*
964 * Do not trust the IO-APIC being empty at bootup
965 */
966 clear_IO_APIC();
967 }
969 /*
970 * Not an __init, needed by the reboot code
971 */
972 void disable_IO_APIC(void)
973 {
974 /*
975 * Clear the IO-APIC before rebooting:
976 */
977 clear_IO_APIC();
979 disconnect_bsp_APIC();
980 }
982 /*
983 * function to set the IO-APIC physical IDs based on the
984 * values stored in the MPC table.
985 *
986 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
987 */
989 #ifndef CONFIG_X86_NUMAQ
990 static void __init setup_ioapic_ids_from_mpc(void)
991 {
992 union IO_APIC_reg_00 reg_00;
993 physid_mask_t phys_id_present_map;
994 int apic;
995 int i;
996 unsigned char old_id;
997 unsigned long flags;
999 /*
1000 * This is broken; anything with a real cpu count has to
1001 * circumvent this idiocy regardless.
1002 */
1003 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1005 /*
1006 * Set the IOAPIC ID to the value stored in the MPC table.
1007 */
1008 for (apic = 0; apic < nr_ioapics; apic++) {
1010 /* Read the register 0 value */
1011 spin_lock_irqsave(&ioapic_lock, flags);
1012 reg_00.raw = io_apic_read(apic, 0);
1013 spin_unlock_irqrestore(&ioapic_lock, flags);
1015 old_id = mp_ioapics[apic].mpc_apicid;
1017 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1018 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1019 apic, mp_ioapics[apic].mpc_apicid);
1020 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1021 reg_00.bits.ID);
1022 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1025 /* Don't check I/O APIC IDs for some xAPIC systems. They have
1026 * no meaning without the serial APIC bus. */
1027 if (NO_IOAPIC_CHECK)
1028 continue;
1029 /*
1030 * Sanity check, is the ID really free? Every APIC in a
1031 * system must have a unique ID or we get lots of nice
1032 * 'stuck on smp_invalidate_needed IPI wait' messages.
1033 */
1034 if (check_apicid_used(phys_id_present_map,
1035 mp_ioapics[apic].mpc_apicid)) {
1036 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1037 apic, mp_ioapics[apic].mpc_apicid);
1038 for (i = 0; i < get_physical_broadcast(); i++)
1039 if (!physid_isset(i, phys_id_present_map))
1040 break;
1041 if (i >= get_physical_broadcast())
1042 panic("Max APIC ID exceeded!\n");
1043 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1044 i);
1045 physid_set(i, phys_id_present_map);
1046 mp_ioapics[apic].mpc_apicid = i;
1047 } else {
1048 physid_mask_t tmp;
1049 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1050 apic_printk(APIC_VERBOSE, "Setting %d in the "
1051 "phys_id_present_map\n",
1052 mp_ioapics[apic].mpc_apicid);
1053 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1057 /*
1058 * We need to adjust the IRQ routing table
1059 * if the ID changed.
1060 */
1061 if (old_id != mp_ioapics[apic].mpc_apicid)
1062 for (i = 0; i < mp_irq_entries; i++)
1063 if (mp_irqs[i].mpc_dstapic == old_id)
1064 mp_irqs[i].mpc_dstapic
1065 = mp_ioapics[apic].mpc_apicid;
1067 /*
1068 * Read the right value from the MPC table and
1069 * write it into the ID register.
1070 */
1071 apic_printk(APIC_VERBOSE, KERN_INFO
1072 "...changing IO-APIC physical APIC ID to %d ...",
1073 mp_ioapics[apic].mpc_apicid);
1075 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1076 spin_lock_irqsave(&ioapic_lock, flags);
1077 io_apic_write(apic, 0, reg_00.raw);
1078 spin_unlock_irqrestore(&ioapic_lock, flags);
1080 /*
1081 * Sanity check
1082 */
1083 spin_lock_irqsave(&ioapic_lock, flags);
1084 reg_00.raw = io_apic_read(apic, 0);
1085 spin_unlock_irqrestore(&ioapic_lock, flags);
1086 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1087 printk("could not set ID!\n");
1088 else
1089 apic_printk(APIC_VERBOSE, " ok.\n");
1092 #else
1093 static void __init setup_ioapic_ids_from_mpc(void) { }
1094 #endif
1096 /*
1097 * There is a nasty bug in some older SMP boards, their mptable lies
1098 * about the timer IRQ. We do the following to work around the situation:
1100 * - timer IRQ defaults to IO-APIC IRQ
1101 * - if this function detects that timer IRQs are defunct, then we fall
1102 * back to ISA timer IRQs
1103 */
1104 static int __init timer_irq_works(void)
1106 unsigned long t1 = jiffies;
1108 local_irq_enable();
1109 /* Let ten ticks pass... */
1110 mdelay((10 * 1000) / HZ);
1112 /*
1113 * Expect a few ticks at least, to be sure some possible
1114 * glue logic does not lock up after one or two first
1115 * ticks in a non-ExtINT mode. Also the local APIC
1116 * might have cached one ExtINT interrupt. Finally, at
1117 * least one tick may be lost due to delays.
1118 */
1119 if (jiffies - t1 > 4)
1120 return 1;
1122 return 0;
1125 /*
1126 * In the SMP+IOAPIC case it might happen that there are an unspecified
1127 * number of pending IRQ events unhandled. These cases are very rare,
1128 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1129 * better to do it this way as thus we do not have to be aware of
1130 * 'pending' interrupts in the IRQ path, except at this point.
1131 */
1132 /*
1133 * Edge triggered needs to resend any interrupt
1134 * that was delayed but this is now handled in the device
1135 * independent code.
1136 */
1138 /*
1139 * Starting up a edge-triggered IO-APIC interrupt is
1140 * nasty - we need to make sure that we get the edge.
1141 * If it is already asserted for some reason, we need
1142 * return 1 to indicate that is was pending.
1144 * This is not complete - we should be able to fake
1145 * an edge even if it isn't on the 8259A...
1146 */
1147 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1149 int was_pending = 0;
1150 unsigned long flags;
1152 spin_lock_irqsave(&ioapic_lock, flags);
1153 if (irq < 16) {
1154 disable_8259A_irq(irq);
1155 if (i8259A_irq_pending(irq))
1156 was_pending = 1;
1158 __unmask_IO_APIC_irq(irq);
1159 spin_unlock_irqrestore(&ioapic_lock, flags);
1161 return was_pending;
1164 /*
1165 * Once we have recorded IRQ_PENDING already, we can mask the
1166 * interrupt for real. This prevents IRQ storms from unhandled
1167 * devices.
1168 */
1169 static void ack_edge_ioapic_irq(unsigned int irq)
1171 if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
1172 == (IRQ_PENDING | IRQ_DISABLED))
1173 mask_IO_APIC_irq(irq);
1174 ack_APIC_irq();
1177 /*
1178 * Level triggered interrupts can just be masked,
1179 * and shutting down and starting up the interrupt
1180 * is the same as enabling and disabling them -- except
1181 * with a startup need to return a "was pending" value.
1183 * Level triggered interrupts are special because we
1184 * do not touch any IO-APIC register while handling
1185 * them. We ack the APIC in the end-IRQ handler, not
1186 * in the start-IRQ-handler. Protection against reentrance
1187 * from the same interrupt is still provided, both by the
1188 * generic IRQ layer and by the fact that an unacked local
1189 * APIC does not accept IRQs.
1190 */
1191 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1193 unmask_IO_APIC_irq(irq);
1195 return 0; /* don't check for pending */
1198 static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1200 unsigned long v;
1201 int i;
1203 mask_IO_APIC_irq(irq);
1204 /*
1205 * It appears there is an erratum which affects at least version 0x11
1206 * of I/O APIC (that's the 82093AA and cores integrated into various
1207 * chipsets). Under certain conditions a level-triggered interrupt is
1208 * erroneously delivered as edge-triggered one but the respective IRR
1209 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1210 * message but it will never arrive and further interrupts are blocked
1211 * from the source. The exact reason is so far unknown, but the
1212 * phenomenon was observed when two consecutive interrupt requests
1213 * from a given source get delivered to the same CPU and the source is
1214 * temporarily disabled in between.
1216 * A workaround is to simulate an EOI message manually. We achieve it
1217 * by setting the trigger mode to edge and then to level when the edge
1218 * trigger mode gets detected in the TMR of a local APIC for a
1219 * level-triggered interrupt. We mask the source for the time of the
1220 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1221 * The idea is from Manfred Spraul. --macro
1222 */
1223 i = IO_APIC_VECTOR(irq);
1225 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1227 ack_APIC_irq();
1229 if (!(v & (1 << (i & 0x1f)))) {
1230 atomic_inc(&irq_mis_count);
1231 spin_lock(&ioapic_lock);
1232 __edge_IO_APIC_irq(irq);
1233 __level_IO_APIC_irq(irq);
1234 spin_unlock(&ioapic_lock);
1238 static void end_level_ioapic_irq (unsigned int irq)
1240 unmask_IO_APIC_irq(irq);
1243 #ifdef CONFIG_PCI_MSI
1244 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1246 int irq = vector_to_irq(vector);
1248 return startup_edge_ioapic_irq(irq);
1251 static void ack_edge_ioapic_vector(unsigned int vector)
1253 int irq = vector_to_irq(vector);
1255 ack_edge_ioapic_irq(irq);
1258 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1260 int irq = vector_to_irq(vector);
1262 return startup_level_ioapic_irq (irq);
1265 static void mask_and_ack_level_ioapic_vector (unsigned int vector)
1267 int irq = vector_to_irq(vector);
1269 mask_and_ack_level_ioapic_irq(irq);
1272 static void end_level_ioapic_vector (unsigned int vector)
1274 int irq = vector_to_irq(vector);
1276 end_level_ioapic_irq(irq);
1279 static void mask_IO_APIC_vector (unsigned int vector)
1281 int irq = vector_to_irq(vector);
1283 mask_IO_APIC_irq(irq);
1286 static void unmask_IO_APIC_vector (unsigned int vector)
1288 int irq = vector_to_irq(vector);
1290 unmask_IO_APIC_irq(irq);
1293 static void set_ioapic_affinity_vector (unsigned int vector,
1294 cpumask_t cpu_mask)
1296 int irq = vector_to_irq(vector);
1298 set_ioapic_affinity_irq(irq, cpu_mask);
1300 #endif
1302 /*
1303 * Level and edge triggered IO-APIC interrupts need different handling,
1304 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1305 * handled with the level-triggered descriptor, but that one has slightly
1306 * more overhead. Level-triggered interrupts cannot be handled with the
1307 * edge-triggered handler, without risking IRQ storms and other ugly
1308 * races.
1309 */
1310 static struct hw_interrupt_type ioapic_edge_type = {
1311 .typename = "IO-APIC-edge",
1312 .startup = startup_edge_ioapic,
1313 .shutdown = shutdown_edge_ioapic,
1314 .enable = enable_edge_ioapic,
1315 .disable = disable_edge_ioapic,
1316 .ack = ack_edge_ioapic,
1317 .end = end_edge_ioapic,
1318 .set_affinity = set_ioapic_affinity,
1319 };
1321 static struct hw_interrupt_type ioapic_level_type = {
1322 .typename = "IO-APIC-level",
1323 .startup = startup_level_ioapic,
1324 .shutdown = shutdown_level_ioapic,
1325 .enable = enable_level_ioapic,
1326 .disable = disable_level_ioapic,
1327 .ack = mask_and_ack_level_ioapic,
1328 .end = end_level_ioapic,
1329 .set_affinity = set_ioapic_affinity,
1330 };
1332 static inline void init_IO_APIC_traps(void)
1334 int irq;
1336 /*
1337 * NOTE! The local APIC isn't very good at handling
1338 * multiple interrupts at the same interrupt level.
1339 * As the interrupt level is determined by taking the
1340 * vector number and shifting that right by 4, we
1341 * want to spread these out a bit so that they don't
1342 * all fall in the same interrupt level.
1344 * Also, we've got to be careful not to trash gate
1345 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1346 */
1347 for (irq = 0; irq < NR_IRQS ; irq++) {
1348 int tmp = irq;
1349 #if 0
1350 if (use_pci_vector()) {
1351 if (!platform_legacy_irq(tmp))
1352 if ((tmp = vector_to_irq(tmp)) == -1)
1353 continue;
1355 #endif
1356 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1357 /*
1358 * Hmm.. We don't have an entry for this,
1359 * so default to an old-fashioned 8259
1360 * interrupt if we can..
1361 */
1362 if (irq < 16)
1363 make_8259A_irq(irq);
1368 static void enable_lapic_irq (unsigned int irq)
1370 unsigned long v;
1372 v = apic_read(APIC_LVT0);
1373 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1376 static void disable_lapic_irq (unsigned int irq)
1378 unsigned long v;
1380 v = apic_read(APIC_LVT0);
1381 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1384 static void ack_lapic_irq (unsigned int irq)
1386 ack_APIC_irq();
1389 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1391 static struct hw_interrupt_type lapic_irq_type = {
1392 .typename = "local-APIC-edge",
1393 .startup = NULL, /* startup_irq() not used for IRQ0 */
1394 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1395 .enable = enable_lapic_irq,
1396 .disable = disable_lapic_irq,
1397 .ack = ack_lapic_irq,
1398 .end = end_lapic_irq
1399 };
1401 /*
1402 * This looks a bit hackish but it's about the only one way of sending
1403 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1404 * not support the ExtINT mode, unfortunately. We need to send these
1405 * cycles as some i82489DX-based boards have glue logic that keeps the
1406 * 8259A interrupt line asserted until INTA. --macro
1407 */
1408 static inline void unlock_ExtINT_logic(void)
1410 int pin, i;
1411 struct IO_APIC_route_entry entry0, entry1;
1412 unsigned char save_control, save_freq_select;
1413 unsigned long flags;
1415 pin = find_isa_irq_pin(8, mp_INT);
1416 if (pin == -1)
1417 return;
1419 spin_lock_irqsave(&ioapic_lock, flags);
1420 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1421 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1422 spin_unlock_irqrestore(&ioapic_lock, flags);
1423 clear_IO_APIC_pin(0, pin);
1425 memset(&entry1, 0, sizeof(entry1));
1427 entry1.dest_mode = 0; /* physical delivery */
1428 entry1.mask = 0; /* unmask IRQ now */
1429 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1430 entry1.delivery_mode = dest_ExtINT;
1431 entry1.polarity = entry0.polarity;
1432 entry1.trigger = 0;
1433 entry1.vector = 0;
1435 spin_lock_irqsave(&ioapic_lock, flags);
1436 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1437 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1438 spin_unlock_irqrestore(&ioapic_lock, flags);
1440 save_control = CMOS_READ(RTC_CONTROL);
1441 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1442 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1443 RTC_FREQ_SELECT);
1444 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1446 i = 100;
1447 while (i-- > 0) {
1448 mdelay(10);
1449 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1450 i -= 10;
1453 CMOS_WRITE(save_control, RTC_CONTROL);
1454 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1455 clear_IO_APIC_pin(0, pin);
1457 spin_lock_irqsave(&ioapic_lock, flags);
1458 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1459 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1460 spin_unlock_irqrestore(&ioapic_lock, flags);
1463 /*
1464 * This code may look a bit paranoid, but it's supposed to cooperate with
1465 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1466 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1467 * fanatically on his truly buggy board.
1468 */
1469 static inline void check_timer(void)
1471 int pin1, pin2;
1472 int vector;
1474 /*
1475 * get/set the timer IRQ vector:
1476 */
1477 disable_8259A_irq(0);
1478 vector = assign_irq_vector(0);
1480 irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
1481 irq_desc[IO_APIC_VECTOR(0)].depth = 0;
1482 irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
1484 /*
1485 * Subtle, code in do_timer_interrupt() expects an AEOI
1486 * mode for the 8259A whenever interrupts are routed
1487 * through I/O APICs. Also IRQ0 has to be enabled in
1488 * the 8259A which implies the virtual wire has to be
1489 * disabled in the local APIC.
1490 */
1491 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1492 init_8259A(1);
1493 timer_ack = 1;
1494 enable_8259A_irq(0);
1496 pin1 = find_isa_irq_pin(0, mp_INT);
1497 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1499 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1501 if (pin1 != -1) {
1502 /*
1503 * Ok, does IRQ0 through the IOAPIC work?
1504 */
1505 unmask_IO_APIC_irq(0);
1506 if (timer_irq_works()) {
1507 return;
1509 clear_IO_APIC_pin(0, pin1);
1510 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1513 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1514 if (pin2 != -1) {
1515 printk("\n..... (found pin %d) ...", pin2);
1516 /*
1517 * legacy devices should be connected to IO APIC #0
1518 */
1519 setup_ExtINT_IRQ0_pin(pin2, vector);
1520 if (timer_irq_works()) {
1521 printk("works.\n");
1522 if (pin1 != -1)
1523 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1524 else
1525 add_pin_to_irq(0, 0, pin2);
1526 return;
1528 /*
1529 * Cleanup, just in case ...
1530 */
1531 clear_IO_APIC_pin(0, pin2);
1533 printk(" failed.\n");
1535 if (nmi_watchdog == NMI_IO_APIC) {
1536 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1537 nmi_watchdog = 0;
1540 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1542 disable_8259A_irq(0);
1543 irq_desc[vector].handler = &lapic_irq_type;
1544 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1545 enable_8259A_irq(0);
1547 if (timer_irq_works()) {
1548 printk(" works.\n");
1549 return;
1551 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1552 printk(" failed.\n");
1554 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1556 timer_ack = 0;
1557 init_8259A(0);
1558 make_8259A_irq(0);
1559 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1561 unlock_ExtINT_logic();
1563 if (timer_irq_works()) {
1564 printk(" works.\n");
1565 return;
1567 printk(" failed :(.\n");
1568 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1569 "report. Then try booting with the 'noapic' option");
1572 #define NR_IOAPIC_BIOSIDS 256
1573 static u8 ioapic_biosid_to_apic_enum[NR_IOAPIC_BIOSIDS];
1574 static void store_ioapic_biosid_mapping(void)
1576 u8 apic;
1577 memset(ioapic_biosid_to_apic_enum, ~0, NR_IOAPIC_BIOSIDS);
1578 for ( apic = 0; apic < nr_ioapics; apic++ )
1579 ioapic_biosid_to_apic_enum[mp_ioapics[apic].mpc_apicid] = apic;
1582 /*
1584 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1585 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1586 * Linux doesn't really care, as it's not actually used
1587 * for any interrupt handling anyway.
1588 */
1589 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1591 void __init setup_IO_APIC(void)
1593 store_ioapic_biosid_mapping();
1595 enable_IO_APIC();
1597 if (acpi_ioapic)
1598 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1599 else
1600 io_apic_irqs = ~PIC_IRQS;
1602 printk("ENABLING IO-APIC IRQs\n");
1604 /*
1605 * Set up IO-APIC IRQ routing.
1606 */
1607 if (!acpi_ioapic)
1608 setup_ioapic_ids_from_mpc();
1609 sync_Arb_IDs();
1610 setup_IO_APIC_irqs();
1611 init_IO_APIC_traps();
1612 check_timer();
1613 print_IO_APIC();
1616 /* --------------------------------------------------------------------------
1617 ACPI-based IOAPIC Configuration
1618 -------------------------------------------------------------------------- */
1620 #ifdef CONFIG_ACPI_BOOT
1622 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1624 union IO_APIC_reg_00 reg_00;
1625 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
1626 physid_mask_t tmp;
1627 unsigned long flags;
1628 int i = 0;
1630 /*
1631 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1632 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1633 * supports up to 16 on one shared APIC bus.
1635 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1636 * advantage of new APIC bus architecture.
1637 */
1639 if (physids_empty(apic_id_map))
1640 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
1642 spin_lock_irqsave(&ioapic_lock, flags);
1643 reg_00.raw = io_apic_read(ioapic, 0);
1644 spin_unlock_irqrestore(&ioapic_lock, flags);
1646 if (apic_id >= get_physical_broadcast()) {
1647 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1648 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1649 apic_id = reg_00.bits.ID;
1652 /*
1653 * Every APIC in a system must have a unique ID or we get lots of nice
1654 * 'stuck on smp_invalidate_needed IPI wait' messages.
1655 */
1656 if (check_apicid_used(apic_id_map, apic_id)) {
1658 for (i = 0; i < get_physical_broadcast(); i++) {
1659 if (!check_apicid_used(apic_id_map, i))
1660 break;
1663 if (i == get_physical_broadcast())
1664 panic("Max apic_id exceeded!\n");
1666 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1667 "trying %d\n", ioapic, apic_id, i);
1669 apic_id = i;
1672 tmp = apicid_to_cpu_present(apic_id);
1673 physids_or(apic_id_map, apic_id_map, tmp);
1675 if (reg_00.bits.ID != apic_id) {
1676 reg_00.bits.ID = apic_id;
1678 spin_lock_irqsave(&ioapic_lock, flags);
1679 io_apic_write(ioapic, 0, reg_00.raw);
1680 reg_00.raw = io_apic_read(ioapic, 0);
1681 spin_unlock_irqrestore(&ioapic_lock, flags);
1683 /* Sanity check */
1684 if (reg_00.bits.ID != apic_id)
1685 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1688 apic_printk(APIC_VERBOSE, KERN_INFO
1689 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1691 return apic_id;
1695 int __init io_apic_get_version (int ioapic)
1697 union IO_APIC_reg_01 reg_01;
1698 unsigned long flags;
1700 spin_lock_irqsave(&ioapic_lock, flags);
1701 reg_01.raw = io_apic_read(ioapic, 1);
1702 spin_unlock_irqrestore(&ioapic_lock, flags);
1704 return reg_01.bits.version;
1708 int __init io_apic_get_redir_entries (int ioapic)
1710 union IO_APIC_reg_01 reg_01;
1711 unsigned long flags;
1713 spin_lock_irqsave(&ioapic_lock, flags);
1714 reg_01.raw = io_apic_read(ioapic, 1);
1715 spin_unlock_irqrestore(&ioapic_lock, flags);
1717 return reg_01.bits.entries;
1721 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1723 struct IO_APIC_route_entry entry;
1724 unsigned long flags;
1726 if (!IO_APIC_IRQ(irq)) {
1727 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1728 ioapic);
1729 return -EINVAL;
1732 /*
1733 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1734 * Note that we mask (disable) IRQs now -- these get enabled when the
1735 * corresponding device driver registers for this IRQ.
1736 */
1738 memset(&entry,0,sizeof(entry));
1740 entry.delivery_mode = INT_DELIVERY_MODE;
1741 entry.dest_mode = INT_DEST_MODE;
1742 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1743 entry.trigger = edge_level;
1744 entry.polarity = active_high_low;
1745 entry.mask = 1;
1747 /*
1748 * IRQs < 16 are already in the irq_2_pin[] map
1749 */
1750 if (irq >= 16)
1751 add_pin_to_irq(irq, ioapic, pin);
1753 entry.vector = assign_irq_vector(irq);
1755 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
1756 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
1757 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1758 edge_level, active_high_low);
1760 ioapic_register_intr(irq, entry.vector, edge_level);
1762 if (!ioapic && (irq < 16))
1763 disable_8259A_irq(irq);
1765 spin_lock_irqsave(&ioapic_lock, flags);
1766 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1767 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1768 spin_unlock_irqrestore(&ioapic_lock, flags);
1770 return 0;
1773 #endif /*CONFIG_ACPI_BOOT*/
1776 int ioapic_guest_read(int apicid, int address, u32 *pval)
1778 u32 val;
1779 int apicenum;
1780 union IO_APIC_reg_00 reg_00;
1781 unsigned long flags;
1783 if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
1784 ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
1785 return -EINVAL;
1787 spin_lock_irqsave(&ioapic_lock, flags);
1788 val = io_apic_read(apicenum, address);
1789 spin_unlock_irqrestore(&ioapic_lock, flags);
1791 /* Rewrite APIC ID to what the BIOS originally specified. */
1792 if ( address == 0 )
1794 reg_00.raw = val;
1795 reg_00.bits.ID = apicid;
1796 val = reg_00.raw;
1799 *pval = val;
1800 return 0;
1803 int ioapic_guest_write(int apicid, int address, u32 val)
1805 int apicenum, pin, irq;
1806 struct IO_APIC_route_entry rte = { 0 };
1807 struct irq_pin_list *entry;
1808 unsigned long flags;
1810 if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
1811 ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
1812 return -EINVAL;
1814 /* Only write to the first half of a route entry. */
1815 if ( (address < 0x10) || (address & 1) )
1816 return 0;
1818 pin = (address - 0x10) >> 1;
1820 rte.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1821 *(int *)&rte = val;
1823 if ( rte.vector >= FIRST_DEVICE_VECTOR )
1825 /* Is there a valid irq mapped to this vector? */
1826 irq = vector_irq[rte.vector];
1827 if ( !IO_APIC_IRQ(irq) )
1828 return 0;
1830 /* Set the correct irq-handling type. */
1831 irq_desc[IO_APIC_VECTOR(irq)].handler = rte.trigger ?
1832 &ioapic_level_type: &ioapic_edge_type;
1834 /* Record the pin<->irq mapping. */
1835 for ( entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next] )
1837 if ( (entry->apic == apicenum) && (entry->pin == pin) )
1838 break;
1839 if ( !entry->next )
1841 add_pin_to_irq(irq, apicenum, pin);
1842 break;
1847 spin_lock_irqsave(&ioapic_lock, flags);
1848 io_apic_write(apicenum, 0x10 + 2 * pin, *(((int *)&rte) + 0));
1849 io_apic_write(apicenum, 0x11 + 2 * pin, *(((int *)&rte) + 1));
1850 spin_unlock_irqrestore(&ioapic_lock, flags);
1852 return 0;