ia64/xen-unstable

view xen/arch/x86/i8259.c @ 5374:22e42640bcff

bitkeeper revision 1.1691.1.8 (42a6fb21d3oJwpLmOxa2jKHRJ-8fJg)

First phase of removing IRQ numbers from Xen (transitioning to
IRQ addressing by 'legacy ISA IRQ', 'interrupt vector', and
'I/O APIC address + pin' as appropriate). Overall plan is to move
I/O APIC parsing and setup out of Xen (so we start DOM0 in virtual wire
mode).
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Jun 08 14:05:21 2005 +0000 (2005-06-08)
parents 5b1f038d3d65
children 0be846d7d261
line source
1 /******************************************************************************
2 * i8259.c
3 *
4 * Well, this is required for SMP systems as well, as it build interrupt
5 * tables for IO APICS as well as uniprocessor 8259-alikes.
6 */
8 #include <xen/config.h>
9 #include <xen/init.h>
10 #include <xen/types.h>
11 #include <asm/regs.h>
12 #include <xen/errno.h>
13 #include <xen/sched.h>
14 #include <xen/irq.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
17 #include <asm/io.h>
18 #include <asm/desc.h>
19 #include <asm/bitops.h>
20 #include <xen/delay.h>
21 #include <asm/apic.h>
24 /*
25 * Common place to define all x86 IRQ vectors
26 *
27 * This builds up the IRQ handler stubs using some ugly macros in irq.h
28 *
29 * These macros create the low-level assembly IRQ routines that save
30 * register context and call do_IRQ(). do_IRQ() then does all the
31 * operations that are needed to keep the AT (or SMP IOAPIC)
32 * interrupt-controller happy.
33 */
35 BUILD_COMMON_IRQ()
37 #define BI(x,y) \
38 BUILD_IRQ(x##y)
40 #define BUILD_16_IRQS(x) \
41 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
42 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
43 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
44 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
46 BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
47 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
48 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
49 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
51 #undef BUILD_16_IRQS
52 #undef BI
55 /*
56 * The following vectors are part of the Linux architecture, there
57 * is no hardware IRQ pin equivalent for them, they are triggered
58 * through the ICC by us (IPIs)
59 */
60 #ifdef CONFIG_SMP
61 BUILD_SMP_INTERRUPT(event_check_interrupt,EVENT_CHECK_VECTOR)
62 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
63 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
64 #endif
66 /*
67 * Every pentium local APIC has two 'local interrupts', with a
68 * soft-definable vector attached to both interrupts, one of
69 * which is a timer interrupt, the other one is error counter
70 * overflow. Linux uses the local APIC timer interrupt to get
71 * a much simpler SMP time architecture:
72 */
73 BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
74 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
75 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
77 #define IRQ(x,y) \
78 IRQ##x##y##_interrupt
80 #define IRQLIST_16(x) \
81 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
82 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
83 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
84 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
86 static void (*interrupt[])(void) = {
87 IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
88 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
89 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
90 IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
91 };
93 #undef IRQ
94 #undef IRQLIST_16
96 /*
97 * This is the 'legacy' 8259A Programmable Interrupt Controller,
98 * present in the majority of PC/AT boxes.
99 * plus some generic x86 specific things if generic specifics makes
100 * any sense at all.
101 * this file should become arch/i386/kernel/irq.c when the old irq.c
102 * moves to arch independent land
103 */
105 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
107 static void end_8259A_irq (unsigned int irq)
108 {
109 if (!(irq_desc[irq_to_vector(irq)].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
110 enable_8259A_irq(irq);
111 }
113 #define shutdown_8259A_irq disable_8259A_irq
115 void mask_and_ack_8259A(unsigned int);
117 static unsigned int startup_8259A_irq(unsigned int irq)
118 {
119 enable_8259A_irq(irq);
120 return 0; /* never anything pending */
121 }
123 static struct hw_interrupt_type i8259A_irq_type = {
124 "XT-PIC",
125 startup_8259A_irq,
126 shutdown_8259A_irq,
127 enable_8259A_irq,
128 disable_8259A_irq,
129 mask_and_ack_8259A,
130 end_8259A_irq,
131 NULL
132 };
134 /*
135 * 8259A PIC functions to handle ISA devices:
136 */
138 /*
139 * This contains the irq mask for both 8259A irq controllers,
140 */
141 static unsigned int cached_irq_mask = 0xffff;
143 #define __byte(x,y) (((unsigned char *)&(y))[x])
144 #define cached_21 (__byte(0,cached_irq_mask))
145 #define cached_A1 (__byte(1,cached_irq_mask))
147 /*
148 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
149 * boards the timer interrupt is not really connected to any IO-APIC pin,
150 * it's fed to the master 8259A's IR0 line only.
151 *
152 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
153 * this 'mixed mode' IRQ handling costs nothing because it's only used
154 * at IRQ setup time.
155 */
156 unsigned long io_apic_irqs;
158 void disable_8259A_irq(unsigned int irq)
159 {
160 unsigned int mask = 1 << irq;
161 unsigned long flags;
163 spin_lock_irqsave(&i8259A_lock, flags);
164 cached_irq_mask |= mask;
165 if (irq & 8)
166 outb(cached_A1,0xA1);
167 else
168 outb(cached_21,0x21);
169 spin_unlock_irqrestore(&i8259A_lock, flags);
170 }
172 void enable_8259A_irq(unsigned int irq)
173 {
174 unsigned int mask = ~(1 << irq);
175 unsigned long flags;
177 spin_lock_irqsave(&i8259A_lock, flags);
178 cached_irq_mask &= mask;
179 if (irq & 8)
180 outb(cached_A1,0xA1);
181 else
182 outb(cached_21,0x21);
183 spin_unlock_irqrestore(&i8259A_lock, flags);
184 }
186 int i8259A_irq_pending(unsigned int irq)
187 {
188 unsigned int mask = 1<<irq;
189 unsigned long flags;
190 int ret;
192 spin_lock_irqsave(&i8259A_lock, flags);
193 if (irq < 8)
194 ret = inb(0x20) & mask;
195 else
196 ret = inb(0xA0) & (mask >> 8);
197 spin_unlock_irqrestore(&i8259A_lock, flags);
199 return ret;
200 }
202 void make_8259A_irq(unsigned int irq)
203 {
204 disable_irq_nosync(irq);
205 io_apic_irqs &= ~(1<<irq);
206 irq_desc[irq_to_vector(irq)].handler = &i8259A_irq_type;
207 enable_irq(irq);
208 }
210 /*
211 * This function assumes to be called rarely. Switching between
212 * 8259A registers is slow.
213 * This has to be protected by the irq controller spinlock
214 * before being called.
215 */
216 static inline int i8259A_irq_real(unsigned int irq)
217 {
218 int value;
219 int irqmask = 1<<irq;
221 if (irq < 8) {
222 outb(0x0B,0x20); /* ISR register */
223 value = inb(0x20) & irqmask;
224 outb(0x0A,0x20); /* back to the IRR register */
225 return value;
226 }
227 outb(0x0B,0xA0); /* ISR register */
228 value = inb(0xA0) & (irqmask >> 8);
229 outb(0x0A,0xA0); /* back to the IRR register */
230 return value;
231 }
233 /*
234 * Careful! The 8259A is a fragile beast, it pretty
235 * much _has_ to be done exactly like this (mask it
236 * first, _then_ send the EOI, and the order of EOI
237 * to the two 8259s is important!
238 */
239 void mask_and_ack_8259A(unsigned int irq)
240 {
241 unsigned int irqmask = 1 << irq;
242 unsigned long flags;
244 spin_lock_irqsave(&i8259A_lock, flags);
245 /*
246 * Lightweight spurious IRQ detection. We do not want
247 * to overdo spurious IRQ handling - it's usually a sign
248 * of hardware problems, so we only do the checks we can
249 * do without slowing down good hardware unnecesserily.
250 *
251 * Note that IRQ7 and IRQ15 (the two spurious IRQs
252 * usually resulting from the 8259A-1|2 PICs) occur
253 * even if the IRQ is masked in the 8259A. Thus we
254 * can check spurious 8259A IRQs without doing the
255 * quite slow i8259A_irq_real() call for every IRQ.
256 * This does not cover 100% of spurious interrupts,
257 * but should be enough to warn the user that there
258 * is something bad going on ...
259 */
260 if (cached_irq_mask & irqmask)
261 goto spurious_8259A_irq;
262 cached_irq_mask |= irqmask;
264 handle_real_irq:
265 if (irq & 8) {
266 inb(0xA1); /* DUMMY - (do we need this?) */
267 outb(cached_A1,0xA1);
268 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
269 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
270 } else {
271 inb(0x21); /* DUMMY - (do we need this?) */
272 outb(cached_21,0x21);
273 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
274 }
275 spin_unlock_irqrestore(&i8259A_lock, flags);
276 return;
278 spurious_8259A_irq:
279 /*
280 * this is the slow path - should happen rarely.
281 */
282 if (i8259A_irq_real(irq))
283 /*
284 * oops, the IRQ _is_ in service according to the
285 * 8259A - not spurious, go handle it.
286 */
287 goto handle_real_irq;
289 {
290 static int spurious_irq_mask;
291 /*
292 * At this point we can be sure the IRQ is spurious,
293 * lets ACK and report it. [once per IRQ]
294 */
295 if (!(spurious_irq_mask & irqmask)) {
296 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
297 spurious_irq_mask |= irqmask;
298 }
299 atomic_inc(&irq_err_count);
300 /*
301 * Theoretically we do not have to handle this IRQ,
302 * but in Linux this does not cause problems and is
303 * simpler for us.
304 */
305 goto handle_real_irq;
306 }
307 }
309 void __init init_8259A(int auto_eoi)
310 {
311 unsigned long flags;
313 spin_lock_irqsave(&i8259A_lock, flags);
315 outb(0xff, 0x21); /* mask all of 8259A-1 */
316 outb(0xff, 0xA1); /* mask all of 8259A-2 */
318 /*
319 * outb_p - this has to work on a wide range of PC hardware.
320 */
321 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
322 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
323 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
324 if (auto_eoi)
325 outb_p(0x03, 0x21); /* master does Auto EOI */
326 else
327 outb_p(0x01, 0x21); /* master expects normal EOI */
329 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
330 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
331 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
332 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
333 is to be investigated) */
335 if (auto_eoi)
336 /*
337 * in AEOI mode we just have to mask the interrupt
338 * when acking.
339 */
340 i8259A_irq_type.ack = disable_8259A_irq;
341 else
342 i8259A_irq_type.ack = mask_and_ack_8259A;
344 udelay(100); /* wait for 8259A to initialize */
346 outb(cached_21, 0x21); /* restore master IRQ mask */
347 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
349 spin_unlock_irqrestore(&i8259A_lock, flags);
350 }
352 static struct irqaction cascade = { no_action, "cascade", NULL};
354 void __init init_IRQ(void)
355 {
356 int i;
358 init_bsp_APIC();
360 init_8259A(0);
362 for ( i = 0; i < NR_IRQS; i++ )
363 {
364 irq_desc[i].status = IRQ_DISABLED;
365 irq_desc[i].handler = &no_irq_type;
366 irq_desc[i].action = NULL;
367 irq_desc[i].depth = 1;
368 spin_lock_init(&irq_desc[i].lock);
369 set_intr_gate(i, interrupt[i]);
370 }
372 for ( i = 0; i < 16; i++ )
373 {
374 vector_irq[LEGACY_VECTOR(i)] = i;
375 irq_desc[LEGACY_VECTOR(i)].handler = &i8259A_irq_type;
376 }
378 /*
379 * IRQ0 must be given a fixed assignment and initialized,
380 * because it's used before the IO-APIC is set up.
381 */
382 irq_vector[0] = FIRST_DEVICE_VECTOR;
383 vector_irq[FIRST_DEVICE_VECTOR] = 0;
385 /* Various IPI functions. */
386 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
387 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
388 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
390 /* Self-generated IPI for local APIC timer. */
391 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
393 /* IPI vectors for APIC spurious and error interrupts. */
394 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
395 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
397 /* Set the clock to HZ Hz */
398 #define CLOCK_TICK_RATE 1193180 /* crystal freq (Hz) */
399 #define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ)
400 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
401 outb_p(LATCH & 0xff , 0x40); /* LSB */
402 outb(LATCH >> 8 , 0x40); /* MSB */
404 setup_irq(2, &cascade);
405 }