ia64/xen-unstable

view xen/include/asm-powerpc/cache.h @ 12930:1c996041fcde

[XEN][POWERPC] Add Function to completely flush the I-Cache for a processor
Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Jimi Xenidis <jimix@watson.ibm.com>
date Mon Oct 02 11:07:54 2006 -0400 (2006-10-02)
parents 2b8660a8a9bc
children
line source
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 *
16 * Copyright (C) IBM Corp. 2005
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
21 #ifndef __ASM_CACHE_H
22 #define __ASM_CACHE_H
24 #include <xen/config.h>
25 #include <asm/processor.h>
27 /* L1 cache line size */
28 #define L1_CACHE_SHIFT (CONFIG_L1_CACHE_SHIFT)
29 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
31 static __inline__ void dcbst(ulong line)
32 {
33 __asm__ __volatile__ ("dcbst 0, %0" : : "r"(line) : "memory");
34 }
36 static __inline__ void icbi(ulong line)
37 {
38 __asm__ __volatile__ ("icbi 0, %0" : : "r"(line) : "memory");
39 }
41 static __inline__ void synchronize_caches(ulong start, size_t len)
42 {
43 ulong addr;
45 for (addr = start; addr < start + len; addr += L1_CACHE_BYTES) {
46 dcbst(addr);
47 }
49 /* allow dcbsts to complete */
50 sync();
52 for (addr = start; addr < start + len; addr += L1_CACHE_BYTES) {
53 icbi(addr);
54 }
56 /* discard instructions partially decoded from old icache contents */
57 isync();
58 }
60 #define __read_mostly
62 struct cpu_caches {
63 u32 dsize; /* L1 d-cache size */
64 u32 dline_size; /* L1 d-cache line size */
65 u32 log_dline_size;
66 u32 dlines_per_page;
67 u32 isize; /* L1 i-cache size */
68 u32 iline_size; /* L1 i-cache line size */
69 u32 log_iline_size;
70 u32 ilines_per_page;
71 };
72 extern struct cpu_caches cpu_caches;
73 extern void cpu_flush_icache(void);
74 #endif