ia64/xen-unstable

view xen/include/asm-ia64/vmx_vcpu.h @ 9164:1abf3783975d

[IA64] Merge guest TR emulation

This patch is intended to merge guest TR emulation both on VTIdomain
and para-domain.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Fri Mar 10 08:52:12 2006 -0700 (2006-03-10)
parents a693ccb4d581
children 7c7bcf173f8b
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * vmx_vcpu.h:
4 * Copyright (c) 2005, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
20 * Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
21 */
23 #ifndef _XEN_IA64_VMX_VCPU_H
24 #define _XEN_IA64_VMX_VCPU_H
27 #include <xen/sched.h>
28 #include <asm/ia64_int.h>
29 #include <asm/vmx_vpd.h>
30 #include <asm/ptrace.h>
31 #include <asm/regs.h>
32 #include <asm/regionreg.h>
33 #include <asm/types.h>
34 #include <asm/vcpu.h>
36 #define VRN_SHIFT 61
37 #define VRN0 0x0UL
38 #define VRN1 0x1UL
39 #define VRN2 0x2UL
40 #define VRN3 0x3UL
41 #define VRN4 0x4UL
42 #define VRN5 0x5UL
43 #define VRN6 0x6UL
44 #define VRN7 0x7UL
45 // for vlsapic
46 #define VLSAPIC_INSVC(vcpu, i) ((vcpu)->arch.insvc[i])
47 //#define VMX_VPD(x,y) ((x)->arch.arch_vmx.vpd->y)
49 #define VMX(x,y) ((x)->arch.arch_vmx.y)
52 #define VMM_RR_SHIFT 20
53 #define VMM_RR_MASK ((1UL<<VMM_RR_SHIFT)-1)
55 extern u64 indirect_reg_igfld_MASK ( int type, int index, u64 value);
56 extern u64 cr_igfld_mask (int index, u64 value);
57 extern int check_indirect_reg_rsv_fields ( int type, int index, u64 value );
58 extern u64 set_isr_ei_ni (VCPU *vcpu);
59 extern u64 set_isr_for_na_inst(VCPU *vcpu, int op);
62 /* next all for VTI domain APIs definition */
63 extern void vmx_vcpu_set_psr(VCPU *vcpu, unsigned long value);
64 extern UINT64 vmx_vcpu_sync_mpsr(UINT64 mipsr, UINT64 value);
65 extern void vmx_vcpu_set_psr_sync_mpsr(VCPU * vcpu, UINT64 value);
66 extern IA64FAULT vmx_vcpu_cover(VCPU *vcpu);
67 extern thash_cb_t *vmx_vcpu_get_vtlb(VCPU *vcpu);
68 extern thash_cb_t *vmx_vcpu_get_vhpt(VCPU *vcpu);
69 extern IA64FAULT vmx_vcpu_set_rr(VCPU *vcpu, UINT64 reg, UINT64 val);
70 extern IA64FAULT vmx_vcpu_get_pkr(VCPU *vcpu, UINT64 reg, UINT64 *pval);
71 IA64FAULT vmx_vcpu_set_pkr(VCPU *vcpu, UINT64 reg, UINT64 val);
72 extern IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa);
73 extern IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa);
74 extern IA64FAULT vmx_vcpu_itr_i(VCPU *vcpu, UINT64 slot, UINT64 pte, UINT64 itir, UINT64 ifa);
75 extern IA64FAULT vmx_vcpu_itr_d(VCPU *vcpu, UINT64 slot, UINT64 pte, UINT64 itir, UINT64 ifa);
76 extern IA64FAULT vmx_vcpu_ptr_d(VCPU *vcpu,UINT64 vadr,UINT64 ps);
77 extern IA64FAULT vmx_vcpu_ptr_i(VCPU *vcpu,UINT64 vadr,UINT64 ps);
78 extern IA64FAULT vmx_vcpu_ptc_l(VCPU *vcpu, UINT64 vadr, UINT64 ps);
79 extern IA64FAULT vmx_vcpu_ptc_e(VCPU *vcpu, UINT64 vadr);
80 extern IA64FAULT vmx_vcpu_ptc_g(VCPU *vcpu, UINT64 vadr, UINT64 ps);
81 extern IA64FAULT vmx_vcpu_ptc_ga(VCPU *vcpu,UINT64 vadr,UINT64 ps);
82 extern IA64FAULT vmx_vcpu_thash(VCPU *vcpu, UINT64 vadr, UINT64 *pval);
83 extern u64 vmx_vcpu_get_itir_on_fault(VCPU *vcpu, u64 ifa);
84 extern IA64FAULT vmx_vcpu_ttag(VCPU *vcpu, UINT64 vadr, UINT64 *pval);
85 extern IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, UINT64 vadr, UINT64 *padr);
86 extern IA64FAULT vmx_vcpu_tak(VCPU *vcpu, UINT64 vadr, UINT64 *key);
87 extern IA64FAULT vmx_vcpu_rfi(VCPU *vcpu);
88 extern UINT64 vmx_vcpu_get_psr(VCPU *vcpu);
89 extern IA64FAULT vmx_vcpu_get_bgr(VCPU *vcpu, unsigned int reg, UINT64 *val);
90 extern IA64FAULT vmx_vcpu_set_bgr(VCPU *vcpu, unsigned int reg, u64 val,int nat);
91 #if 0
92 extern IA64FAULT vmx_vcpu_get_gr(VCPU *vcpu, unsigned reg, UINT64 * val);
93 extern IA64FAULT vmx_vcpu_set_gr(VCPU *vcpu, unsigned reg, u64 value, int nat);
94 #endif
95 extern IA64FAULT vmx_vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm24);
96 extern IA64FAULT vmx_vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24);
97 extern IA64FAULT vmx_vcpu_set_psr_l(VCPU *vcpu, UINT64 val);
98 extern void vtm_init(VCPU *vcpu);
99 extern uint64_t vtm_get_itc(VCPU *vcpu);
100 extern void vtm_set_itc(VCPU *vcpu, uint64_t new_itc);
101 extern void vtm_set_itv(VCPU *vcpu, uint64_t val);
102 extern void vtm_set_itm(VCPU *vcpu, uint64_t val);
103 extern void vtm_interruption_update(VCPU *vcpu, vtime_t* vtm);
104 //extern void vtm_domain_out(VCPU *vcpu);
105 //extern void vtm_domain_in(VCPU *vcpu);
106 extern void vlsapic_reset(VCPU *vcpu);
107 extern int vmx_check_pending_irq(VCPU *vcpu);
108 extern void guest_write_eoi(VCPU *vcpu);
109 extern uint64_t guest_read_vivr(VCPU *vcpu);
110 extern void vmx_inject_vhpi(VCPU *vcpu, u8 vec);
111 extern int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector);
112 extern struct virtual_platform_def *vmx_vcpu_get_plat(VCPU *vcpu);
113 extern void memread_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
114 extern void memread_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s);
115 extern void memwrite_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s);
116 extern void memwrite_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
117 extern void vcpu_load_kernel_regs(VCPU *vcpu);
118 extern IA64FAULT vmx_vcpu_increment_iip(VCPU *vcpu);
119 extern void vmx_switch_rr7(unsigned long ,shared_info_t*,void *,void *,void *);
121 extern void dtlb_fault (VCPU *vcpu, u64 vadr);
122 extern void nested_dtlb (VCPU *vcpu);
123 extern void alt_dtlb (VCPU *vcpu, u64 vadr);
124 extern void dvhpt_fault (VCPU *vcpu, u64 vadr);
125 extern void dnat_page_consumption (VCPU *vcpu, uint64_t vadr);
126 extern void page_not_present(VCPU *vcpu, u64 vadr);
128 /**************************************************************************
129 VCPU control register access routines
130 **************************************************************************/
132 static inline
133 IA64FAULT vmx_vcpu_get_dcr(VCPU *vcpu, UINT64 *pval)
134 {
135 *pval = VCPU(vcpu,dcr);
136 return (IA64_NO_FAULT);
137 }
139 static inline
140 IA64FAULT vmx_vcpu_get_itm(VCPU *vcpu, UINT64 *pval)
141 {
142 *pval = VCPU(vcpu,itm);
143 return (IA64_NO_FAULT);
144 }
146 static inline
147 IA64FAULT vmx_vcpu_get_iva(VCPU *vcpu, UINT64 *pval)
148 {
149 *pval = VCPU(vcpu,iva);
150 return (IA64_NO_FAULT);
151 }
152 static inline
153 IA64FAULT vmx_vcpu_get_pta(VCPU *vcpu, UINT64 *pval)
154 {
155 *pval = VCPU(vcpu,pta);
156 return (IA64_NO_FAULT);
157 }
159 static inline
160 IA64FAULT vmx_vcpu_get_lid(VCPU *vcpu, UINT64 *pval)
161 {
162 *pval = VCPU(vcpu,lid);
163 return (IA64_NO_FAULT);
164 }
165 static inline
166 IA64FAULT vmx_vcpu_get_ivr(VCPU *vcpu, UINT64 *pval)
167 {
168 *pval = guest_read_vivr(vcpu);
169 return (IA64_NO_FAULT);
170 }
171 static inline
172 IA64FAULT vmx_vcpu_get_tpr(VCPU *vcpu, UINT64 *pval)
173 {
174 *pval = VCPU(vcpu,tpr);
175 return (IA64_NO_FAULT);
176 }
177 static inline
178 IA64FAULT vmx_vcpu_get_eoi(VCPU *vcpu, UINT64 *pval)
179 {
180 *pval = 0L; // reads of eoi always return 0
181 return (IA64_NO_FAULT);
182 }
183 static inline
184 IA64FAULT vmx_vcpu_get_irr0(VCPU *vcpu, UINT64 *pval)
185 {
186 *pval = VCPU(vcpu,irr[0]);
187 return (IA64_NO_FAULT);
188 }
189 static inline
190 IA64FAULT vmx_vcpu_get_irr1(VCPU *vcpu, UINT64 *pval)
191 {
192 *pval = VCPU(vcpu,irr[1]);
193 return (IA64_NO_FAULT);
194 }
195 static inline
196 IA64FAULT vmx_vcpu_get_irr2(VCPU *vcpu, UINT64 *pval)
197 {
198 *pval = VCPU(vcpu,irr[2]);
199 return (IA64_NO_FAULT);
200 }
201 static inline
202 IA64FAULT vmx_vcpu_get_irr3(VCPU *vcpu, UINT64 *pval)
203 {
204 *pval = VCPU(vcpu,irr[3]);
205 return (IA64_NO_FAULT);
206 }
207 static inline
208 IA64FAULT vmx_vcpu_get_itv(VCPU *vcpu, UINT64 *pval)
209 {
210 *pval = VCPU(vcpu,itv);
211 return (IA64_NO_FAULT);
212 }
213 static inline
214 IA64FAULT vmx_vcpu_get_pmv(VCPU *vcpu, UINT64 *pval)
215 {
216 *pval = VCPU(vcpu,pmv);
217 return (IA64_NO_FAULT);
218 }
219 static inline
220 IA64FAULT vmx_vcpu_get_cmcv(VCPU *vcpu, UINT64 *pval)
221 {
222 *pval = VCPU(vcpu,cmcv);
223 return (IA64_NO_FAULT);
224 }
225 static inline
226 IA64FAULT vmx_vcpu_get_lrr0(VCPU *vcpu, UINT64 *pval)
227 {
228 *pval = VCPU(vcpu,lrr0);
229 return (IA64_NO_FAULT);
230 }
231 static inline
232 IA64FAULT vmx_vcpu_get_lrr1(VCPU *vcpu, UINT64 *pval)
233 { *pval = VCPU(vcpu,lrr1);
234 return (IA64_NO_FAULT);
235 }
236 static inline
237 IA64FAULT
238 vmx_vcpu_set_dcr(VCPU *vcpu, u64 val)
239 {
240 u64 mdcr, mask;
241 VCPU(vcpu,dcr)=val;
242 /* All vDCR bits will go to mDCR, except for be/pp bit */
243 mdcr = ia64_get_dcr();
244 mask = IA64_DCR_BE | IA64_DCR_PP;
245 mdcr = ( mdcr & mask ) | ( val & (~mask) );
246 ia64_set_dcr( mdcr);
248 return IA64_NO_FAULT;
249 }
251 static inline
252 IA64FAULT
253 vmx_vcpu_set_itm(VCPU *vcpu, u64 val)
254 {
255 vtm_set_itm(vcpu, val);
256 return IA64_NO_FAULT;
257 }
258 static inline
259 IA64FAULT
260 vmx_vcpu_set_iva(VCPU *vcpu, u64 val)
261 {
262 VCPU(vcpu,iva)=val;
263 return IA64_NO_FAULT;
264 }
266 static inline
267 IA64FAULT
268 vmx_vcpu_set_pta(VCPU *vcpu, u64 val)
269 {
270 VCPU(vcpu,pta)=val;
271 return IA64_NO_FAULT;
272 }
274 static inline
275 IA64FAULT
276 vmx_vcpu_set_lid(VCPU *vcpu, u64 val)
277 {
278 VCPU(vcpu,lid)=val;
279 return IA64_NO_FAULT;
280 }
281 extern IA64FAULT vmx_vcpu_set_tpr(VCPU *vcpu, u64 val);
283 static inline
284 IA64FAULT
285 vmx_vcpu_set_eoi(VCPU *vcpu, u64 val)
286 {
287 guest_write_eoi(vcpu);
288 return IA64_NO_FAULT;
289 }
291 static inline
292 IA64FAULT
293 vmx_vcpu_set_itv(VCPU *vcpu, u64 val)
294 {
296 vtm_set_itv(vcpu, val);
297 return IA64_NO_FAULT;
298 }
299 static inline
300 IA64FAULT
301 vmx_vcpu_set_pmv(VCPU *vcpu, u64 val)
302 {
303 VCPU(vcpu,pmv)=val;
304 return IA64_NO_FAULT;
305 }
306 static inline
307 IA64FAULT
308 vmx_vcpu_set_cmcv(VCPU *vcpu, u64 val)
309 {
310 VCPU(vcpu,cmcv)=val;
311 return IA64_NO_FAULT;
312 }
313 static inline
314 IA64FAULT
315 vmx_vcpu_set_lrr0(VCPU *vcpu, u64 val)
316 {
317 VCPU(vcpu,lrr0)=val;
318 return IA64_NO_FAULT;
319 }
320 static inline
321 IA64FAULT
322 vmx_vcpu_set_lrr1(VCPU *vcpu, u64 val)
323 {
324 VCPU(vcpu,lrr1)=val;
325 return IA64_NO_FAULT;
326 }
331 /**************************************************************************
332 VCPU privileged application register access routines
333 **************************************************************************/
334 static inline
335 IA64FAULT vmx_vcpu_set_itc(VCPU *vcpu, UINT64 val)
336 {
337 vtm_set_itc(vcpu, val);
338 return IA64_NO_FAULT;
339 }
340 static inline
341 IA64FAULT vmx_vcpu_get_itc(VCPU *vcpu,UINT64 *val)
342 {
343 *val = vtm_get_itc(vcpu);
344 return IA64_NO_FAULT;
345 }
346 /*
347 static inline
348 IA64FAULT vmx_vcpu_get_rr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
349 {
350 *pval = VMX(vcpu,vrr[reg>>61]);
351 return (IA64_NO_FAULT);
352 }
353 */
354 /**************************************************************************
355 VCPU debug breakpoint register access routines
356 **************************************************************************/
358 static inline
359 IA64FAULT vmx_vcpu_get_cpuid(VCPU *vcpu, UINT64 reg, UINT64 *pval)
360 {
361 // TODO: unimplemented DBRs return a reserved register fault
362 // TODO: Should set Logical CPU state, not just physical
363 if(reg > 4){
364 panic("there are only five cpuid registers");
365 }
366 *pval=VCPU(vcpu,vcpuid[reg]);
367 return (IA64_NO_FAULT);
368 }
371 static inline
372 IA64FAULT vmx_vcpu_set_dbr(VCPU *vcpu, UINT64 reg, UINT64 val)
373 {
374 // TODO: unimplemented DBRs return a reserved register fault
375 // TODO: Should set Logical CPU state, not just physical
376 ia64_set_dbr(reg,val);
377 return (IA64_NO_FAULT);
378 }
379 static inline
380 IA64FAULT vmx_vcpu_set_ibr(VCPU *vcpu, UINT64 reg, UINT64 val)
381 {
382 // TODO: unimplemented IBRs return a reserved register fault
383 // TODO: Should set Logical CPU state, not just physical
384 ia64_set_ibr(reg,val);
385 return (IA64_NO_FAULT);
386 }
387 static inline
388 IA64FAULT vmx_vcpu_get_dbr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
389 {
390 // TODO: unimplemented DBRs return a reserved register fault
391 UINT64 val = ia64_get_dbr(reg);
392 *pval = val;
393 return (IA64_NO_FAULT);
394 }
395 static inline
396 IA64FAULT vmx_vcpu_get_ibr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
397 {
398 // TODO: unimplemented IBRs return a reserved register fault
399 UINT64 val = ia64_get_ibr(reg);
400 *pval = val;
401 return (IA64_NO_FAULT);
402 }
404 /**************************************************************************
405 VCPU performance monitor register access routines
406 **************************************************************************/
407 static inline
408 IA64FAULT vmx_vcpu_set_pmc(VCPU *vcpu, UINT64 reg, UINT64 val)
409 {
410 // TODO: Should set Logical CPU state, not just physical
411 // NOTE: Writes to unimplemented PMC registers are discarded
412 ia64_set_pmc(reg,val);
413 return (IA64_NO_FAULT);
414 }
415 static inline
416 IA64FAULT vmx_vcpu_set_pmd(VCPU *vcpu, UINT64 reg, UINT64 val)
417 {
418 // TODO: Should set Logical CPU state, not just physical
419 // NOTE: Writes to unimplemented PMD registers are discarded
420 ia64_set_pmd(reg,val);
421 return (IA64_NO_FAULT);
422 }
423 static inline
424 IA64FAULT vmx_vcpu_get_pmc(VCPU *vcpu, UINT64 reg, UINT64 *pval)
425 {
426 // NOTE: Reads from unimplemented PMC registers return zero
427 UINT64 val = (UINT64)ia64_get_pmc(reg);
428 *pval = val;
429 return (IA64_NO_FAULT);
430 }
431 static inline
432 IA64FAULT vmx_vcpu_get_pmd(VCPU *vcpu, UINT64 reg, UINT64 *pval)
433 {
434 // NOTE: Reads from unimplemented PMD registers return zero
435 UINT64 val = (UINT64)ia64_get_pmd(reg);
436 *pval = val;
437 return (IA64_NO_FAULT);
438 }
440 /**************************************************************************
441 VCPU banked general register access routines
442 **************************************************************************/
443 #if 0
444 static inline
445 IA64FAULT vmx_vcpu_bsw0(VCPU *vcpu)
446 {
448 VCPU(vcpu,vpsr) &= ~IA64_PSR_BN;
449 return (IA64_NO_FAULT);
450 }
451 static inline
452 IA64FAULT vmx_vcpu_bsw1(VCPU *vcpu)
453 {
455 VCPU(vcpu,vpsr) |= IA64_PSR_BN;
456 return (IA64_NO_FAULT);
457 }
458 #endif
459 #if 0
460 /* Another hash performance algorithm */
461 #define redistribute_rid(rid) (((rid) & ~0xffff) | (((rid) << 8) & 0xff00) | (((rid) >> 8) & 0xff))
462 #endif
463 static inline unsigned long
464 vmx_vrrtomrr(VCPU *v, unsigned long val)
465 {
466 ia64_rr rr;
468 rr.rrval=val;
469 rr.rid = rr.rid + v->arch.starting_rid;
470 rr.ps = PAGE_SHIFT;
471 rr.ve = 1;
472 return vmMangleRID(rr.rrval);
473 /* Disable this rid allocation algorithm for now */
474 #if 0
475 rid=(((u64)vcpu->domain->domain_id)<<DOMAIN_RID_SHIFT) + rr.rid;
476 rr.rid = redistribute_rid(rid);
477 #endif
479 }
481 #define check_work_pending(v) \
482 (event_pending((v)) || ((v)->arch.irq_new_pending))
483 #endif