ia64/xen-unstable

view linux-2.4.29-xen-sparse/include/asm-xen/msr.h @ 3516:1a4f61d36171

bitkeeper revision 1.1159.223.31 (41f599bcklevTYwPtWQUZ7QK-azDbg)

Fix recent patch to change the way the version string is generated.
Signed-off-by: ian.pratt@cl.cam.ac.uk
author iap10@freefall.cl.cam.ac.uk
date Tue Jan 25 00:58:36 2005 +0000 (2005-01-25)
parents ed0d4ce83995
children 0dc3b8b8c298
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 /*
5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
8 */
10 #define rdmsr(msr,val1,val2) \
11 { \
12 dom0_op_t op; \
13 op.cmd = DOM0_MSR; \
14 op.u.msr.write = 0; \
15 op.u.msr.msr = msr; \
16 op.u.msr.cpu_mask = (1 << current->processor); \
17 HYPERVISOR_dom0_op(&op); \
18 val1 = op.u.msr.out1; \
19 val2 = op.u.msr.out2; \
20 }
22 #define wrmsr(msr,val1,val2) \
23 { \
24 dom0_op_t op; \
25 op.cmd = DOM0_MSR; \
26 op.u.msr.write = 1; \
27 op.u.msr.cpu_mask = (1 << current->processor); \
28 op.u.msr.msr = msr; \
29 op.u.msr.in1 = val1; \
30 op.u.msr.in2 = val2; \
31 HYPERVISOR_dom0_op(&op); \
32 }
34 #define rdtsc(low,high) \
35 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
37 #define rdtscl(low) \
38 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
40 #define rdtscll(val) \
41 __asm__ __volatile__("rdtsc" : "=A" (val))
43 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
45 #define rdpmc(counter,low,high) \
46 __asm__ __volatile__("rdpmc" \
47 : "=a" (low), "=d" (high) \
48 : "c" (counter))
50 /* symbolic names for some interesting MSRs */
51 /* Intel defined MSRs. */
52 #define MSR_IA32_P5_MC_ADDR 0
53 #define MSR_IA32_P5_MC_TYPE 1
54 #define MSR_IA32_PLATFORM_ID 0x17
55 #define MSR_IA32_EBL_CR_POWERON 0x2a
57 #define MSR_IA32_APICBASE 0x1b
58 #define MSR_IA32_APICBASE_BSP (1<<8)
59 #define MSR_IA32_APICBASE_ENABLE (1<<11)
60 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
62 #define MSR_IA32_UCODE_WRITE 0x79
63 #define MSR_IA32_UCODE_REV 0x8b
65 #define MSR_IA32_BBL_CR_CTL 0x119
67 #define MSR_IA32_MCG_CAP 0x179
68 #define MSR_IA32_MCG_STATUS 0x17a
69 #define MSR_IA32_MCG_CTL 0x17b
71 #define MSR_IA32_THERM_CONTROL 0x19a
72 #define MSR_IA32_THERM_INTERRUPT 0x19b
73 #define MSR_IA32_THERM_STATUS 0x19c
74 #define MSR_IA32_MISC_ENABLE 0x1a0
76 #define MSR_IA32_DEBUGCTLMSR 0x1d9
77 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
78 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
79 #define MSR_IA32_LASTINTFROMIP 0x1dd
80 #define MSR_IA32_LASTINTTOIP 0x1de
82 #define MSR_IA32_MC0_CTL 0x400
83 #define MSR_IA32_MC0_STATUS 0x401
84 #define MSR_IA32_MC0_ADDR 0x402
85 #define MSR_IA32_MC0_MISC 0x403
87 #define MSR_P6_PERFCTR0 0xc1
88 #define MSR_P6_PERFCTR1 0xc2
89 #define MSR_P6_EVNTSEL0 0x186
90 #define MSR_P6_EVNTSEL1 0x187
92 #define MSR_IA32_PERF_STATUS 0x198
93 #define MSR_IA32_PERF_CTL 0x199
95 /* AMD Defined MSRs */
96 #define MSR_K6_EFER 0xC0000080
97 #define MSR_K6_STAR 0xC0000081
98 #define MSR_K6_WHCR 0xC0000082
99 #define MSR_K6_UWCCR 0xC0000085
100 #define MSR_K6_EPMR 0xC0000086
101 #define MSR_K6_PSOR 0xC0000087
102 #define MSR_K6_PFIR 0xC0000088
104 #define MSR_K7_EVNTSEL0 0xC0010000
105 #define MSR_K7_PERFCTR0 0xC0010004
106 #define MSR_K7_HWCR 0xC0010015
107 #define MSR_K7_CLK_CTL 0xC001001b
108 #define MSR_K7_FID_VID_CTL 0xC0010041
109 #define MSR_K7_VID_STATUS 0xC0010042
111 /* Centaur-Hauls/IDT defined MSRs. */
112 #define MSR_IDT_FCR1 0x107
113 #define MSR_IDT_FCR2 0x108
114 #define MSR_IDT_FCR3 0x109
115 #define MSR_IDT_FCR4 0x10a
117 #define MSR_IDT_MCR0 0x110
118 #define MSR_IDT_MCR1 0x111
119 #define MSR_IDT_MCR2 0x112
120 #define MSR_IDT_MCR3 0x113
121 #define MSR_IDT_MCR4 0x114
122 #define MSR_IDT_MCR5 0x115
123 #define MSR_IDT_MCR6 0x116
124 #define MSR_IDT_MCR7 0x117
125 #define MSR_IDT_MCR_CTRL 0x120
127 /* VIA Cyrix defined MSRs*/
128 #define MSR_VIA_FCR 0x1107
129 #define MSR_VIA_LONGHAUL 0x110a
130 #define MSR_VIA_BCR2 0x1147
132 /* Transmeta defined MSRs */
133 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
134 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
135 #define MSR_TMTA_LRTI_READOUT 0x80868018
136 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
138 #endif /* __ASM_MSR_H */