ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/kernel/cpu/common.c @ 6294:1a0723cd37f1

Fix many uses of machine addresses in XenLinux. Primarily
this fixes users of virt_to_machine/machine_to_virt to
use virt_to_mfn/mfn_to_virt where that is more appropriate.

This should be a big step to improved PAE stability.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Fri Aug 19 16:06:43 2005 +0000 (2005-08-19)
parents 56a63f9f378f
children f51fe43c5d1c 5f4724c13040 3a8f27c6d56c
line source
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
9 #include <asm/i387.h>
10 #include <asm/msr.h>
11 #include <asm/io.h>
12 #include <asm/mmu_context.h>
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #include <asm/mpspec.h>
15 #include <asm/apic.h>
16 #include <mach_apic.h>
17 #endif
18 #include <asm-xen/hypervisor.h>
20 #include "cpu.h"
22 DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
23 EXPORT_PER_CPU_SYMBOL(cpu_gdt_table);
25 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
26 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
28 static int cachesize_override __initdata = -1;
29 static int disable_x86_fxsr __initdata = 0;
30 static int disable_x86_serial_nr __initdata = 1;
32 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
34 extern void mcheck_init(struct cpuinfo_x86 *c);
36 extern void machine_specific_modify_cpu_capabilities(struct cpuinfo_x86 *c);
38 extern int disable_pse;
40 static void default_init(struct cpuinfo_x86 * c)
41 {
42 /* Not much we can do here... */
43 /* Check if at least it has cpuid */
44 if (c->cpuid_level == -1) {
45 /* No cpuid. It must be an ancient CPU */
46 if (c->x86 == 4)
47 strcpy(c->x86_model_id, "486");
48 else if (c->x86 == 3)
49 strcpy(c->x86_model_id, "386");
50 }
51 }
53 static struct cpu_dev default_cpu = {
54 .c_init = default_init,
55 };
56 static struct cpu_dev * this_cpu = &default_cpu;
58 static int __init cachesize_setup(char *str)
59 {
60 get_option (&str, &cachesize_override);
61 return 1;
62 }
63 __setup("cachesize=", cachesize_setup);
65 int __init get_model_name(struct cpuinfo_x86 *c)
66 {
67 unsigned int *v;
68 char *p, *q;
70 if (cpuid_eax(0x80000000) < 0x80000004)
71 return 0;
73 v = (unsigned int *) c->x86_model_id;
74 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
75 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
76 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
77 c->x86_model_id[48] = 0;
79 /* Intel chips right-justify this string for some dumb reason;
80 undo that brain damage */
81 p = q = &c->x86_model_id[0];
82 while ( *p == ' ' )
83 p++;
84 if ( p != q ) {
85 while ( *p )
86 *q++ = *p++;
87 while ( q <= &c->x86_model_id[48] )
88 *q++ = '\0'; /* Zero-pad the rest */
89 }
91 return 1;
92 }
95 void __init display_cacheinfo(struct cpuinfo_x86 *c)
96 {
97 unsigned int n, dummy, ecx, edx, l2size;
99 n = cpuid_eax(0x80000000);
101 if (n >= 0x80000005) {
102 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
103 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
104 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
105 c->x86_cache_size=(ecx>>24)+(edx>>24);
106 }
108 if (n < 0x80000006) /* Some chips just has a large L1. */
109 return;
111 ecx = cpuid_ecx(0x80000006);
112 l2size = ecx >> 16;
114 /* do processor-specific cache resizing */
115 if (this_cpu->c_size_cache)
116 l2size = this_cpu->c_size_cache(c,l2size);
118 /* Allow user to override all this if necessary. */
119 if (cachesize_override != -1)
120 l2size = cachesize_override;
122 if ( l2size == 0 )
123 return; /* Again, no L2 cache is possible */
125 c->x86_cache_size = l2size;
127 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
128 l2size, ecx & 0xFF);
129 }
131 /* Naming convention should be: <Name> [(<Codename>)] */
132 /* This table only is used unless init_<vendor>() below doesn't set it; */
133 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
135 /* Look up CPU names by table lookup. */
136 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
137 {
138 struct cpu_model_info *info;
140 if ( c->x86_model >= 16 )
141 return NULL; /* Range check */
143 if (!this_cpu)
144 return NULL;
146 info = this_cpu->c_models;
148 while (info && info->family) {
149 if (info->family == c->x86)
150 return info->model_names[c->x86_model];
151 info++;
152 }
153 return NULL; /* Not found */
154 }
157 void __init get_cpu_vendor(struct cpuinfo_x86 *c, int early)
158 {
159 char *v = c->x86_vendor_id;
160 int i;
162 for (i = 0; i < X86_VENDOR_NUM; i++) {
163 if (cpu_devs[i]) {
164 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
165 (cpu_devs[i]->c_ident[1] &&
166 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
167 c->x86_vendor = i;
168 if (!early)
169 this_cpu = cpu_devs[i];
170 break;
171 }
172 }
173 }
174 }
177 static int __init x86_fxsr_setup(char * s)
178 {
179 disable_x86_fxsr = 1;
180 return 1;
181 }
182 __setup("nofxsr", x86_fxsr_setup);
185 /* Standard macro to see if a specific flag is changeable */
186 static inline int flag_is_changeable_p(u32 flag)
187 {
188 u32 f1, f2;
190 asm("pushfl\n\t"
191 "pushfl\n\t"
192 "popl %0\n\t"
193 "movl %0,%1\n\t"
194 "xorl %2,%0\n\t"
195 "pushl %0\n\t"
196 "popfl\n\t"
197 "pushfl\n\t"
198 "popl %0\n\t"
199 "popfl\n\t"
200 : "=&r" (f1), "=&r" (f2)
201 : "ir" (flag));
203 return ((f1^f2) & flag) != 0;
204 }
207 /* Probe for the CPUID instruction */
208 static int __init have_cpuid_p(void)
209 {
210 return flag_is_changeable_p(X86_EFLAGS_ID);
211 }
213 /* Do minimum CPU detection early.
214 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
215 The others are not touched to avoid unwanted side effects. */
216 static void __init early_cpu_detect(void)
217 {
218 struct cpuinfo_x86 *c = &boot_cpu_data;
220 c->x86_cache_alignment = 32;
222 if (!have_cpuid_p())
223 return;
225 /* Get vendor name */
226 cpuid(0x00000000, &c->cpuid_level,
227 (int *)&c->x86_vendor_id[0],
228 (int *)&c->x86_vendor_id[8],
229 (int *)&c->x86_vendor_id[4]);
231 get_cpu_vendor(c, 1);
233 c->x86 = 4;
234 if (c->cpuid_level >= 0x00000001) {
235 u32 junk, tfms, cap0, misc;
236 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
237 c->x86 = (tfms >> 8) & 15;
238 c->x86_model = (tfms >> 4) & 15;
239 if (c->x86 == 0xf) {
240 c->x86 += (tfms >> 20) & 0xff;
241 c->x86_model += ((tfms >> 16) & 0xF) << 4;
242 }
243 c->x86_mask = tfms & 15;
244 if (cap0 & (1<<19))
245 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
246 }
248 early_intel_workaround(c);
250 #ifdef CONFIG_X86_HT
251 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
252 #endif
253 }
255 void __init generic_identify(struct cpuinfo_x86 * c)
256 {
257 u32 tfms, xlvl;
258 int junk;
260 if (have_cpuid_p()) {
261 /* Get vendor name */
262 cpuid(0x00000000, &c->cpuid_level,
263 (int *)&c->x86_vendor_id[0],
264 (int *)&c->x86_vendor_id[8],
265 (int *)&c->x86_vendor_id[4]);
267 get_cpu_vendor(c, 0);
268 /* Initialize the standard set of capabilities */
269 /* Note that the vendor-specific code below might override */
271 /* Intel-defined flags: level 0x00000001 */
272 if ( c->cpuid_level >= 0x00000001 ) {
273 u32 capability, excap;
274 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
275 c->x86_capability[0] = capability;
276 c->x86_capability[4] = excap;
277 c->x86 = (tfms >> 8) & 15;
278 c->x86_model = (tfms >> 4) & 15;
279 if (c->x86 == 0xf) {
280 c->x86 += (tfms >> 20) & 0xff;
281 c->x86_model += ((tfms >> 16) & 0xF) << 4;
282 }
283 c->x86_mask = tfms & 15;
284 } else {
285 /* Have CPUID level 0 only - unheard of */
286 c->x86 = 4;
287 }
289 /* AMD-defined flags: level 0x80000001 */
290 xlvl = cpuid_eax(0x80000000);
291 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
292 if ( xlvl >= 0x80000001 ) {
293 c->x86_capability[1] = cpuid_edx(0x80000001);
294 c->x86_capability[6] = cpuid_ecx(0x80000001);
295 }
296 if ( xlvl >= 0x80000004 )
297 get_model_name(c); /* Default name */
298 }
299 }
300 }
302 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
303 {
304 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
305 /* Disable processor serial number */
306 unsigned long lo,hi;
307 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
308 lo |= 0x200000;
309 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
310 printk(KERN_NOTICE "CPU serial number disabled.\n");
311 clear_bit(X86_FEATURE_PN, c->x86_capability);
313 /* Disabling the serial number may affect the cpuid level */
314 c->cpuid_level = cpuid_eax(0);
315 }
316 }
318 static int __init x86_serial_nr_setup(char *s)
319 {
320 disable_x86_serial_nr = 0;
321 return 1;
322 }
323 __setup("serialnumber", x86_serial_nr_setup);
327 /*
328 * This does the hard work of actually picking apart the CPU stuff...
329 */
330 void __init identify_cpu(struct cpuinfo_x86 *c)
331 {
332 int i;
334 c->loops_per_jiffy = loops_per_jiffy;
335 c->x86_cache_size = -1;
336 c->x86_vendor = X86_VENDOR_UNKNOWN;
337 c->cpuid_level = -1; /* CPUID not detected */
338 c->x86_model = c->x86_mask = 0; /* So far unknown... */
339 c->x86_vendor_id[0] = '\0'; /* Unset */
340 c->x86_model_id[0] = '\0'; /* Unset */
341 c->x86_num_cores = 1;
342 memset(&c->x86_capability, 0, sizeof c->x86_capability);
344 if (!have_cpuid_p()) {
345 /* First of all, decide if this is a 486 or higher */
346 /* It's a 486 if we can modify the AC flag */
347 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
348 c->x86 = 4;
349 else
350 c->x86 = 3;
351 }
353 generic_identify(c);
355 printk(KERN_DEBUG "CPU: After generic identify, caps:");
356 for (i = 0; i < NCAPINTS; i++)
357 printk(" %08lx", c->x86_capability[i]);
358 printk("\n");
360 if (this_cpu->c_identify) {
361 this_cpu->c_identify(c);
363 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
364 for (i = 0; i < NCAPINTS; i++)
365 printk(" %08lx", c->x86_capability[i]);
366 printk("\n");
367 }
369 /*
370 * Vendor-specific initialization. In this section we
371 * canonicalize the feature flags, meaning if there are
372 * features a certain CPU supports which CPUID doesn't
373 * tell us, CPUID claiming incorrect flags, or other bugs,
374 * we handle them here.
375 *
376 * At the end of this section, c->x86_capability better
377 * indicate the features this CPU genuinely supports!
378 */
379 if (this_cpu->c_init)
380 this_cpu->c_init(c);
382 /* Disable the PN if appropriate */
383 squash_the_stupid_serial_number(c);
385 /*
386 * The vendor-specific functions might have changed features. Now
387 * we do "generic changes."
388 */
390 /* TSC disabled? */
391 if ( tsc_disable )
392 clear_bit(X86_FEATURE_TSC, c->x86_capability);
394 /* FXSR disabled? */
395 if (disable_x86_fxsr) {
396 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
397 clear_bit(X86_FEATURE_XMM, c->x86_capability);
398 }
400 if (disable_pse)
401 clear_bit(X86_FEATURE_PSE, c->x86_capability);
403 /* If the model name is still unset, do table lookup. */
404 if ( !c->x86_model_id[0] ) {
405 char *p;
406 p = table_lookup_model(c);
407 if ( p )
408 strcpy(c->x86_model_id, p);
409 else
410 /* Last resort... */
411 sprintf(c->x86_model_id, "%02x/%02x",
412 c->x86_vendor, c->x86_model);
413 }
415 machine_specific_modify_cpu_capabilities(c);
417 /* Now the feature flags better reflect actual CPU features! */
419 printk(KERN_DEBUG "CPU: After all inits, caps:");
420 for (i = 0; i < NCAPINTS; i++)
421 printk(" %08lx", c->x86_capability[i]);
422 printk("\n");
424 /*
425 * On SMP, boot_cpu_data holds the common feature set between
426 * all CPUs; so make sure that we indicate which features are
427 * common between the CPUs. The first time this routine gets
428 * executed, c == &boot_cpu_data.
429 */
430 if ( c != &boot_cpu_data ) {
431 /* AND the already accumulated flags with these */
432 for ( i = 0 ; i < NCAPINTS ; i++ )
433 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
434 }
436 /* Init Machine Check Exception if available. */
437 #ifdef CONFIG_X86_MCE
438 mcheck_init(c);
439 #endif
440 }
442 #ifdef CONFIG_X86_HT
443 void __init detect_ht(struct cpuinfo_x86 *c)
444 {
445 u32 eax, ebx, ecx, edx;
446 int index_msb, tmp;
447 int cpu = smp_processor_id();
449 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
450 return;
452 cpuid(1, &eax, &ebx, &ecx, &edx);
453 smp_num_siblings = (ebx & 0xff0000) >> 16;
455 if (smp_num_siblings == 1) {
456 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
457 } else if (smp_num_siblings > 1 ) {
458 index_msb = 31;
460 if (smp_num_siblings > NR_CPUS) {
461 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
462 smp_num_siblings = 1;
463 return;
464 }
465 tmp = smp_num_siblings;
466 while ((tmp & 0x80000000 ) == 0) {
467 tmp <<=1 ;
468 index_msb--;
469 }
470 if (smp_num_siblings & (smp_num_siblings - 1))
471 index_msb++;
472 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
474 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
475 phys_proc_id[cpu]);
477 smp_num_siblings = smp_num_siblings / c->x86_num_cores;
479 tmp = smp_num_siblings;
480 index_msb = 31;
481 while ((tmp & 0x80000000) == 0) {
482 tmp <<=1 ;
483 index_msb--;
484 }
486 if (smp_num_siblings & (smp_num_siblings - 1))
487 index_msb++;
489 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
491 if (c->x86_num_cores > 1)
492 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
493 cpu_core_id[cpu]);
494 }
495 }
496 #endif
498 void __init print_cpu_info(struct cpuinfo_x86 *c)
499 {
500 char *vendor = NULL;
502 if (c->x86_vendor < X86_VENDOR_NUM)
503 vendor = this_cpu->c_vendor;
504 else if (c->cpuid_level >= 0)
505 vendor = c->x86_vendor_id;
507 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
508 printk("%s ", vendor);
510 if (!c->x86_model_id[0])
511 printk("%d86", c->x86);
512 else
513 printk("%s", c->x86_model_id);
515 if (c->x86_mask || c->cpuid_level >= 0)
516 printk(" stepping %02x\n", c->x86_mask);
517 else
518 printk("\n");
519 }
521 cpumask_t cpu_initialized __initdata = CPU_MASK_NONE;
523 /* This is hacky. :)
524 * We're emulating future behavior.
525 * In the future, the cpu-specific init functions will be called implicitly
526 * via the magic of initcalls.
527 * They will insert themselves into the cpu_devs structure.
528 * Then, when cpu_init() is called, we can just iterate over that array.
529 */
531 extern int intel_cpu_init(void);
532 extern int cyrix_init_cpu(void);
533 extern int nsc_init_cpu(void);
534 extern int amd_init_cpu(void);
535 extern int centaur_init_cpu(void);
536 extern int transmeta_init_cpu(void);
537 extern int rise_init_cpu(void);
538 extern int nexgen_init_cpu(void);
539 extern int umc_init_cpu(void);
541 void __init early_cpu_init(void)
542 {
543 intel_cpu_init();
544 cyrix_init_cpu();
545 nsc_init_cpu();
546 amd_init_cpu();
547 centaur_init_cpu();
548 transmeta_init_cpu();
549 rise_init_cpu();
550 nexgen_init_cpu();
551 umc_init_cpu();
552 early_cpu_detect();
554 #ifdef CONFIG_DEBUG_PAGEALLOC
555 /* pse is not compatible with on-the-fly unmapping,
556 * disable it even if the cpus claim to support it.
557 */
558 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
559 disable_pse = 1;
560 #endif
561 }
563 void __init cpu_gdt_init(struct Xgt_desc_struct *gdt_descr)
564 {
565 unsigned long frames[16];
566 unsigned long va;
567 int f;
569 for (va = gdt_descr->address, f = 0;
570 va < gdt_descr->address + gdt_descr->size;
571 va += PAGE_SIZE, f++) {
572 frames[f] = virt_to_mfn(va);
573 make_page_readonly((void *)va);
574 }
575 if (HYPERVISOR_set_gdt(frames, gdt_descr->size / 8))
576 BUG();
577 lgdt_finish();
578 }
580 /*
581 * cpu_init() initializes state that is per-CPU. Some data is already
582 * initialized (naturally) in the bootstrap process, such as the GDT
583 * and IDT. We reload them nevertheless, this function acts as a
584 * 'CPU state barrier', nothing should get across.
585 */
586 void __init cpu_init (void)
587 {
588 int cpu = smp_processor_id();
589 struct tss_struct * t = &per_cpu(init_tss, cpu);
590 struct thread_struct *thread = &current->thread;
592 if (cpu_test_and_set(cpu, cpu_initialized)) {
593 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
594 for (;;) local_irq_enable();
595 }
596 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
598 if (cpu_has_vme || cpu_has_de)
599 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
600 if (tsc_disable && cpu_has_tsc) {
601 printk(KERN_NOTICE "Disabling TSC...\n");
602 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
603 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
604 set_in_cr4(X86_CR4_TSD);
605 }
607 /*
608 * Set up the per-thread TLS descriptor cache:
609 */
610 memcpy(thread->tls_array, &get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN],
611 GDT_ENTRY_TLS_ENTRIES * 8);
613 cpu_gdt_init(&cpu_gdt_descr[cpu]);
615 /*
616 * Delete NT
617 */
618 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
620 /*
621 * Set up and load the per-CPU TSS and LDT
622 */
623 atomic_inc(&init_mm.mm_count);
624 current->active_mm = &init_mm;
625 if (current->mm)
626 BUG();
627 enter_lazy_tlb(&init_mm, current);
629 load_esp0(t, thread);
631 load_LDT(&init_mm.context);
633 /* Clear %fs and %gs. */
634 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
636 /* Clear all 6 debug registers: */
638 #define CD(register) HYPERVISOR_set_debugreg(register, 0)
640 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
642 #undef CD
644 /*
645 * Force FPU initialization:
646 */
647 current_thread_info()->status = 0;
648 clear_used_math();
649 mxcsr_feature_mask_init();
650 }