ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/kernel/iosapic.c @ 9745:19148831ab05

[IA64] add base iosapic files

Add base iosapic files from Linux-2.6.16 in preparation for
Kevin's iosapic changes.

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild.aw
date Fri Apr 21 08:56:24 2006 -0600 (2006-04-21)
parents
children de2dc4e7966a
line source
1 /*
2 * I/O SAPIC support.
3 *
4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
11 *
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
13 * In particular, we now have separate handlers for edge
14 * and level triggered interrupts.
15 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
16 * PCI to vector mapping, shared PCI interrupts.
17 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
18 * Clean up much of the old IOSAPIC cruft.
19 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
20 * ACPI S5(SoftOff) support.
21 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
22 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
23 * iosapic_set_affinity(), initializations for
24 * /proc/irq/#/smp_affinity
25 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
26 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
27 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
28 * error
29 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
30 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
31 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
32 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
33 * Remove iosapic_address & gsi_base from external interfaces.
34 * Rationalize __init/__devinit attributes.
35 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
36 * Updated to work with irq migration necessary for CPU Hotplug
37 */
38 /*
39 * Here is what the interrupt logic between a PCI device and the kernel looks like:
40 *
41 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
42 * device is uniquely identified by its bus--, and slot-number (the function
43 * number does not matter here because all functions share the same interrupt
44 * lines).
45 *
46 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
47 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
48 * triggered and use the same polarity). Each interrupt line has a unique Global
49 * System Interrupt (GSI) number which can be calculated as the sum of the controller's
50 * base GSI number and the IOSAPIC pin number to which the line connects.
51 *
52 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
53 * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
54 *
55 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
56 * architecture-independent interrupt handling mechanism in Linux. As an
57 * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
58 * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
59 * IRQ. A platform can implement platform_irq_to_vector(irq) and
60 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
61 * Please see also include/asm-ia64/hw_irq.h for those APIs.
62 *
63 * To sum up, there are three levels of mappings involved:
64 *
65 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
66 *
67 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
68 * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
69 * source code.
70 */
71 #include <linux/config.h>
73 #include <linux/acpi.h>
74 #include <linux/init.h>
75 #include <linux/irq.h>
76 #include <linux/kernel.h>
77 #include <linux/list.h>
78 #include <linux/pci.h>
79 #include <linux/smp.h>
80 #include <linux/smp_lock.h>
81 #include <linux/string.h>
82 #include <linux/bootmem.h>
84 #include <asm/delay.h>
85 #include <asm/hw_irq.h>
86 #include <asm/io.h>
87 #include <asm/iosapic.h>
88 #include <asm/machvec.h>
89 #include <asm/processor.h>
90 #include <asm/ptrace.h>
91 #include <asm/system.h>
94 #undef DEBUG_INTERRUPT_ROUTING
96 #ifdef DEBUG_INTERRUPT_ROUTING
97 #define DBG(fmt...) printk(fmt)
98 #else
99 #define DBG(fmt...)
100 #endif
102 #define NR_PREALLOCATE_RTE_ENTRIES (PAGE_SIZE / sizeof(struct iosapic_rte_info))
103 #define RTE_PREALLOCATED (1)
105 static DEFINE_SPINLOCK(iosapic_lock);
107 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
109 struct iosapic_rte_info {
110 struct list_head rte_list; /* node in list of RTEs sharing the same vector */
111 char __iomem *addr; /* base address of IOSAPIC */
112 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
113 char rte_index; /* IOSAPIC RTE index */
114 int refcnt; /* reference counter */
115 unsigned int flags; /* flags */
116 } ____cacheline_aligned;
118 static struct iosapic_intr_info {
119 struct list_head rtes; /* RTEs using this vector (empty => not an IOSAPIC interrupt) */
120 int count; /* # of RTEs that shares this vector */
121 u32 low32; /* current value of low word of Redirection table entry */
122 unsigned int dest; /* destination CPU physical ID */
123 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
124 unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */
125 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
126 } iosapic_intr_info[IA64_NUM_VECTORS];
128 static struct iosapic {
129 char __iomem *addr; /* base address of IOSAPIC */
130 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
131 unsigned short num_rte; /* number of RTE in this IOSAPIC */
132 int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
133 #ifdef CONFIG_NUMA
134 unsigned short node; /* numa node association via pxm */
135 #endif
136 } iosapic_lists[NR_IOSAPICS];
138 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
140 static int iosapic_kmalloc_ok;
141 static LIST_HEAD(free_rte_list);
143 /*
144 * Find an IOSAPIC associated with a GSI
145 */
146 static inline int
147 find_iosapic (unsigned int gsi)
148 {
149 int i;
151 for (i = 0; i < NR_IOSAPICS; i++) {
152 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
153 return i;
154 }
156 return -1;
157 }
159 static inline int
160 _gsi_to_vector (unsigned int gsi)
161 {
162 struct iosapic_intr_info *info;
163 struct iosapic_rte_info *rte;
165 for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
166 list_for_each_entry(rte, &info->rtes, rte_list)
167 if (rte->gsi_base + rte->rte_index == gsi)
168 return info - iosapic_intr_info;
169 return -1;
170 }
172 /*
173 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
174 * entry exists, return -1.
175 */
176 inline int
177 gsi_to_vector (unsigned int gsi)
178 {
179 return _gsi_to_vector(gsi);
180 }
182 int
183 gsi_to_irq (unsigned int gsi)
184 {
185 unsigned long flags;
186 int irq;
187 /*
188 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
189 * numbers...
190 */
191 spin_lock_irqsave(&iosapic_lock, flags);
192 {
193 irq = _gsi_to_vector(gsi);
194 }
195 spin_unlock_irqrestore(&iosapic_lock, flags);
197 return irq;
198 }
200 static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, unsigned int vec)
201 {
202 struct iosapic_rte_info *rte;
204 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
205 if (rte->gsi_base + rte->rte_index == gsi)
206 return rte;
207 return NULL;
208 }
210 static void
211 set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
212 {
213 unsigned long pol, trigger, dmode;
214 u32 low32, high32;
215 char __iomem *addr;
216 int rte_index;
217 char redir;
218 struct iosapic_rte_info *rte;
220 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
222 rte = gsi_vector_to_rte(gsi, vector);
223 if (!rte)
224 return; /* not an IOSAPIC interrupt */
226 rte_index = rte->rte_index;
227 addr = rte->addr;
228 pol = iosapic_intr_info[vector].polarity;
229 trigger = iosapic_intr_info[vector].trigger;
230 dmode = iosapic_intr_info[vector].dmode;
232 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
234 #ifdef CONFIG_SMP
235 {
236 unsigned int irq;
238 for (irq = 0; irq < NR_IRQS; ++irq)
239 if (irq_to_vector(irq) == vector) {
240 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
241 break;
242 }
243 }
244 #endif
246 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
247 (trigger << IOSAPIC_TRIGGER_SHIFT) |
248 (dmode << IOSAPIC_DELIVERY_SHIFT) |
249 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
250 vector);
252 /* dest contains both id and eid */
253 high32 = (dest << IOSAPIC_DEST_SHIFT);
255 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
256 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
257 iosapic_intr_info[vector].low32 = low32;
258 iosapic_intr_info[vector].dest = dest;
259 }
261 static void
262 nop (unsigned int vector)
263 {
264 /* do nothing... */
265 }
267 static void
268 mask_irq (unsigned int irq)
269 {
270 unsigned long flags;
271 char __iomem *addr;
272 u32 low32;
273 int rte_index;
274 ia64_vector vec = irq_to_vector(irq);
275 struct iosapic_rte_info *rte;
277 if (list_empty(&iosapic_intr_info[vec].rtes))
278 return; /* not an IOSAPIC interrupt! */
280 spin_lock_irqsave(&iosapic_lock, flags);
281 {
282 /* set only the mask bit */
283 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
284 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
285 addr = rte->addr;
286 rte_index = rte->rte_index;
287 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
288 }
289 }
290 spin_unlock_irqrestore(&iosapic_lock, flags);
291 }
293 static void
294 unmask_irq (unsigned int irq)
295 {
296 unsigned long flags;
297 char __iomem *addr;
298 u32 low32;
299 int rte_index;
300 ia64_vector vec = irq_to_vector(irq);
301 struct iosapic_rte_info *rte;
303 if (list_empty(&iosapic_intr_info[vec].rtes))
304 return; /* not an IOSAPIC interrupt! */
306 spin_lock_irqsave(&iosapic_lock, flags);
307 {
308 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
309 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
310 addr = rte->addr;
311 rte_index = rte->rte_index;
312 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
313 }
314 }
315 spin_unlock_irqrestore(&iosapic_lock, flags);
316 }
319 static void
320 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
321 {
322 #ifdef CONFIG_SMP
323 unsigned long flags;
324 u32 high32, low32;
325 int dest, rte_index;
326 char __iomem *addr;
327 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
328 ia64_vector vec;
329 struct iosapic_rte_info *rte;
331 irq &= (~IA64_IRQ_REDIRECTED);
332 vec = irq_to_vector(irq);
334 if (cpus_empty(mask))
335 return;
337 dest = cpu_physical_id(first_cpu(mask));
339 if (list_empty(&iosapic_intr_info[vec].rtes))
340 return; /* not an IOSAPIC interrupt */
342 set_irq_affinity_info(irq, dest, redir);
344 /* dest contains both id and eid */
345 high32 = dest << IOSAPIC_DEST_SHIFT;
347 spin_lock_irqsave(&iosapic_lock, flags);
348 {
349 low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
351 if (redir)
352 /* change delivery mode to lowest priority */
353 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
354 else
355 /* change delivery mode to fixed */
356 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
358 iosapic_intr_info[vec].low32 = low32;
359 iosapic_intr_info[vec].dest = dest;
360 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
361 addr = rte->addr;
362 rte_index = rte->rte_index;
363 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
364 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
365 }
366 }
367 spin_unlock_irqrestore(&iosapic_lock, flags);
368 #endif
369 }
371 /*
372 * Handlers for level-triggered interrupts.
373 */
375 static unsigned int
376 iosapic_startup_level_irq (unsigned int irq)
377 {
378 unmask_irq(irq);
379 return 0;
380 }
382 static void
383 iosapic_end_level_irq (unsigned int irq)
384 {
385 ia64_vector vec = irq_to_vector(irq);
386 struct iosapic_rte_info *rte;
388 move_irq(irq);
389 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
390 iosapic_eoi(rte->addr, vec);
391 }
393 #define iosapic_shutdown_level_irq mask_irq
394 #define iosapic_enable_level_irq unmask_irq
395 #define iosapic_disable_level_irq mask_irq
396 #define iosapic_ack_level_irq nop
398 struct hw_interrupt_type irq_type_iosapic_level = {
399 .typename = "IO-SAPIC-level",
400 .startup = iosapic_startup_level_irq,
401 .shutdown = iosapic_shutdown_level_irq,
402 .enable = iosapic_enable_level_irq,
403 .disable = iosapic_disable_level_irq,
404 .ack = iosapic_ack_level_irq,
405 .end = iosapic_end_level_irq,
406 .set_affinity = iosapic_set_affinity
407 };
409 /*
410 * Handlers for edge-triggered interrupts.
411 */
413 static unsigned int
414 iosapic_startup_edge_irq (unsigned int irq)
415 {
416 unmask_irq(irq);
417 /*
418 * IOSAPIC simply drops interrupts pended while the
419 * corresponding pin was masked, so we can't know if an
420 * interrupt is pending already. Let's hope not...
421 */
422 return 0;
423 }
425 static void
426 iosapic_ack_edge_irq (unsigned int irq)
427 {
428 irq_desc_t *idesc = irq_descp(irq);
430 move_irq(irq);
431 /*
432 * Once we have recorded IRQ_PENDING already, we can mask the
433 * interrupt for real. This prevents IRQ storms from unhandled
434 * devices.
435 */
436 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
437 mask_irq(irq);
438 }
440 #define iosapic_enable_edge_irq unmask_irq
441 #define iosapic_disable_edge_irq nop
442 #define iosapic_end_edge_irq nop
444 struct hw_interrupt_type irq_type_iosapic_edge = {
445 .typename = "IO-SAPIC-edge",
446 .startup = iosapic_startup_edge_irq,
447 .shutdown = iosapic_disable_edge_irq,
448 .enable = iosapic_enable_edge_irq,
449 .disable = iosapic_disable_edge_irq,
450 .ack = iosapic_ack_edge_irq,
451 .end = iosapic_end_edge_irq,
452 .set_affinity = iosapic_set_affinity
453 };
455 unsigned int
456 iosapic_version (char __iomem *addr)
457 {
458 /*
459 * IOSAPIC Version Register return 32 bit structure like:
460 * {
461 * unsigned int version : 8;
462 * unsigned int reserved1 : 8;
463 * unsigned int max_redir : 8;
464 * unsigned int reserved2 : 8;
465 * }
466 */
467 return iosapic_read(addr, IOSAPIC_VERSION);
468 }
470 static int iosapic_find_sharable_vector (unsigned long trigger, unsigned long pol)
471 {
472 int i, vector = -1, min_count = -1;
473 struct iosapic_intr_info *info;
475 /*
476 * shared vectors for edge-triggered interrupts are not
477 * supported yet
478 */
479 if (trigger == IOSAPIC_EDGE)
480 return -1;
482 for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
483 info = &iosapic_intr_info[i];
484 if (info->trigger == trigger && info->polarity == pol &&
485 (info->dmode == IOSAPIC_FIXED || info->dmode == IOSAPIC_LOWEST_PRIORITY)) {
486 if (min_count == -1 || info->count < min_count) {
487 vector = i;
488 min_count = info->count;
489 }
490 }
491 }
493 return vector;
494 }
496 /*
497 * if the given vector is already owned by other,
498 * assign a new vector for the other and make the vector available
499 */
500 static void __init
501 iosapic_reassign_vector (int vector)
502 {
503 int new_vector;
505 if (!list_empty(&iosapic_intr_info[vector].rtes)) {
506 new_vector = assign_irq_vector(AUTO_ASSIGN);
507 if (new_vector < 0)
508 panic("%s: out of interrupt vectors!\n", __FUNCTION__);
509 printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
510 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
511 sizeof(struct iosapic_intr_info));
512 INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes);
513 list_move(iosapic_intr_info[vector].rtes.next, &iosapic_intr_info[new_vector].rtes);
514 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
515 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
516 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
517 }
518 }
520 static struct iosapic_rte_info *iosapic_alloc_rte (void)
521 {
522 int i;
523 struct iosapic_rte_info *rte;
524 int preallocated = 0;
526 if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
527 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * NR_PREALLOCATE_RTE_ENTRIES);
528 if (!rte)
529 return NULL;
530 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
531 list_add(&rte->rte_list, &free_rte_list);
532 }
534 if (!list_empty(&free_rte_list)) {
535 rte = list_entry(free_rte_list.next, struct iosapic_rte_info, rte_list);
536 list_del(&rte->rte_list);
537 preallocated++;
538 } else {
539 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
540 if (!rte)
541 return NULL;
542 }
544 memset(rte, 0, sizeof(struct iosapic_rte_info));
545 if (preallocated)
546 rte->flags |= RTE_PREALLOCATED;
548 return rte;
549 }
551 static void iosapic_free_rte (struct iosapic_rte_info *rte)
552 {
553 if (rte->flags & RTE_PREALLOCATED)
554 list_add_tail(&rte->rte_list, &free_rte_list);
555 else
556 kfree(rte);
557 }
559 static inline int vector_is_shared (int vector)
560 {
561 return (iosapic_intr_info[vector].count > 1);
562 }
564 static int
565 register_intr (unsigned int gsi, int vector, unsigned char delivery,
566 unsigned long polarity, unsigned long trigger)
567 {
568 irq_desc_t *idesc;
569 struct hw_interrupt_type *irq_type;
570 int rte_index;
571 int index;
572 unsigned long gsi_base;
573 void __iomem *iosapic_address;
574 struct iosapic_rte_info *rte;
576 index = find_iosapic(gsi);
577 if (index < 0) {
578 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi);
579 return -ENODEV;
580 }
582 iosapic_address = iosapic_lists[index].addr;
583 gsi_base = iosapic_lists[index].gsi_base;
585 rte = gsi_vector_to_rte(gsi, vector);
586 if (!rte) {
587 rte = iosapic_alloc_rte();
588 if (!rte) {
589 printk(KERN_WARNING "%s: cannot allocate memory\n", __FUNCTION__);
590 return -ENOMEM;
591 }
593 rte_index = gsi - gsi_base;
594 rte->rte_index = rte_index;
595 rte->addr = iosapic_address;
596 rte->gsi_base = gsi_base;
597 rte->refcnt++;
598 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
599 iosapic_intr_info[vector].count++;
600 iosapic_lists[index].rtes_inuse++;
601 }
602 else if (vector_is_shared(vector)) {
603 struct iosapic_intr_info *info = &iosapic_intr_info[vector];
604 if (info->trigger != trigger || info->polarity != polarity) {
605 printk (KERN_WARNING "%s: cannot override the interrupt\n", __FUNCTION__);
606 return -EINVAL;
607 }
608 }
610 iosapic_intr_info[vector].polarity = polarity;
611 iosapic_intr_info[vector].dmode = delivery;
612 iosapic_intr_info[vector].trigger = trigger;
614 if (trigger == IOSAPIC_EDGE)
615 irq_type = &irq_type_iosapic_edge;
616 else
617 irq_type = &irq_type_iosapic_level;
619 idesc = irq_descp(vector);
620 if (idesc->handler != irq_type) {
621 if (idesc->handler != &no_irq_type)
622 printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
623 __FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
624 idesc->handler = irq_type;
625 }
626 return 0;
627 }
629 static unsigned int
630 get_target_cpu (unsigned int gsi, int vector)
631 {
632 #ifdef CONFIG_SMP
633 static int cpu = -1;
635 /*
636 * In case of vector shared by multiple RTEs, all RTEs that
637 * share the vector need to use the same destination CPU.
638 */
639 if (!list_empty(&iosapic_intr_info[vector].rtes))
640 return iosapic_intr_info[vector].dest;
642 /*
643 * If the platform supports redirection via XTP, let it
644 * distribute interrupts.
645 */
646 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
647 return cpu_physical_id(smp_processor_id());
649 /*
650 * Some interrupts (ACPI SCI, for instance) are registered
651 * before the BSP is marked as online.
652 */
653 if (!cpu_online(smp_processor_id()))
654 return cpu_physical_id(smp_processor_id());
656 #ifdef CONFIG_NUMA
657 {
658 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
659 cpumask_t cpu_mask;
661 iosapic_index = find_iosapic(gsi);
662 if (iosapic_index < 0 ||
663 iosapic_lists[iosapic_index].node == MAX_NUMNODES)
664 goto skip_numa_setup;
666 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
668 for_each_cpu_mask(numa_cpu, cpu_mask) {
669 if (!cpu_online(numa_cpu))
670 cpu_clear(numa_cpu, cpu_mask);
671 }
673 num_cpus = cpus_weight(cpu_mask);
675 if (!num_cpus)
676 goto skip_numa_setup;
678 /* Use vector assigment to distribute across cpus in node */
679 cpu_index = vector % num_cpus;
681 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
682 numa_cpu = next_cpu(numa_cpu, cpu_mask);
684 if (numa_cpu != NR_CPUS)
685 return cpu_physical_id(numa_cpu);
686 }
687 skip_numa_setup:
688 #endif
689 /*
690 * Otherwise, round-robin interrupt vectors across all the
691 * processors. (It'd be nice if we could be smarter in the
692 * case of NUMA.)
693 */
694 do {
695 if (++cpu >= NR_CPUS)
696 cpu = 0;
697 } while (!cpu_online(cpu));
699 return cpu_physical_id(cpu);
700 #else
701 return cpu_physical_id(smp_processor_id());
702 #endif
703 }
705 /*
706 * ACPI can describe IOSAPIC interrupts via static tables and namespace
707 * methods. This provides an interface to register those interrupts and
708 * program the IOSAPIC RTE.
709 */
710 int
711 iosapic_register_intr (unsigned int gsi,
712 unsigned long polarity, unsigned long trigger)
713 {
714 int vector, mask = 1, err;
715 unsigned int dest;
716 unsigned long flags;
717 struct iosapic_rte_info *rte;
718 u32 low32;
719 again:
720 /*
721 * If this GSI has already been registered (i.e., it's a
722 * shared interrupt, or we lost a race to register it),
723 * don't touch the RTE.
724 */
725 spin_lock_irqsave(&iosapic_lock, flags);
726 {
727 vector = gsi_to_vector(gsi);
728 if (vector > 0) {
729 rte = gsi_vector_to_rte(gsi, vector);
730 rte->refcnt++;
731 spin_unlock_irqrestore(&iosapic_lock, flags);
732 return vector;
733 }
734 }
735 spin_unlock_irqrestore(&iosapic_lock, flags);
737 /* If vector is running out, we try to find a sharable vector */
738 vector = assign_irq_vector(AUTO_ASSIGN);
739 if (vector < 0) {
740 vector = iosapic_find_sharable_vector(trigger, polarity);
741 if (vector < 0)
742 return -ENOSPC;
743 }
745 spin_lock_irqsave(&irq_descp(vector)->lock, flags);
746 spin_lock(&iosapic_lock);
747 {
748 if (gsi_to_vector(gsi) > 0) {
749 if (list_empty(&iosapic_intr_info[vector].rtes))
750 free_irq_vector(vector);
751 spin_unlock(&iosapic_lock);
752 spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
753 goto again;
754 }
756 dest = get_target_cpu(gsi, vector);
757 err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
758 polarity, trigger);
759 if (err < 0) {
760 spin_unlock(&iosapic_lock);
761 spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
762 return err;
763 }
765 /*
766 * If the vector is shared and already unmasked for
767 * other interrupt sources, don't mask it.
768 */
769 low32 = iosapic_intr_info[vector].low32;
770 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
771 mask = 0;
772 set_rte(gsi, vector, dest, mask);
773 }
774 spin_unlock(&iosapic_lock);
775 spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
777 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
778 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
779 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
780 cpu_logical_id(dest), dest, vector);
782 return vector;
783 }
785 void
786 iosapic_unregister_intr (unsigned int gsi)
787 {
788 unsigned long flags;
789 int irq, vector, index;
790 irq_desc_t *idesc;
791 u32 low32;
792 unsigned long trigger, polarity;
793 unsigned int dest;
794 struct iosapic_rte_info *rte;
796 /*
797 * If the irq associated with the gsi is not found,
798 * iosapic_unregister_intr() is unbalanced. We need to check
799 * this again after getting locks.
800 */
801 irq = gsi_to_irq(gsi);
802 if (irq < 0) {
803 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi);
804 WARN_ON(1);
805 return;
806 }
807 vector = irq_to_vector(irq);
809 idesc = irq_descp(irq);
810 spin_lock_irqsave(&idesc->lock, flags);
811 spin_lock(&iosapic_lock);
812 {
813 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
814 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi);
815 WARN_ON(1);
816 goto out;
817 }
819 if (--rte->refcnt > 0)
820 goto out;
822 /* Mask the interrupt */
823 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
824 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32);
826 /* Remove the rte entry from the list */
827 list_del(&rte->rte_list);
828 iosapic_intr_info[vector].count--;
829 iosapic_free_rte(rte);
830 index = find_iosapic(gsi);
831 iosapic_lists[index].rtes_inuse--;
832 WARN_ON(iosapic_lists[index].rtes_inuse < 0);
834 trigger = iosapic_intr_info[vector].trigger;
835 polarity = iosapic_intr_info[vector].polarity;
836 dest = iosapic_intr_info[vector].dest;
837 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
838 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
839 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
840 cpu_logical_id(dest), dest, vector);
842 if (list_empty(&iosapic_intr_info[vector].rtes)) {
843 /* Sanity check */
844 BUG_ON(iosapic_intr_info[vector].count);
846 /* Clear the interrupt controller descriptor */
847 idesc->handler = &no_irq_type;
849 /* Clear the interrupt information */
850 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
851 iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
852 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
854 if (idesc->action) {
855 printk(KERN_ERR "interrupt handlers still exist on IRQ %u\n", irq);
856 WARN_ON(1);
857 }
859 /* Free the interrupt vector */
860 free_irq_vector(vector);
861 }
862 }
863 out:
864 spin_unlock(&iosapic_lock);
865 spin_unlock_irqrestore(&idesc->lock, flags);
866 }
868 /*
869 * ACPI calls this when it finds an entry for a platform interrupt.
870 * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
871 */
872 int __init
873 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
874 int iosapic_vector, u16 eid, u16 id,
875 unsigned long polarity, unsigned long trigger)
876 {
877 static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
878 unsigned char delivery;
879 int vector, mask = 0;
880 unsigned int dest = ((id << 8) | eid) & 0xffff;
882 switch (int_type) {
883 case ACPI_INTERRUPT_PMI:
884 vector = iosapic_vector;
885 /*
886 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
887 * we need to make sure the vector is available
888 */
889 iosapic_reassign_vector(vector);
890 delivery = IOSAPIC_PMI;
891 break;
892 case ACPI_INTERRUPT_INIT:
893 vector = assign_irq_vector(AUTO_ASSIGN);
894 if (vector < 0)
895 panic("%s: out of interrupt vectors!\n", __FUNCTION__);
896 delivery = IOSAPIC_INIT;
897 break;
898 case ACPI_INTERRUPT_CPEI:
899 vector = IA64_CPE_VECTOR;
900 delivery = IOSAPIC_LOWEST_PRIORITY;
901 mask = 1;
902 break;
903 default:
904 printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type);
905 return -1;
906 }
908 register_intr(gsi, vector, delivery, polarity, trigger);
910 printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
911 int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
912 int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
913 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
914 cpu_logical_id(dest), dest, vector);
916 set_rte(gsi, vector, dest, mask);
917 return vector;
918 }
921 /*
922 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
923 * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
924 */
925 void __init
926 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
927 unsigned long polarity,
928 unsigned long trigger)
929 {
930 int vector;
931 unsigned int dest = cpu_physical_id(smp_processor_id());
933 vector = isa_irq_to_vector(isa_irq);
935 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
937 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
938 isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
939 polarity == IOSAPIC_POL_HIGH ? "high" : "low",
940 cpu_logical_id(dest), dest, vector);
942 set_rte(gsi, vector, dest, 1);
943 }
945 void __init
946 iosapic_system_init (int system_pcat_compat)
947 {
948 int vector;
950 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
951 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
952 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); /* mark as unused */
953 }
955 pcat_compat = system_pcat_compat;
956 if (pcat_compat) {
957 /*
958 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
959 * enabled.
960 */
961 printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
962 outb(0xff, 0xA1);
963 outb(0xff, 0x21);
964 }
965 }
967 static inline int
968 iosapic_alloc (void)
969 {
970 int index;
972 for (index = 0; index < NR_IOSAPICS; index++)
973 if (!iosapic_lists[index].addr)
974 return index;
976 printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
977 return -1;
978 }
980 static inline void
981 iosapic_free (int index)
982 {
983 memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
984 }
986 static inline int
987 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
988 {
989 int index;
990 unsigned int gsi_end, base, end;
992 /* check gsi range */
993 gsi_end = gsi_base + ((ver >> 16) & 0xff);
994 for (index = 0; index < NR_IOSAPICS; index++) {
995 if (!iosapic_lists[index].addr)
996 continue;
998 base = iosapic_lists[index].gsi_base;
999 end = base + iosapic_lists[index].num_rte - 1;
1001 if (gsi_base < base && gsi_end < base)
1002 continue;/* OK */
1004 if (gsi_base > end && gsi_end > end)
1005 continue; /* OK */
1007 return -EBUSY;
1009 return 0;
1012 int __devinit
1013 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1015 int num_rte, err, index;
1016 unsigned int isa_irq, ver;
1017 char __iomem *addr;
1018 unsigned long flags;
1020 spin_lock_irqsave(&iosapic_lock, flags);
1022 addr = ioremap(phys_addr, 0);
1023 ver = iosapic_version(addr);
1025 if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1026 iounmap(addr);
1027 spin_unlock_irqrestore(&iosapic_lock, flags);
1028 return err;
1031 /*
1032 * The MAX_REDIR register holds the highest input pin
1033 * number (starting from 0).
1034 * We add 1 so that we can use it for number of pins (= RTEs)
1035 */
1036 num_rte = ((ver >> 16) & 0xff) + 1;
1038 index = iosapic_alloc();
1039 iosapic_lists[index].addr = addr;
1040 iosapic_lists[index].gsi_base = gsi_base;
1041 iosapic_lists[index].num_rte = num_rte;
1042 #ifdef CONFIG_NUMA
1043 iosapic_lists[index].node = MAX_NUMNODES;
1044 #endif
1046 spin_unlock_irqrestore(&iosapic_lock, flags);
1048 if ((gsi_base == 0) && pcat_compat) {
1049 /*
1050 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
1051 * get reprogrammed later on with data from the ACPI Interrupt Source
1052 * Override table.
1053 */
1054 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1055 iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);
1057 return 0;
1060 #ifdef CONFIG_HOTPLUG
1061 int
1062 iosapic_remove (unsigned int gsi_base)
1064 int index, err = 0;
1065 unsigned long flags;
1067 spin_lock_irqsave(&iosapic_lock, flags);
1069 index = find_iosapic(gsi_base);
1070 if (index < 0) {
1071 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1072 __FUNCTION__, gsi_base);
1073 goto out;
1076 if (iosapic_lists[index].rtes_inuse) {
1077 err = -EBUSY;
1078 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1079 __FUNCTION__, gsi_base);
1080 goto out;
1083 iounmap(iosapic_lists[index].addr);
1084 iosapic_free(index);
1086 out:
1087 spin_unlock_irqrestore(&iosapic_lock, flags);
1088 return err;
1090 #endif /* CONFIG_HOTPLUG */
1092 #ifdef CONFIG_NUMA
1093 void __devinit
1094 map_iosapic_to_node(unsigned int gsi_base, int node)
1096 int index;
1098 index = find_iosapic(gsi_base);
1099 if (index < 0) {
1100 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1101 __FUNCTION__, gsi_base);
1102 return;
1104 iosapic_lists[index].node = node;
1105 return;
1107 #endif
1109 static int __init iosapic_enable_kmalloc (void)
1111 iosapic_kmalloc_ok = 1;
1112 return 0;
1114 core_initcall (iosapic_enable_kmalloc);