ia64/xen-unstable

view stubdom/pciutils.patch @ 19828:180ae4bca33e

VT-d: don't disable VT-d engine in suspend for security purpose

force_iommu option is used to force enabling and using IOMMU for
security purpose. So when force_iommu is set, it shouldn't disable
VT-d engines in suspend.

Signed-off-by: Weidong Han <weidong.han@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jun 24 11:15:31 2009 +0100 (2009-06-24)
parents b3d827e63a09
children
line source
1 diff -urN pciutils-2.2.9.orig/lib/access.c pciutils-2.2.9/lib/access.c
2 --- pciutils-2.2.9.orig/lib/access.c 2007-02-06 11:59:43.000000000 +0000
3 +++ pciutils-2.2.9/lib/access.c 2008-06-30 19:07:09.713187000 +0100
4 @@ -57,6 +57,11 @@
5 #else
6 NULL,
7 #endif
8 +#ifdef PCI_OS_MINIOS
9 + &pm_minios,
10 +#else
11 + NULL,
12 +#endif
13 };
15 struct pci_access *
16 --- pciutils-2.2.9.orig/lib/pci.h 2006-09-09 13:46:06.000000000 +0100
17 +++ pciutils-2.2.9/lib/pci.h 2008-06-30 18:56:15.350111000 +0100
18 @@ -33,6 +33,7 @@
19 PCI_ACCESS_NBSD_LIBPCI, /* NetBSD libpci */
20 PCI_ACCESS_OBSD_DEVICE, /* OpenBSD /dev/pci */
21 PCI_ACCESS_DUMP, /* Dump file (params: filename) */
22 + PCI_ACCESS_MINIOS, /* MiniOS */
23 PCI_ACCESS_MAX
24 };
26 @@ -63,6 +64,7 @@
27 int fd_rw; /* proc: fd opened read-write */
28 struct pci_dev *cached_dev; /* proc: device the fd is for */
29 int fd_pos; /* proc: current position */
30 + void *minios;
31 };
33 /* Initialize PCI access */
34 --- pciutils-2.2.9.orig/lib/internal.h 2006-09-09 11:52:47.000000000 +0100
35 +++ pciutils-2.2.9/lib/internal.h 2008-07-01 10:46:24.968202000 +0100
36 @@ -37,4 +37,4 @@
38 extern struct pci_methods pm_intel_conf1, pm_intel_conf2, pm_linux_proc,
39 pm_fbsd_device, pm_aix_device, pm_nbsd_libpci, pm_obsd_device,
40 - pm_dump, pm_linux_sysfs;
41 + pm_dump, pm_linux_sysfs, pm_minios;
42 --- pciutils-2.2.9.orig/lib/Makefile 2007-10-19 13:41:34.000000000 +0100
43 +++ pciutils-2.2.9/lib/Makefile 2008-07-01 12:13:14.400525000 +0100
44 @@ -46,6 +46,12 @@
45 PCILIB=libpciutils.a
46 endif
48 +ifdef PCI_OS_MINIOS
49 +XEN_ROOT=../../..
50 +include $(XEN_ROOT)/Config.mk
51 +OBJS += minios.o
52 +endif
53 +
54 all: $(PCILIB) $(PCILIBPC)
56 $(PCILIB): $(OBJS)
57 --- pciutils-2.2.9.orig/lib/types.h 2007-09-03 09:44:15.000000000 +0100
58 +++ pciutils-2.2.9/lib/types.h 2008-07-01 12:17:08.396156000 +0100
59 @@ -17,9 +17,13 @@
60 typedef DWORD u32;
61 #elif defined(PCI_HAVE_STDINT_H)
62 #include <stdint.h>
63 +#ifdef PCI_OS_MINIOS
64 +#include <types.h>
65 +#else
66 typedef uint8_t u8;
67 typedef uint16_t u16;
68 typedef uint32_t u32;
69 +#endif
70 #else
71 typedef u_int8_t u8;
72 typedef u_int16_t u16;
73 --- pciutils-2.2.9.orig/lib/minios.c 1970-01-01 01:00:00.000000000 +0100
74 +++ pciutils-2.2.9/lib/minios.c 2008-07-01 12:31:40.554260000 +0100
75 @@ -0,0 +1,113 @@
76 +/*
77 + * The PCI Library -- MiniOS PCI frontend access
78 + *
79 + * Samuel Thibault <samuel.thibault@eu.citrix.com>, 2008
80 + *
81 + * Can be freely distributed and used under the terms of the GNU GPL.
82 + */
83 +
84 +#include <os.h>
85 +#include <pcifront.h>
86 +#include <xenbus.h>
87 +#include "internal.h"
88 +
89 +static int
90 +minios_detect(struct pci_access *a)
91 +{
92 + return 1;
93 +}
94 +
95 +static void
96 +minios_init(struct pci_access *a)
97 +{
98 + a->minios = init_pcifront(NULL);
99 + if (!a->minios)
100 + a->warning("minios_init open failed");
101 +}
102 +
103 +static void
104 +minios_cleanup(struct pci_access *a)
105 +{
106 + if (a->minios)
107 + shutdown_pcifront(a->minios);
108 +}
109 +
110 +static void
111 +minios_scan(struct pci_access *a)
112 +{
113 + if (!a->minios)
114 + return;
115 +
116 + void func(unsigned int domain, unsigned int bus, unsigned int slot, unsigned int fun)
117 + {
118 + struct pci_dev *d = pci_alloc_dev(a);
119 +
120 + d->domain = domain;
121 + d->bus = bus;
122 + d->dev = slot;
123 + d->func = fun;
124 +
125 + pci_link_dev(a, d);
126 + }
127 +
128 + pcifront_scan(a->minios, func);
129 +}
130 +
131 +static int
132 +minios_read(struct pci_dev *d, int pos, byte *buf, int len)
133 +{
134 + unsigned int val;
135 + switch (len) {
136 + case 1:
137 + if (pcifront_conf_read(d->access->minios, d->domain, d->bus, d->dev, d->func, pos, len, &val))
138 + return 0;
139 + * buf = val;
140 + return 1;
141 + case 2:
142 + if (pcifront_conf_read(d->access->minios, d->domain, d->bus, d->dev, d->func, pos, len, &val))
143 + return 0;
144 + *(u16 *) buf = cpu_to_le16((u16) val);
145 + return 1;
146 + case 4:
147 + if (pcifront_conf_read(d->access->minios, d->domain, d->bus, d->dev, d->func, pos, len, &val))
148 + return 0;
149 + *(u32 *) buf = cpu_to_le32((u32) val);
150 + return 1;
151 + default:
152 + return pci_generic_block_read(d, pos, buf, len);
153 + }
154 +}
155 +
156 +static int
157 +minios_write(struct pci_dev *d, int pos, byte *buf, int len)
158 +{
159 + unsigned int val;
160 + switch (len) {
161 + case 1:
162 + val = * buf;
163 + break;
164 + case 2:
165 + val = le16_to_cpu(*(u16 *) buf);
166 + break;
167 + case 4:
168 + val = le32_to_cpu(*(u32 *) buf);
169 + break;
170 + default:
171 + return pci_generic_block_write(d, pos, buf, len);
172 + }
173 + return !pcifront_conf_write(d->access->minios, d->domain, d->bus, d->dev, d->func, pos, len, val);
174 +}
175 +
176 +struct pci_methods pm_minios = {
177 + "MiniOS-device",
178 + NULL, /* config */
179 + minios_detect,
180 + minios_init,
181 + minios_cleanup,
182 + minios_scan,
183 + pci_generic_fill_info,
184 + minios_read,
185 + minios_write,
186 + NULL, /* dev_init */
187 + NULL /* dev_cleanup */
188 +};
189 --- pciutils-2.2.9/lib/generic.c 2007-02-06 12:00:05.000000000 +0000
190 +++ pciutils-2.2.9-mine/lib/generic.c 2008-07-01 19:13:52.289949000 +0100
191 @@ -74,6 +74,19 @@
192 pci_generic_scan_bus(a, busmap, 0);
193 }
195 +static u32 pci_size(u32 base, u32 maxbase, u32 mask)
196 +{
197 + u32 size = mask & maxbase;
198 + if (!size)
199 + return 0;
200 + size = (size & ~(size-1)) - 1;
201 +
202 + if (base == maxbase && ((base | size) & mask) != mask)
203 + return 0;
204 +
205 + return size + 1;
206 +}
207 +
208 int
209 pci_generic_fill_info(struct pci_dev *d, int flags)
210 {
211 @@ -114,23 +127,61 @@
212 if (!x || x == (u32) ~0)
213 continue;
214 if ((x & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
215 - d->base_addr[i] = x;
216 - else
217 + {
218 + d->base_addr[i] = x & PCI_BASE_ADDRESS_IO_MASK;
219 + if (flags & PCI_FILL_SIZES)
220 + {
221 + u32 size;
222 + pci_write_long(d, PCI_BASE_ADDRESS_0 + i*4, ~0);
223 + d->size[i] = pci_size(x, pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4), PCI_BASE_ADDRESS_IO_MASK);
224 + pci_write_long(d, PCI_BASE_ADDRESS_0 + i*4, x);
225 + }
226 + }
227 + else
228 {
229 if ((x & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != PCI_BASE_ADDRESS_MEM_TYPE_64)
230 - d->base_addr[i] = x;
231 + {
232 + d->base_addr[i] = x & PCI_BASE_ADDRESS_MEM_MASK;
233 + if (flags & PCI_FILL_SIZES)
234 + {
235 + u32 size;
236 + pci_write_long(d, PCI_BASE_ADDRESS_0 + i*4, ~0);
237 + d->size[i] = pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4);
238 + d->size[i] = pci_size(x, pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4), PCI_BASE_ADDRESS_MEM_MASK);
239 + pci_write_long(d, PCI_BASE_ADDRESS_0 + i*4, x);
240 + }
241 + }
242 else if (i >= cnt-1)
243 a->warning("%04x:%02x:%02x.%d: Invalid 64-bit address seen for BAR %d.", d->domain, d->bus, d->dev, d->func, i);
244 else
245 {
246 u32 y = pci_read_long(d, PCI_BASE_ADDRESS_0 + (++i)*4);
247 #ifdef PCI_HAVE_64BIT_ADDRESS
248 - d->base_addr[i-1] = x | (((pciaddr_t) y) << 32);
249 + d->base_addr[i-1] = (x | (((pciaddr_t) y) << 32)) & PCI_BASE_ADDRESS_MEM_MASK;
250 + if (flags & PCI_FILL_SIZES)
251 + {
252 + u32 size;
253 + pci_write_long(d, PCI_BASE_ADDRESS_0 + (i-1)*4, ~0);
254 + pci_write_long(d, PCI_BASE_ADDRESS_0 + i*4, ~0);
255 + d->size[i-1] = pci_size(y, pci_read_long(d, PCI_BASE_ADDRESS_0 + (i-1)*4) |
256 + pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4), 0xffffffff );
257 + pci_write_long(d, PCI_BASE_ADDRESS_0 + (i-1)*4, x);
258 + pci_write_long(d, PCI_BASE_ADDRESS_0 + i*4, y);
259 + }
260 #else
261 if (y)
262 a->warning("%04x:%02x:%02x.%d 64-bit device address ignored.", d->domain, d->bus, d->dev, d->func);
263 else
264 - d->base_addr[i-1] = x;
265 + {
266 + d->base_addr[i-1] = x & PCI_BASE_ADDRESS_MEM_MASK;
267 + if (flags & PCI_FILL_SIZES)
268 + {
269 + u32 size;
270 + pci_write_long(d, PCI_BASE_ADDRESS_0 + (i-1)*4, ~0);
271 + d->size[i-1] = pci_size(x, pci_read_long(d, PCI_BASE_ADDRESS_0 + (i-1)*4), PCI_BASE_ADDRESS_MEM_MASK);
272 + pci_write_long(d, PCI_BASE_ADDRESS_0 + (i-1)*4, x);
273 + }
274 + }
275 #endif
276 }
277 }
278 @@ -154,10 +205,19 @@
279 {
280 u32 u = pci_read_long(d, reg);
281 if (u != 0xffffffff)
282 - d->rom_base_addr = u;
283 + {
284 + d->rom_base_addr = u;
285 + if (flags & PCI_FILL_SIZES)
286 + {
287 + u32 size;
288 + pci_write_long(d, reg, ~0);
289 + d->rom_size = pci_read_long(d, reg);
290 + pci_write_long(d, reg, u);
291 + }
292 + }
293 }
294 }
295 - return flags & ~PCI_FILL_SIZES;
296 + return flags;
297 }
299 static int