ia64/xen-unstable

view xen/include/asm-x86/config.h @ 8700:1712b52e0074

Move MAX_DMADOM_PFN to asm/config.h.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon Jan 30 11:23:32 2006 +0100 (2006-01-30)
parents 1db05e589fa0
children f1b361b05bf3
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #elif defined(CONFIG_X86_PAE)
13 # define CONFIG_PAGING_LEVELS 3
14 #else
15 # define CONFIG_PAGING_LEVELS 2
16 #endif
18 #define CONFIG_X86 1
19 #define CONFIG_X86_HT 1
20 #define CONFIG_SHADOW 1
21 #define CONFIG_VMX 1
22 #define CONFIG_SMP 1
23 #define CONFIG_X86_LOCAL_APIC 1
24 #define CONFIG_X86_GOOD_APIC 1
25 #define CONFIG_X86_IO_APIC 1
26 #define CONFIG_HPET_TIMER 1
28 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
29 #define CONFIG_X86_L1_CACHE_SHIFT 7
31 #define CONFIG_ACPI 1
32 #define CONFIG_ACPI_BOOT 1
34 #define HZ 100
36 #define OPT_CONSOLE_STR "com1,vga"
38 #define NR_CPUS 32
40 /* Linkage for x86 */
41 #define __ALIGN .align 16,0x90
42 #define __ALIGN_STR ".align 16,0x90"
43 #ifdef __ASSEMBLY__
44 #define ALIGN __ALIGN
45 #define ALIGN_STR __ALIGN_STR
46 #define ENTRY(name) \
47 .globl name; \
48 ALIGN; \
49 name:
50 #endif
52 #define barrier() __asm__ __volatile__("": : :"memory")
54 #define NR_hypercalls 32
56 #ifndef NDEBUG
57 #define MEMORY_GUARD
58 #ifdef __x86_64__
59 #define STACK_ORDER 2
60 #endif
61 #endif
63 #ifndef STACK_ORDER
64 #define STACK_ORDER 1
65 #endif
66 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
68 #define MAX_DMADOM_PFN 0x7FFFFUL /* 31 addressable bits */
70 #ifndef __ASSEMBLY__
71 extern unsigned long _end; /* standard ELF symbol */
72 #endif /* __ASSEMBLY__ */
74 #define FORCE_CRASH() __asm__ __volatile__ ( "ud2" )
76 #if defined(__x86_64__)
78 #define CONFIG_X86_64 1
80 #define asmlinkage
82 #define XENHEAP_DEFAULT_MB (16)
84 #define PML4_ENTRY_BITS 39
85 #ifndef __ASSEMBLY__
86 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
87 #define PML4_ADDR(_slot) \
88 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
89 (_slot ## UL << PML4_ENTRY_BITS))
90 #else
91 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
92 #define PML4_ADDR(_slot) \
93 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
94 #endif
96 /*
97 * Memory layout:
98 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
99 * Guest-defined use.
100 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
101 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
102 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
103 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
104 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
105 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
106 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
107 * Read-only guest linear page table (GUEST ACCESSIBLE).
108 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
109 * Guest linear page table.
110 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
111 * Shadow linear page table.
112 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
113 * Per-domain mappings (e.g., GDT, LDT).
114 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
115 * Machine-to-phys translation table.
116 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
117 * Page-frame information array.
118 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
119 * ioremap()/fixmap area.
120 * 0xffff828c00000000 - 0xffff82ffffffffff [464GB, PML4:261]
121 * Reserved for future use.
122 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
123 * 1:1 direct mapping of all physical memory. Xen and its heap live here.
124 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
125 * Reserved for future use.
126 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
127 * Guest-defined use.
128 */
131 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
132 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
133 #define ROOT_PAGETABLE_XEN_SLOTS \
134 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
136 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
137 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
138 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
139 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
140 #define RO_MPT_VIRT_START (PML4_ADDR(256))
141 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
142 /* Slot 257: read-only guest-accessible linear page table. */
143 #define RO_LINEAR_PT_VIRT_START (PML4_ADDR(257))
144 #define RO_LINEAR_PT_VIRT_END (RO_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
145 /* Slot 258: linear page table (guest table). */
146 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
147 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
148 /* Slot 259: linear page table (shadow table). */
149 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
150 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
151 /* Slot 260: per-domain mappings. */
152 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
153 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
154 #define PERDOMAIN_MBYTES ((unsigned long)GDT_LDT_MBYTES)
155 /* Slot 261: machine-to-phys conversion table (16GB). */
156 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
157 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
158 /* Slot 261: page-frame information array (16GB). */
159 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
160 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
161 /* Slot 261: ioremap()/fixmap area (16GB). */
162 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
163 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
164 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
165 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
166 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
168 #define PGT_base_page_table PGT_l4_page_table
170 #define __HYPERVISOR_CS64 0xe010
171 #define __HYPERVISOR_CS32 0xe008
172 #define __HYPERVISOR_CS __HYPERVISOR_CS64
173 #define __HYPERVISOR_DS64 0x0000
174 #define __HYPERVISOR_DS32 0xe018
175 #define __HYPERVISOR_DS __HYPERVISOR_DS64
177 #define __GUEST_CS64 0xe033
178 #define __GUEST_CS32 0xe023
179 #define __GUEST_CS __GUEST_CS64
180 #define __GUEST_DS 0x0000
181 #define __GUEST_SS 0xe02b
183 /* For generic assembly code: use macros to define operation/operand sizes. */
184 #define __OS "q" /* Operation Suffix */
185 #define __OP "r" /* Operand Prefix */
186 #define __FIXUP_ALIGN ".align 8"
187 #define __FIXUP_WORD ".quad"
189 #elif defined(__i386__)
191 #define CONFIG_X86_32 1
192 #define CONFIG_DOMAIN_PAGE 1
194 #define asmlinkage __attribute__((regparm(0)))
196 /*
197 * Memory layout (high to low): SIZE PAE-SIZE
198 * ------ ------
199 * I/O remapping area ( 4MB)
200 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
201 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 4MB)
202 * Shadow linear pagetable ( 4MB) ( 8MB)
203 * Guest linear pagetable ( 4MB) ( 8MB)
204 * Machine-to-physical translation table [writable] ( 4MB) (16MB)
205 * Frame-info table (24MB) (96MB)
206 * * Start of guest inaccessible area
207 * Machine-to-physical translation table [read-only] ( 4MB)
208 * * Start of guest unmodifiable area
209 */
211 #define IOREMAP_MBYTES 4
212 #define DIRECTMAP_MBYTES 12
213 #define MAPCACHE_MBYTES 4
214 #define PERDOMAIN_MBYTES 8
216 #ifdef CONFIG_X86_PAE
217 # define LINEARPT_MBYTES 8
218 # define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
219 # define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
220 #else
221 # define LINEARPT_MBYTES 4
222 # define MACHPHYS_MBYTES 4
223 # define FRAMETABLE_MBYTES 24
224 #endif
226 #define IOREMAP_VIRT_END 0UL
227 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
228 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
229 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
230 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
231 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
232 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
233 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
234 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
235 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
236 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
237 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
238 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
239 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
240 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
241 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
242 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
243 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
245 #define XENHEAP_DEFAULT_MB (DIRECTMAP_MBYTES)
246 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
248 /* Maximum linear address accessible via guest memory segments. */
249 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
251 #ifdef CONFIG_X86_PAE
252 /* Hypervisor owns top 168MB of virtual address space. */
253 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
254 #else
255 /* Hypervisor owns top 64MB of virtual address space. */
256 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xFC000000)
257 #endif
259 #define L2_PAGETABLE_FIRST_XEN_SLOT \
260 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
261 #define L2_PAGETABLE_LAST_XEN_SLOT \
262 (~0UL >> L2_PAGETABLE_SHIFT)
263 #define L2_PAGETABLE_XEN_SLOTS \
264 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
266 #ifdef CONFIG_X86_PAE
267 # define PGT_base_page_table PGT_l3_page_table
268 #else
269 # define PGT_base_page_table PGT_l2_page_table
270 #endif
272 #define __HYPERVISOR_CS 0xe008
273 #define __HYPERVISOR_DS 0xe010
275 /* For generic assembly code: use macros to define operation/operand sizes. */
276 #define __OS "l" /* Operation Suffix */
277 #define __OP "e" /* Operand Prefix */
278 #define __FIXUP_ALIGN ".align 4"
279 #define __FIXUP_WORD ".long"
281 #endif /* __i386__ */
283 #ifndef __ASSEMBLY__
284 extern unsigned long xenheap_phys_end; /* user-configurable */
285 #endif
287 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
288 #define GDT_LDT_VCPU_SHIFT 5
289 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
290 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
291 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
292 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
294 /* The address of a particular VCPU's GDT or LDT. */
295 #define GDT_VIRT_START(v) \
296 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
297 #define LDT_VIRT_START(v) \
298 (GDT_VIRT_START(v) + (64*1024))
300 #define PDPT_L1_ENTRIES \
301 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
302 #define PDPT_L2_ENTRIES \
303 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
305 #if defined(__x86_64__)
306 #define ELFSIZE 64
307 #else
308 #define ELFSIZE 32
309 #endif
311 #endif /* __X86_CONFIG_H__ */