ia64/xen-unstable

view xen/arch/x86/hvm/vmx/vmx.c @ 8957:13e9fdaeed27

When thermal interrupt happened when vmx guest is running,
smp_thermal_interrupt() should be called.

Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Feb 22 09:54:20 2006 +0100 (2006-02-22)
parents 991c4d62d392
children 8fb4392c1d87
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <asm/current.h>
29 #include <asm/io.h>
30 #include <asm/shadow.h>
31 #include <asm/regs.h>
32 #include <asm/cpufeature.h>
33 #include <asm/processor.h>
34 #include <asm/types.h>
35 #include <asm/msr.h>
36 #include <asm/spinlock.h>
37 #include <asm/hvm/hvm.h>
38 #include <asm/hvm/support.h>
39 #include <asm/hvm/vmx/vmx.h>
40 #include <asm/hvm/vmx/vmcs.h>
41 #include <asm/shadow.h>
42 #if CONFIG_PAGING_LEVELS >= 3
43 #include <asm/shadow_64.h>
44 #endif
45 #include <public/sched.h>
46 #include <public/hvm/ioreq.h>
47 #include <asm/hvm/vpic.h>
48 #include <asm/hvm/vlapic.h>
50 static unsigned long trace_values[NR_CPUS][4];
51 #define TRACE_VMEXIT(index,value) trace_values[smp_processor_id()][index]=value
53 void vmx_final_setup_guest(struct vcpu *v)
54 {
55 v->arch.schedule_tail = arch_vmx_do_launch;
57 if ( v->vcpu_id == 0 )
58 {
59 struct domain *d = v->domain;
60 struct vcpu *vc;
62 /* Initialize monitor page table */
63 for_each_vcpu(d, vc)
64 vc->arch.monitor_table = mk_pagetable(0);
66 /*
67 * Required to do this once per domain
68 * XXX todo: add a seperate function to do these.
69 */
70 memset(&d->shared_info->evtchn_mask[0], 0xff,
71 sizeof(d->shared_info->evtchn_mask));
73 /* Put the domain in shadow mode even though we're going to be using
74 * the shared 1:1 page table initially. It shouldn't hurt */
75 shadow_mode_enable(d,
76 SHM_enable|SHM_refcounts|
77 SHM_translate|SHM_external|SHM_wr_pt_pte);
78 }
79 }
81 void vmx_relinquish_resources(struct vcpu *v)
82 {
83 struct hvm_virpit *vpit;
85 if (v->vcpu_id == 0) {
86 /* unmap IO shared page */
87 struct domain *d = v->domain;
88 if ( d->arch.hvm_domain.shared_page_va )
89 unmap_domain_page_global(
90 (void *)d->arch.hvm_domain.shared_page_va);
91 shadow_direct_map_clean(v);
92 }
94 vmx_request_clear_vmcs(v);
95 destroy_vmcs(&v->arch.hvm_vmx);
96 free_monitor_pagetable(v);
97 vpit = &v->domain->arch.hvm_domain.vpit;
98 kill_timer(&vpit->pit_timer);
99 kill_timer(&v->arch.hvm_vmx.hlt_timer);
100 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
101 {
102 kill_timer(&VLAPIC(v)->vlapic_timer);
103 xfree(VLAPIC(v));
104 }
105 }
107 #ifdef __x86_64__
108 static struct vmx_msr_state percpu_msr[NR_CPUS];
110 static u32 msr_data_index[VMX_MSR_COUNT] =
111 {
112 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
113 MSR_SYSCALL_MASK, MSR_EFER,
114 };
116 void vmx_save_segments(struct vcpu *v)
117 {
118 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
119 }
121 /*
122 * To avoid MSR save/restore at every VM exit/entry time, we restore
123 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
124 * are not modified once set for generic domains, we don't save them,
125 * but simply reset them to the values set at percpu_traps_init().
126 */
127 void vmx_load_msrs(void)
128 {
129 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
130 int i;
132 while ( host_state->flags )
133 {
134 i = find_first_set_bit(host_state->flags);
135 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
136 clear_bit(i, &host_state->flags);
137 }
138 }
140 static void vmx_save_init_msrs(void)
141 {
142 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
143 int i;
145 for ( i = 0; i < VMX_MSR_COUNT; i++ )
146 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
147 }
149 #define CASE_READ_MSR(address) \
150 case MSR_ ## address: \
151 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
152 break
154 #define CASE_WRITE_MSR(address) \
155 case MSR_ ## address: \
156 { \
157 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
158 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
159 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
160 } \
161 wrmsrl(MSR_ ## address, msr_content); \
162 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
163 } \
164 break
166 #define IS_CANO_ADDRESS(add) 1
167 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
168 {
169 u64 msr_content = 0;
170 struct vcpu *vc = current;
171 struct vmx_msr_state * msr = &vc->arch.hvm_vmx.msr_content;
172 switch(regs->ecx){
173 case MSR_EFER:
174 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
175 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content %llx\n", (unsigned long long)msr_content);
176 if (test_bit(VMX_CPU_STATE_LME_ENABLED,
177 &vc->arch.hvm_vmx.cpu_state))
178 msr_content |= 1 << _EFER_LME;
180 if (VMX_LONG_GUEST(vc))
181 msr_content |= 1 << _EFER_LMA;
182 break;
183 case MSR_FS_BASE:
184 if (!(VMX_LONG_GUEST(vc)))
185 /* XXX should it be GP fault */
186 domain_crash_synchronous();
187 __vmread(GUEST_FS_BASE, &msr_content);
188 break;
189 case MSR_GS_BASE:
190 if (!(VMX_LONG_GUEST(vc)))
191 domain_crash_synchronous();
192 __vmread(GUEST_GS_BASE, &msr_content);
193 break;
194 case MSR_SHADOW_GS_BASE:
195 msr_content = msr->shadow_gs;
196 break;
198 CASE_READ_MSR(STAR);
199 CASE_READ_MSR(LSTAR);
200 CASE_READ_MSR(CSTAR);
201 CASE_READ_MSR(SYSCALL_MASK);
202 default:
203 return 0;
204 }
205 HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n", msr_content);
206 regs->eax = msr_content & 0xffffffff;
207 regs->edx = msr_content >> 32;
208 return 1;
209 }
211 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
212 {
213 u64 msr_content = regs->eax | ((u64)regs->edx << 32);
214 struct vcpu *vc = current;
215 struct vmx_msr_state * msr = &vc->arch.hvm_vmx.msr_content;
216 struct vmx_msr_state * host_state =
217 &percpu_msr[smp_processor_id()];
219 HVM_DBG_LOG(DBG_LEVEL_1, " mode_do_msr_write msr %lx msr_content %lx\n",
220 regs->ecx, msr_content);
222 switch (regs->ecx){
223 case MSR_EFER:
224 if ((msr_content & EFER_LME) ^
225 test_bit(VMX_CPU_STATE_LME_ENABLED,
226 &vc->arch.hvm_vmx.cpu_state)){
227 if (test_bit(VMX_CPU_STATE_PG_ENABLED,
228 &vc->arch.hvm_vmx.cpu_state) ||
229 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
230 &vc->arch.hvm_vmx.cpu_state)){
231 vmx_inject_exception(vc, TRAP_gp_fault, 0);
232 }
233 }
234 if (msr_content & EFER_LME)
235 set_bit(VMX_CPU_STATE_LME_ENABLED,
236 &vc->arch.hvm_vmx.cpu_state);
237 /* No update for LME/LMA since it have no effect */
238 msr->msr_items[VMX_INDEX_MSR_EFER] =
239 msr_content;
240 if (msr_content & ~(EFER_LME | EFER_LMA)){
241 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
242 if (!test_bit(VMX_INDEX_MSR_EFER, &msr->flags)){
243 rdmsrl(MSR_EFER,
244 host_state->msr_items[VMX_INDEX_MSR_EFER]);
245 set_bit(VMX_INDEX_MSR_EFER, &host_state->flags);
246 set_bit(VMX_INDEX_MSR_EFER, &msr->flags);
247 }
248 }
249 break;
251 case MSR_FS_BASE:
252 case MSR_GS_BASE:
253 if (!(VMX_LONG_GUEST(vc)))
254 domain_crash_synchronous();
255 if (!IS_CANO_ADDRESS(msr_content)){
256 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
257 vmx_inject_exception(vc, TRAP_gp_fault, 0);
258 }
259 if (regs->ecx == MSR_FS_BASE)
260 __vmwrite(GUEST_FS_BASE, msr_content);
261 else
262 __vmwrite(GUEST_GS_BASE, msr_content);
263 break;
265 case MSR_SHADOW_GS_BASE:
266 if (!(VMX_LONG_GUEST(vc)))
267 domain_crash_synchronous();
268 vc->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
269 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
270 break;
272 CASE_WRITE_MSR(STAR);
273 CASE_WRITE_MSR(LSTAR);
274 CASE_WRITE_MSR(CSTAR);
275 CASE_WRITE_MSR(SYSCALL_MASK);
276 default:
277 return 0;
278 }
279 return 1;
280 }
282 void
283 vmx_restore_msrs(struct vcpu *v)
284 {
285 int i = 0;
286 struct vmx_msr_state *guest_state;
287 struct vmx_msr_state *host_state;
288 unsigned long guest_flags ;
290 guest_state = &v->arch.hvm_vmx.msr_content;;
291 host_state = &percpu_msr[smp_processor_id()];
293 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
294 guest_flags = guest_state->flags;
295 if (!guest_flags)
296 return;
298 while (guest_flags){
299 i = find_first_set_bit(guest_flags);
301 HVM_DBG_LOG(DBG_LEVEL_2,
302 "restore guest's index %d msr %lx with %lx\n",
303 i, (unsigned long) msr_data_index[i], (unsigned long) guest_state->msr_items[i]);
304 set_bit(i, &host_state->flags);
305 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
306 clear_bit(i, &guest_flags);
307 }
308 }
309 #else /* __i386__ */
310 #define vmx_save_init_msrs() ((void)0)
312 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs){
313 return 0;
314 }
315 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs){
316 return 0;
317 }
318 #endif
320 void stop_vmx(void)
321 {
322 if (read_cr4() & X86_CR4_VMXE)
323 __vmxoff();
324 }
326 int vmx_initialize_guest_resources(struct vcpu *v)
327 {
328 vmx_final_setup_guest(v);
329 return 1;
330 }
332 int vmx_relinquish_guest_resources(struct vcpu *v)
333 {
334 vmx_relinquish_resources(v);
335 return 1;
336 }
338 void vmx_migrate_timers(struct vcpu *v)
339 {
340 struct hvm_virpit *vpit = &(v->domain->arch.hvm_domain.vpit);
342 migrate_timer(&vpit->pit_timer, v->processor);
343 migrate_timer(&v->arch.hvm_vmx.hlt_timer, v->processor);
344 if ( hvm_apic_support(v->domain) && VLAPIC(v))
345 migrate_timer(&(VLAPIC(v)->vlapic_timer), v->processor);
346 }
348 void vmx_store_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
349 {
350 #if defined (__x86_64__)
351 __vmread(GUEST_RFLAGS, &regs->rflags);
352 __vmread(GUEST_SS_SELECTOR, &regs->ss);
353 __vmread(GUEST_CS_SELECTOR, &regs->cs);
354 __vmread(GUEST_DS_SELECTOR, &regs->ds);
355 __vmread(GUEST_ES_SELECTOR, &regs->es);
356 __vmread(GUEST_GS_SELECTOR, &regs->gs);
357 __vmread(GUEST_FS_SELECTOR, &regs->fs);
358 __vmread(GUEST_RIP, &regs->rip);
359 __vmread(GUEST_RSP, &regs->rsp);
360 #elif defined (__i386__)
361 __vmread(GUEST_RFLAGS, &regs->eflags);
362 __vmread(GUEST_SS_SELECTOR, &regs->ss);
363 __vmread(GUEST_CS_SELECTOR, &regs->cs);
364 __vmread(GUEST_DS_SELECTOR, &regs->ds);
365 __vmread(GUEST_ES_SELECTOR, &regs->es);
366 __vmread(GUEST_GS_SELECTOR, &regs->gs);
367 __vmread(GUEST_FS_SELECTOR, &regs->fs);
368 __vmread(GUEST_RIP, &regs->eip);
369 __vmread(GUEST_RSP, &regs->esp);
370 #else
371 #error Unsupported architecture
372 #endif
373 }
375 void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
376 {
377 #if defined (__x86_64__)
378 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
379 __vmwrite(GUEST_RSP, regs->rsp);
381 __vmwrite(GUEST_RFLAGS, regs->rflags);
382 if (regs->rflags & EF_TF)
383 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
384 else
385 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
387 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
388 __vmwrite(GUEST_RIP, regs->rip);
389 #elif defined (__i386__)
390 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
391 __vmwrite(GUEST_RSP, regs->esp);
393 __vmwrite(GUEST_RFLAGS, regs->eflags);
394 if (regs->eflags & EF_TF)
395 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
396 else
397 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
399 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
400 __vmwrite(GUEST_RIP, regs->eip);
401 #else
402 #error Unsupported architecture
403 #endif
404 }
406 void vmx_store_cpu_guest_ctrl_regs(struct vcpu *v, unsigned long crs[8])
407 {
408 __vmread(CR0_READ_SHADOW, &crs[0]);
409 __vmread(GUEST_CR3, &crs[3]);
410 __vmread(CR4_READ_SHADOW, &crs[4]);
411 }
413 void vmx_modify_guest_state(struct vcpu *v)
414 {
415 modify_vmcs(&v->arch.hvm_vmx, &v->arch.guest_context.user_regs);
416 }
418 int vmx_realmode(struct vcpu *v)
419 {
420 unsigned long rflags;
422 __vmread(GUEST_RFLAGS, &rflags);
423 return rflags & X86_EFLAGS_VM;
424 }
426 int vmx_instruction_length(struct vcpu *v)
427 {
428 unsigned long inst_len;
430 if (__vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len))
431 return 0;
432 return inst_len;
433 }
435 unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
436 {
437 switch ( num )
438 {
439 case 0:
440 return v->arch.hvm_vmx.cpu_cr0;
441 case 2:
442 return v->arch.hvm_vmx.cpu_cr2;
443 case 3:
444 return v->arch.hvm_vmx.cpu_cr3;
445 default:
446 BUG();
447 }
448 return 0; /* dummy */
449 }
451 extern long evtchn_send(int lport);
452 void do_nmi(struct cpu_user_regs *);
454 static int check_vmx_controls(ctrls, msr)
455 {
456 u32 vmx_msr_low, vmx_msr_high;
458 rdmsr(msr, vmx_msr_low, vmx_msr_high);
459 if (ctrls < vmx_msr_low || ctrls > vmx_msr_high) {
460 printk("Insufficient VMX capability 0x%x, "
461 "msr=0x%x,low=0x%8x,high=0x%x\n",
462 ctrls, msr, vmx_msr_low, vmx_msr_high);
463 return 0;
464 }
465 return 1;
466 }
468 int start_vmx(void)
469 {
470 struct vmcs_struct *vmcs;
471 u32 ecx;
472 u32 eax, edx;
473 u64 phys_vmcs; /* debugging */
475 /*
476 * Xen does not fill x86_capability words except 0.
477 */
478 ecx = cpuid_ecx(1);
479 boot_cpu_data.x86_capability[4] = ecx;
481 if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
482 return 0;
484 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
486 if (eax & IA32_FEATURE_CONTROL_MSR_LOCK) {
487 if ((eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0) {
488 printk("VMX disabled by Feature Control MSR.\n");
489 return 0;
490 }
491 }
492 else {
493 wrmsr(IA32_FEATURE_CONTROL_MSR,
494 IA32_FEATURE_CONTROL_MSR_LOCK |
495 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
496 }
498 if (!check_vmx_controls(MONITOR_PIN_BASED_EXEC_CONTROLS,
499 MSR_IA32_VMX_PINBASED_CTLS_MSR))
500 return 0;
501 if (!check_vmx_controls(MONITOR_CPU_BASED_EXEC_CONTROLS,
502 MSR_IA32_VMX_PROCBASED_CTLS_MSR))
503 return 0;
504 if (!check_vmx_controls(MONITOR_VM_EXIT_CONTROLS,
505 MSR_IA32_VMX_EXIT_CTLS_MSR))
506 return 0;
507 if (!check_vmx_controls(MONITOR_VM_ENTRY_CONTROLS,
508 MSR_IA32_VMX_ENTRY_CTLS_MSR))
509 return 0;
511 set_in_cr4(X86_CR4_VMXE); /* Enable VMXE */
513 if (!(vmcs = alloc_vmcs())) {
514 printk("Failed to allocate VMCS\n");
515 return 0;
516 }
518 phys_vmcs = (u64) virt_to_maddr(vmcs);
520 if (!(__vmxon(phys_vmcs))) {
521 printk("VMXON is done\n");
522 }
524 vmx_save_init_msrs();
526 /* Setup HVM interfaces */
527 hvm_funcs.disable = stop_vmx;
529 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
530 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
532 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
533 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
535 #ifdef __x86_64__
536 hvm_funcs.save_segments = vmx_save_segments;
537 hvm_funcs.load_msrs = vmx_load_msrs;
538 hvm_funcs.restore_msrs = vmx_restore_msrs;
539 #endif
541 hvm_funcs.store_cpu_guest_ctrl_regs = vmx_store_cpu_guest_ctrl_regs;
542 hvm_funcs.modify_guest_state = vmx_modify_guest_state;
544 hvm_funcs.realmode = vmx_realmode;
545 hvm_funcs.paging_enabled = vmx_paging_enabled;
546 hvm_funcs.instruction_length = vmx_instruction_length;
547 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
549 hvm_enabled = 1;
551 return 1;
552 }
554 /*
555 * Not all cases receive valid value in the VM-exit instruction length field.
556 */
557 #define __get_instruction_length(len) \
558 __vmread(VM_EXIT_INSTRUCTION_LEN, &(len)); \
559 if ((len) < 1 || (len) > 15) \
560 __hvm_bug(&regs);
562 static void inline __update_guest_eip(unsigned long inst_len)
563 {
564 unsigned long current_eip;
566 __vmread(GUEST_RIP, &current_eip);
567 __vmwrite(GUEST_RIP, current_eip + inst_len);
568 }
571 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
572 {
573 unsigned long gpa; /* FIXME: PAE */
574 int result;
576 #if 0 /* keep for debugging */
577 {
578 unsigned long eip;
580 __vmread(GUEST_RIP, &eip);
581 HVM_DBG_LOG(DBG_LEVEL_VMMU,
582 "vmx_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
583 va, eip, (unsigned long)regs->error_code);
584 }
585 #endif
587 if ( !vmx_paging_enabled(current) )
588 {
589 /* construct 1-to-1 direct mapping */
590 if ( shadow_direct_map_fault(va, regs) )
591 return 1;
593 handle_mmio(va, va);
594 TRACE_VMEXIT (2,2);
595 return 1;
596 }
597 gpa = gva_to_gpa(va);
599 /* Use 1:1 page table to identify MMIO address space */
600 if ( mmio_space(gpa) ){
601 struct vcpu *v = current;
602 /* No support for APIC */
603 if (!hvm_apic_support(v->domain) && gpa >= 0xFEC00000) {
604 u32 inst_len;
605 __vmread(VM_EXIT_INSTRUCTION_LEN, &(inst_len));
606 __update_guest_eip(inst_len);
607 return 1;
608 }
609 TRACE_VMEXIT (2,2);
610 handle_mmio(va, gpa);
611 return 1;
612 }
614 result = shadow_fault(va, regs);
615 TRACE_VMEXIT (2,result);
616 #if 0
617 if ( !result )
618 {
619 __vmread(GUEST_RIP, &eip);
620 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
621 }
622 #endif
624 return result;
625 }
627 static void vmx_do_no_device_fault(void)
628 {
629 unsigned long cr0;
630 struct vcpu *v = current;
632 setup_fpu(current);
633 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
635 /* Disable TS in guest CR0 unless the guest wants the exception too. */
636 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
637 if ( !(cr0 & X86_CR0_TS) )
638 {
639 __vmread_vcpu(v, GUEST_CR0, &cr0);
640 cr0 &= ~X86_CR0_TS;
641 __vmwrite(GUEST_CR0, cr0);
642 }
643 }
645 /* Reserved bits: [31:15], [12:11], [9], [6], [2:1] */
646 #define VMX_VCPU_CPUID_L1_RESERVED 0xffff9a46
648 static void vmx_vmexit_do_cpuid(unsigned long input, struct cpu_user_regs *regs)
649 {
650 unsigned int eax, ebx, ecx, edx;
651 unsigned long eip;
652 struct vcpu *v = current;
654 __vmread(GUEST_RIP, &eip);
656 HVM_DBG_LOG(DBG_LEVEL_1,
657 "do_cpuid: (eax) %lx, (ebx) %lx, (ecx) %lx, (edx) %lx,"
658 " (esi) %lx, (edi) %lx",
659 (unsigned long)regs->eax, (unsigned long)regs->ebx,
660 (unsigned long)regs->ecx, (unsigned long)regs->edx,
661 (unsigned long)regs->esi, (unsigned long)regs->edi);
663 cpuid(input, &eax, &ebx, &ecx, &edx);
665 if ( input == 1 )
666 {
667 if ( hvm_apic_support(v->domain) &&
668 !vlapic_global_enabled((VLAPIC(v))) )
669 clear_bit(X86_FEATURE_APIC, &edx);
671 #if CONFIG_PAGING_LEVELS < 3
672 clear_bit(X86_FEATURE_PAE, &edx);
673 clear_bit(X86_FEATURE_PSE, &edx);
674 clear_bit(X86_FEATURE_PSE36, &edx);
675 #else
676 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L2 )
677 {
678 if ( !v->domain->arch.hvm_domain.pae_enabled )
679 clear_bit(X86_FEATURE_PAE, &edx);
680 clear_bit(X86_FEATURE_PSE, &edx);
681 clear_bit(X86_FEATURE_PSE36, &edx);
682 }
683 #endif
685 /* Unsupportable for virtualised CPUs. */
686 ecx &= ~VMX_VCPU_CPUID_L1_RESERVED; /* mask off reserved bits */
687 clear_bit(X86_FEATURE_VMXE & 31, &ecx);
688 clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
689 }
690 #ifdef __i386__
691 else if ( input == 0x80000001 )
692 {
693 /* Mask feature for Intel ia32e or AMD long mode. */
694 clear_bit(X86_FEATURE_LM & 31, &edx);
695 }
696 #endif
698 regs->eax = (unsigned long) eax;
699 regs->ebx = (unsigned long) ebx;
700 regs->ecx = (unsigned long) ecx;
701 regs->edx = (unsigned long) edx;
703 HVM_DBG_LOG(DBG_LEVEL_1,
704 "vmx_vmexit_do_cpuid: eip: %lx, input: %lx, out:eax=%x, ebx=%x, ecx=%x, edx=%x",
705 eip, input, eax, ebx, ecx, edx);
707 }
709 #define CASE_GET_REG_P(REG, reg) \
710 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
712 static void vmx_dr_access (unsigned long exit_qualification, struct cpu_user_regs *regs)
713 {
714 unsigned int reg;
715 unsigned long *reg_p = 0;
716 struct vcpu *v = current;
717 unsigned long eip;
719 __vmread(GUEST_RIP, &eip);
721 reg = exit_qualification & DEBUG_REG_ACCESS_NUM;
723 HVM_DBG_LOG(DBG_LEVEL_1,
724 "vmx_dr_access : eip=%lx, reg=%d, exit_qualification = %lx",
725 eip, reg, exit_qualification);
727 switch(exit_qualification & DEBUG_REG_ACCESS_REG) {
728 CASE_GET_REG_P(EAX, eax);
729 CASE_GET_REG_P(ECX, ecx);
730 CASE_GET_REG_P(EDX, edx);
731 CASE_GET_REG_P(EBX, ebx);
732 CASE_GET_REG_P(EBP, ebp);
733 CASE_GET_REG_P(ESI, esi);
734 CASE_GET_REG_P(EDI, edi);
735 case REG_ESP:
736 break;
737 default:
738 __hvm_bug(regs);
739 }
741 switch (exit_qualification & DEBUG_REG_ACCESS_TYPE) {
742 case TYPE_MOV_TO_DR:
743 /* don't need to check the range */
744 if (reg != REG_ESP)
745 v->arch.guest_context.debugreg[reg] = *reg_p;
746 else {
747 unsigned long value;
748 __vmread(GUEST_RSP, &value);
749 v->arch.guest_context.debugreg[reg] = value;
750 }
751 break;
752 case TYPE_MOV_FROM_DR:
753 if (reg != REG_ESP)
754 *reg_p = v->arch.guest_context.debugreg[reg];
755 else {
756 __vmwrite(GUEST_RSP, v->arch.guest_context.debugreg[reg]);
757 }
758 break;
759 }
760 }
762 /*
763 * Invalidate the TLB for va. Invalidate the shadow page corresponding
764 * the address va.
765 */
766 static void vmx_vmexit_do_invlpg(unsigned long va)
767 {
768 unsigned long eip;
769 struct vcpu *v = current;
771 __vmread(GUEST_RIP, &eip);
773 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
774 eip, va);
776 /*
777 * We do the safest things first, then try to update the shadow
778 * copying from guest
779 */
780 shadow_invlpg(v, va);
781 }
783 static int check_for_null_selector(unsigned long eip)
784 {
785 unsigned char inst[MAX_INST_LEN];
786 unsigned long sel;
787 int i, inst_len;
788 int inst_copy_from_guest(unsigned char *, unsigned long, int);
790 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
791 memset(inst, 0, MAX_INST_LEN);
792 if (inst_copy_from_guest(inst, eip, inst_len) != inst_len) {
793 printf("check_for_null_selector: get guest instruction failed\n");
794 domain_crash_synchronous();
795 }
797 for (i = 0; i < inst_len; i++) {
798 switch (inst[i]) {
799 case 0xf3: /* REPZ */
800 case 0xf2: /* REPNZ */
801 case 0xf0: /* LOCK */
802 case 0x66: /* data32 */
803 case 0x67: /* addr32 */
804 continue;
805 case 0x2e: /* CS */
806 __vmread(GUEST_CS_SELECTOR, &sel);
807 break;
808 case 0x36: /* SS */
809 __vmread(GUEST_SS_SELECTOR, &sel);
810 break;
811 case 0x26: /* ES */
812 __vmread(GUEST_ES_SELECTOR, &sel);
813 break;
814 case 0x64: /* FS */
815 __vmread(GUEST_FS_SELECTOR, &sel);
816 break;
817 case 0x65: /* GS */
818 __vmread(GUEST_GS_SELECTOR, &sel);
819 break;
820 case 0x3e: /* DS */
821 /* FALLTHROUGH */
822 default:
823 /* DS is the default */
824 __vmread(GUEST_DS_SELECTOR, &sel);
825 }
826 return sel == 0 ? 1 : 0;
827 }
829 return 0;
830 }
832 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
833 unsigned long count, int size, long value,
834 int dir, int pvalid);
836 static void vmx_io_instruction(struct cpu_user_regs *regs,
837 unsigned long exit_qualification, unsigned long inst_len)
838 {
839 struct mmio_op *mmio_opp;
840 unsigned long eip, cs, eflags;
841 unsigned long port, size, dir;
842 int vm86;
844 mmio_opp = &current->arch.hvm_vcpu.mmio_op;
845 mmio_opp->instr = INSTR_PIO;
846 mmio_opp->flags = 0;
848 __vmread(GUEST_RIP, &eip);
849 __vmread(GUEST_CS_SELECTOR, &cs);
850 __vmread(GUEST_RFLAGS, &eflags);
851 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
853 HVM_DBG_LOG(DBG_LEVEL_1,
854 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
855 "exit_qualification = %lx",
856 vm86, cs, eip, exit_qualification);
858 if (test_bit(6, &exit_qualification))
859 port = (exit_qualification >> 16) & 0xFFFF;
860 else
861 port = regs->edx & 0xffff;
862 TRACE_VMEXIT(2, port);
863 size = (exit_qualification & 7) + 1;
864 dir = test_bit(3, &exit_qualification); /* direction */
866 if (test_bit(4, &exit_qualification)) { /* string instruction */
867 unsigned long addr, count = 1;
868 int sign = regs->eflags & EF_DF ? -1 : 1;
870 __vmread(GUEST_LINEAR_ADDRESS, &addr);
872 /*
873 * In protected mode, guest linear address is invalid if the
874 * selector is null.
875 */
876 if (!vm86 && check_for_null_selector(eip))
877 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
879 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
880 mmio_opp->flags |= REPZ;
881 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
882 }
884 /*
885 * Handle string pio instructions that cross pages or that
886 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
887 */
888 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
889 unsigned long value = 0;
891 mmio_opp->flags |= OVERLAP;
892 if (dir == IOREQ_WRITE)
893 hvm_copy(&value, addr, size, HVM_COPY_IN);
894 send_pio_req(regs, port, 1, size, value, dir, 0);
895 } else {
896 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
897 if (sign > 0)
898 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
899 else
900 count = (addr & ~PAGE_MASK) / size;
901 } else
902 __update_guest_eip(inst_len);
904 send_pio_req(regs, port, count, size, addr, dir, 1);
905 }
906 } else {
907 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
908 hvm_print_line(current, regs->eax); /* guest debug output */
910 __update_guest_eip(inst_len);
911 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
912 }
913 }
915 int
916 vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
917 {
918 unsigned long inst_len;
919 int error = 0;
921 error |= __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
922 error |= __vmread(GUEST_RIP, &c->eip);
923 c->eip += inst_len; /* skip transition instruction */
924 error |= __vmread(GUEST_RSP, &c->esp);
925 error |= __vmread(GUEST_RFLAGS, &c->eflags);
927 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
928 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
929 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
931 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
932 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
934 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
935 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
937 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
938 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
939 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
940 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
942 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
943 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
944 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
945 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
947 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
948 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
949 error |= __vmread(GUEST_ES_BASE, &c->es_base);
950 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
952 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
953 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
954 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
955 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
957 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
958 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
959 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
960 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
962 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
963 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
964 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
965 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
967 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
968 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
969 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
970 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
972 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
973 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
974 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
975 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
977 return !error;
978 }
980 int
981 vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
982 {
983 unsigned long mfn, old_cr4, old_base_mfn;
984 int error = 0;
986 error |= __vmwrite(GUEST_RIP, c->eip);
987 error |= __vmwrite(GUEST_RSP, c->esp);
988 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
990 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
992 if (!vmx_paging_enabled(v)) {
993 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
994 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
995 goto skip_cr3;
996 }
998 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
999 /*
1000 * This is simple TLB flush, implying the guest has
1001 * removed some translation or changed page attributes.
1002 * We simply invalidate the shadow.
1003 */
1004 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1005 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1006 printk("Invalid CR3 value=%x", c->cr3);
1007 domain_crash_synchronous();
1008 return 0;
1010 shadow_sync_all(v->domain);
1011 } else {
1012 /*
1013 * If different, make a shadow. Check if the PDBR is valid
1014 * first.
1015 */
1016 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1017 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1018 printk("Invalid CR3 value=%x", c->cr3);
1019 domain_crash_synchronous();
1020 return 0;
1022 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1023 if(!get_page(mfn_to_page(mfn), v->domain))
1024 return 0;
1025 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1026 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1027 if (old_base_mfn)
1028 put_page(mfn_to_page(old_base_mfn));
1029 /*
1030 * arch.shadow_table should now hold the next CR3 for shadow
1031 */
1032 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1033 update_pagetables(v);
1034 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1035 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1038 skip_cr3:
1040 error |= __vmread(CR4_READ_SHADOW, &old_cr4);
1041 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1042 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1044 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1045 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1047 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1048 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1050 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1051 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1052 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1053 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1055 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1056 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1057 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1058 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1060 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1061 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1062 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1063 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1065 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1066 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1067 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1068 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1070 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1071 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1072 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1073 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1075 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1076 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1077 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1078 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1080 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1081 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1082 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1083 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1085 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1086 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1087 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1088 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1090 return !error;
1093 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1095 int
1096 vmx_assist(struct vcpu *v, int mode)
1098 struct vmx_assist_context c;
1099 u32 magic;
1100 u32 cp;
1102 /* make sure vmxassist exists (this is not an error) */
1103 if (!hvm_copy(&magic, VMXASSIST_MAGIC_OFFSET, sizeof(magic), HVM_COPY_IN))
1104 return 0;
1105 if (magic != VMXASSIST_MAGIC)
1106 return 0;
1108 switch (mode) {
1109 /*
1110 * Transfer control to vmxassist.
1111 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1112 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1113 * by vmxassist and will transfer control to it.
1114 */
1115 case VMX_ASSIST_INVOKE:
1116 /* save the old context */
1117 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1118 goto error;
1119 if (cp != 0) {
1120 if (!vmx_world_save(v, &c))
1121 goto error;
1122 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_OUT))
1123 goto error;
1126 /* restore the new context, this should activate vmxassist */
1127 if (!hvm_copy(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp), HVM_COPY_IN))
1128 goto error;
1129 if (cp != 0) {
1130 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1131 goto error;
1132 if (!vmx_world_restore(v, &c))
1133 goto error;
1134 return 1;
1136 break;
1138 /*
1139 * Restore the VMXASSIST_OLD_CONTEXT that was saved by VMX_ASSIST_INVOKE
1140 * above.
1141 */
1142 case VMX_ASSIST_RESTORE:
1143 /* save the old context */
1144 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1145 goto error;
1146 if (cp != 0) {
1147 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1148 goto error;
1149 if (!vmx_world_restore(v, &c))
1150 goto error;
1151 return 1;
1153 break;
1156 error:
1157 printf("Failed to transfer to vmxassist\n");
1158 domain_crash_synchronous();
1159 return 0;
1162 static int vmx_set_cr0(unsigned long value)
1164 struct vcpu *v = current;
1165 unsigned long mfn;
1166 unsigned long eip;
1167 int paging_enabled;
1168 unsigned long vm_entry_value;
1169 unsigned long old_cr0;
1171 /*
1172 * CR0: We don't want to lose PE and PG.
1173 */
1174 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1175 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1177 /* TS cleared? Then initialise FPU now. */
1178 if ( !(value & X86_CR0_TS) )
1180 setup_fpu(v);
1181 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1184 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1185 __vmwrite(CR0_READ_SHADOW, value);
1187 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1189 if ((value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled) {
1190 /*
1191 * The guest CR3 must be pointing to the guest physical.
1192 */
1193 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1194 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1195 !get_page(mfn_to_page(mfn), v->domain) )
1197 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1198 domain_crash_synchronous(); /* need to take a clean path */
1201 #if defined(__x86_64__)
1202 if (test_bit(VMX_CPU_STATE_LME_ENABLED,
1203 &v->arch.hvm_vmx.cpu_state) &&
1204 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
1205 &v->arch.hvm_vmx.cpu_state)){
1206 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enable\n");
1207 vmx_inject_exception(v, TRAP_gp_fault, 0);
1209 if (test_bit(VMX_CPU_STATE_LME_ENABLED,
1210 &v->arch.hvm_vmx.cpu_state)){
1211 /* Here the PAE is should to be opened */
1212 HVM_DBG_LOG(DBG_LEVEL_1, "Enable the Long mode\n");
1213 set_bit(VMX_CPU_STATE_LMA_ENABLED,
1214 &v->arch.hvm_vmx.cpu_state);
1215 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1216 vm_entry_value |= VM_ENTRY_CONTROLS_IA32E_MODE;
1217 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1219 #if CONFIG_PAGING_LEVELS >= 4
1220 if(!shadow_set_guest_paging_levels(v->domain, 4)) {
1221 printk("Unsupported guest paging levels\n");
1222 domain_crash_synchronous(); /* need to take a clean path */
1224 #endif
1226 else
1227 #endif /* __x86_64__ */
1229 #if CONFIG_PAGING_LEVELS >= 3
1230 if(!shadow_set_guest_paging_levels(v->domain, 2)) {
1231 printk("Unsupported guest paging levels\n");
1232 domain_crash_synchronous(); /* need to take a clean path */
1234 #endif
1238 unsigned long crn;
1239 /* update CR4's PAE if needed */
1240 __vmread(GUEST_CR4, &crn);
1241 if ( (!(crn & X86_CR4_PAE)) &&
1242 test_bit(VMX_CPU_STATE_PAE_ENABLED,
1243 &v->arch.hvm_vmx.cpu_state) )
1245 HVM_DBG_LOG(DBG_LEVEL_1, "enable PAE on cr4\n");
1246 __vmwrite(GUEST_CR4, crn | X86_CR4_PAE);
1250 /*
1251 * Now arch.guest_table points to machine physical.
1252 */
1253 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1254 update_pagetables(v);
1256 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1257 (unsigned long) (mfn << PAGE_SHIFT));
1259 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1260 /*
1261 * arch->shadow_table should hold the next CR3 for shadow
1262 */
1263 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1264 v->arch.hvm_vmx.cpu_cr3, mfn);
1267 if(!((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled)
1268 if(v->arch.hvm_vmx.cpu_cr3) {
1269 put_page(mfn_to_page(get_mfn_from_gpfn(
1270 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1271 v->arch.guest_table = mk_pagetable(0);
1274 /*
1275 * VMX does not implement real-mode virtualization. We emulate
1276 * real-mode by performing a world switch to VMXAssist whenever
1277 * a partition disables the CR0.PE bit.
1278 */
1279 if ((value & X86_CR0_PE) == 0) {
1280 if ( value & X86_CR0_PG ) {
1281 /* inject GP here */
1282 vmx_inject_exception(v, TRAP_gp_fault, 0);
1283 return 0;
1284 } else {
1285 /*
1286 * Disable paging here.
1287 * Same to PE == 1 && PG == 0
1288 */
1289 if (test_bit(VMX_CPU_STATE_LMA_ENABLED,
1290 &v->arch.hvm_vmx.cpu_state)){
1291 clear_bit(VMX_CPU_STATE_LMA_ENABLED,
1292 &v->arch.hvm_vmx.cpu_state);
1293 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1294 vm_entry_value &= ~VM_ENTRY_CONTROLS_IA32E_MODE;
1295 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1299 clear_all_shadow_status(v->domain);
1300 if (vmx_assist(v, VMX_ASSIST_INVOKE)) {
1301 set_bit(VMX_CPU_STATE_ASSIST_ENABLED, &v->arch.hvm_vmx.cpu_state);
1302 __vmread(GUEST_RIP, &eip);
1303 HVM_DBG_LOG(DBG_LEVEL_1,
1304 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1305 return 0; /* do not update eip! */
1307 } else if (test_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1308 &v->arch.hvm_vmx.cpu_state)) {
1309 __vmread(GUEST_RIP, &eip);
1310 HVM_DBG_LOG(DBG_LEVEL_1,
1311 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1312 if (vmx_assist(v, VMX_ASSIST_RESTORE)) {
1313 clear_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1314 &v->arch.hvm_vmx.cpu_state);
1315 __vmread(GUEST_RIP, &eip);
1316 HVM_DBG_LOG(DBG_LEVEL_1,
1317 "Restoring to %%eip 0x%lx\n", eip);
1318 return 0; /* do not update eip! */
1322 return 1;
1325 #define CASE_GET_REG(REG, reg) \
1326 case REG_ ## REG: value = regs->reg; break
1328 #define CASE_EXTEND_SET_REG \
1329 CASE_EXTEND_REG(S)
1330 #define CASE_EXTEND_GET_REG \
1331 CASE_EXTEND_REG(G)
1333 #ifdef __i386__
1334 #define CASE_EXTEND_REG(T)
1335 #else
1336 #define CASE_EXTEND_REG(T) \
1337 CASE_ ## T ## ET_REG(R8, r8); \
1338 CASE_ ## T ## ET_REG(R9, r9); \
1339 CASE_ ## T ## ET_REG(R10, r10); \
1340 CASE_ ## T ## ET_REG(R11, r11); \
1341 CASE_ ## T ## ET_REG(R12, r12); \
1342 CASE_ ## T ## ET_REG(R13, r13); \
1343 CASE_ ## T ## ET_REG(R14, r14); \
1344 CASE_ ## T ## ET_REG(R15, r15);
1345 #endif
1348 /*
1349 * Write to control registers
1350 */
1351 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1353 unsigned long value;
1354 unsigned long old_cr;
1355 struct vcpu *v = current;
1357 switch (gp) {
1358 CASE_GET_REG(EAX, eax);
1359 CASE_GET_REG(ECX, ecx);
1360 CASE_GET_REG(EDX, edx);
1361 CASE_GET_REG(EBX, ebx);
1362 CASE_GET_REG(EBP, ebp);
1363 CASE_GET_REG(ESI, esi);
1364 CASE_GET_REG(EDI, edi);
1365 CASE_EXTEND_GET_REG
1366 case REG_ESP:
1367 __vmread(GUEST_RSP, &value);
1368 break;
1369 default:
1370 printk("invalid gp: %d\n", gp);
1371 __hvm_bug(regs);
1374 HVM_DBG_LOG(DBG_LEVEL_1, "mov_to_cr: CR%d, value = %lx,", cr, value);
1375 HVM_DBG_LOG(DBG_LEVEL_1, "current = %lx,", (unsigned long) current);
1377 switch(cr) {
1378 case 0:
1380 return vmx_set_cr0(value);
1382 case 3:
1384 unsigned long old_base_mfn, mfn;
1386 /*
1387 * If paging is not enabled yet, simply copy the value to CR3.
1388 */
1389 if (!vmx_paging_enabled(v)) {
1390 v->arch.hvm_vmx.cpu_cr3 = value;
1391 break;
1394 /*
1395 * We make a new one if the shadow does not exist.
1396 */
1397 if (value == v->arch.hvm_vmx.cpu_cr3) {
1398 /*
1399 * This is simple TLB flush, implying the guest has
1400 * removed some translation or changed page attributes.
1401 * We simply invalidate the shadow.
1402 */
1403 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1404 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1405 __hvm_bug(regs);
1406 shadow_sync_all(v->domain);
1407 } else {
1408 /*
1409 * If different, make a shadow. Check if the PDBR is valid
1410 * first.
1411 */
1412 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1413 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1414 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1415 !get_page(mfn_to_page(mfn), v->domain) )
1417 printk("Invalid CR3 value=%lx", value);
1418 domain_crash_synchronous(); /* need to take a clean path */
1420 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1421 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1422 if (old_base_mfn)
1423 put_page(mfn_to_page(old_base_mfn));
1424 /*
1425 * arch.shadow_table should now hold the next CR3 for shadow
1426 */
1427 #if CONFIG_PAGING_LEVELS >= 3
1428 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L3 )
1429 shadow_sync_all(v->domain);
1430 #endif
1432 v->arch.hvm_vmx.cpu_cr3 = value;
1433 update_pagetables(v);
1434 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1435 value);
1436 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1438 break;
1440 case 4: /* CR4 */
1442 unsigned long old_cr4;
1444 __vmread(CR4_READ_SHADOW, &old_cr4);
1446 if ( value & X86_CR4_PAE && !(old_cr4 & X86_CR4_PAE) )
1448 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1450 if ( vmx_pgbit_test(v) )
1452 /* The guest is 32 bit. */
1453 #if CONFIG_PAGING_LEVELS >= 4
1454 unsigned long mfn, old_base_mfn;
1456 if( !shadow_set_guest_paging_levels(v->domain, 3) )
1458 printk("Unsupported guest paging levels\n");
1459 domain_crash_synchronous(); /* need to take a clean path */
1462 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1463 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1464 !get_page(mfn_to_page(mfn), v->domain) )
1466 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1467 domain_crash_synchronous(); /* need to take a clean path */
1470 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1471 if ( old_base_mfn )
1472 put_page(mfn_to_page(old_base_mfn));
1474 /*
1475 * Now arch.guest_table points to machine physical.
1476 */
1478 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1479 update_pagetables(v);
1481 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1482 (unsigned long) (mfn << PAGE_SHIFT));
1484 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1486 /*
1487 * arch->shadow_table should hold the next CR3 for shadow
1488 */
1490 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1491 v->arch.hvm_vmx.cpu_cr3, mfn);
1492 #endif
1494 else
1496 /* The guest is 64 bit. */
1497 #if CONFIG_PAGING_LEVELS >= 4
1498 if ( !shadow_set_guest_paging_levels(v->domain, 4) )
1500 printk("Unsupported guest paging levels\n");
1501 domain_crash_synchronous(); /* need to take a clean path */
1503 #endif
1506 else if ( value & X86_CR4_PAE )
1507 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1508 else
1510 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED, &v->arch.hvm_vmx.cpu_state) )
1511 vmx_inject_exception(v, TRAP_gp_fault, 0);
1513 clear_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1516 __vmread(CR4_READ_SHADOW, &old_cr);
1517 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1518 __vmwrite(CR4_READ_SHADOW, value);
1520 /*
1521 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1522 * all TLB entries except global entries.
1523 */
1524 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1525 shadow_sync_all(v->domain);
1527 break;
1529 default:
1530 printk("invalid cr: %d\n", gp);
1531 __hvm_bug(regs);
1534 return 1;
1537 #define CASE_SET_REG(REG, reg) \
1538 case REG_ ## REG: \
1539 regs->reg = value; \
1540 break
1542 /*
1543 * Read from control registers. CR0 and CR4 are read from the shadow.
1544 */
1545 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1547 unsigned long value;
1548 struct vcpu *v = current;
1550 if (cr != 3)
1551 __hvm_bug(regs);
1553 value = (unsigned long) v->arch.hvm_vmx.cpu_cr3;
1555 switch (gp) {
1556 CASE_SET_REG(EAX, eax);
1557 CASE_SET_REG(ECX, ecx);
1558 CASE_SET_REG(EDX, edx);
1559 CASE_SET_REG(EBX, ebx);
1560 CASE_SET_REG(EBP, ebp);
1561 CASE_SET_REG(ESI, esi);
1562 CASE_SET_REG(EDI, edi);
1563 CASE_EXTEND_SET_REG
1564 case REG_ESP:
1565 __vmwrite(GUEST_RSP, value);
1566 regs->esp = value;
1567 break;
1568 default:
1569 printk("invalid gp: %d\n", gp);
1570 __hvm_bug(regs);
1573 HVM_DBG_LOG(DBG_LEVEL_VMMU, "mov_from_cr: CR%d, value = %lx,", cr, value);
1576 static int vmx_cr_access(unsigned long exit_qualification, struct cpu_user_regs *regs)
1578 unsigned int gp, cr;
1579 unsigned long value;
1580 struct vcpu *v = current;
1582 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1583 case TYPE_MOV_TO_CR:
1584 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1585 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1586 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1587 TRACE_VMEXIT(2,cr);
1588 TRACE_VMEXIT(3,gp);
1589 return mov_to_cr(gp, cr, regs);
1590 case TYPE_MOV_FROM_CR:
1591 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1592 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1593 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1594 TRACE_VMEXIT(2,cr);
1595 TRACE_VMEXIT(3,gp);
1596 mov_from_cr(cr, gp, regs);
1597 break;
1598 case TYPE_CLTS:
1599 TRACE_VMEXIT(1,TYPE_CLTS);
1601 /* We initialise the FPU now, to avoid needing another vmexit. */
1602 setup_fpu(v);
1603 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1605 __vmread_vcpu(v, GUEST_CR0, &value);
1606 value &= ~X86_CR0_TS; /* clear TS */
1607 __vmwrite(GUEST_CR0, value);
1609 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1610 value &= ~X86_CR0_TS; /* clear TS */
1611 __vmwrite(CR0_READ_SHADOW, value);
1612 break;
1613 case TYPE_LMSW:
1614 TRACE_VMEXIT(1,TYPE_LMSW);
1615 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1616 value = (value & ~0xF) |
1617 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1618 return vmx_set_cr0(value);
1619 break;
1620 default:
1621 __hvm_bug(regs);
1622 break;
1624 return 1;
1627 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1629 u64 msr_content = 0;
1630 struct vcpu *v = current;
1632 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1633 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1634 (unsigned long)regs->edx);
1635 switch (regs->ecx) {
1636 case MSR_IA32_TIME_STAMP_COUNTER:
1638 struct hvm_virpit *vpit;
1640 rdtscll(msr_content);
1641 vpit = &(v->domain->arch.hvm_domain.vpit);
1642 msr_content += vpit->shift;
1643 break;
1645 case MSR_IA32_SYSENTER_CS:
1646 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1647 break;
1648 case MSR_IA32_SYSENTER_ESP:
1649 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1650 break;
1651 case MSR_IA32_SYSENTER_EIP:
1652 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1653 break;
1654 case MSR_IA32_APICBASE:
1655 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1656 break;
1657 default:
1658 if(long_mode_do_msr_read(regs))
1659 return;
1660 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1661 break;
1664 regs->eax = msr_content & 0xFFFFFFFF;
1665 regs->edx = msr_content >> 32;
1667 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1668 "ecx=%lx, eax=%lx, edx=%lx",
1669 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1670 (unsigned long)regs->edx);
1673 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1675 u64 msr_content;
1676 struct vcpu *v = current;
1678 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1679 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1680 (unsigned long)regs->edx);
1682 msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
1684 switch (regs->ecx) {
1685 case MSR_IA32_TIME_STAMP_COUNTER:
1687 struct hvm_virpit *vpit;
1688 u64 host_tsc, drift;
1690 rdtscll(host_tsc);
1691 vpit = &(v->domain->arch.hvm_domain.vpit);
1692 drift = v->arch.hvm_vmx.tsc_offset - vpit->shift;
1693 vpit->shift = msr_content - host_tsc;
1694 v->arch.hvm_vmx.tsc_offset = vpit->shift + drift;
1695 __vmwrite(TSC_OFFSET, vpit->shift);
1697 #if defined (__i386__)
1698 __vmwrite(TSC_OFFSET_HIGH, ((vpit->shift)>>32));
1699 #endif
1700 break;
1702 case MSR_IA32_SYSENTER_CS:
1703 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1704 break;
1705 case MSR_IA32_SYSENTER_ESP:
1706 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1707 break;
1708 case MSR_IA32_SYSENTER_EIP:
1709 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1710 break;
1711 case MSR_IA32_APICBASE:
1712 vlapic_msr_set(VLAPIC(v), msr_content);
1713 break;
1714 default:
1715 long_mode_do_msr_write(regs);
1716 break;
1719 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1720 "ecx=%lx, eax=%lx, edx=%lx",
1721 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1722 (unsigned long)regs->edx);
1725 /*
1726 * Need to use this exit to reschedule
1727 */
1728 void vmx_vmexit_do_hlt(void)
1730 struct vcpu *v=current;
1731 struct hvm_virpit *vpit = &(v->domain->arch.hvm_domain.vpit);
1732 s_time_t next_pit=-1,next_wakeup;
1734 if ( !v->vcpu_id )
1735 next_pit = get_pit_scheduled(v,vpit);
1736 next_wakeup = get_apictime_scheduled(v);
1737 if ( (next_pit != -1 && next_pit < next_wakeup) || next_wakeup == -1 )
1738 next_wakeup = next_pit;
1739 if ( next_wakeup != - 1 )
1740 set_timer(&current->arch.hvm_vmx.hlt_timer, next_wakeup);
1741 hvm_safe_block();
1744 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
1746 unsigned int vector;
1747 int error;
1749 asmlinkage void do_IRQ(struct cpu_user_regs *);
1750 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
1751 fastcall void smp_event_check_interrupt(void);
1752 fastcall void smp_invalidate_interrupt(void);
1753 fastcall void smp_call_function_interrupt(void);
1754 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
1755 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
1756 #ifdef CONFIG_X86_MCE_P4THERMAL
1757 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
1758 #endif
1760 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1761 && !(vector & INTR_INFO_VALID_MASK))
1762 __hvm_bug(regs);
1764 vector &= 0xff;
1765 local_irq_disable();
1767 switch(vector) {
1768 case LOCAL_TIMER_VECTOR:
1769 smp_apic_timer_interrupt(regs);
1770 break;
1771 case EVENT_CHECK_VECTOR:
1772 smp_event_check_interrupt();
1773 break;
1774 case INVALIDATE_TLB_VECTOR:
1775 smp_invalidate_interrupt();
1776 break;
1777 case CALL_FUNCTION_VECTOR:
1778 smp_call_function_interrupt();
1779 break;
1780 case SPURIOUS_APIC_VECTOR:
1781 smp_spurious_interrupt(regs);
1782 break;
1783 case ERROR_APIC_VECTOR:
1784 smp_error_interrupt(regs);
1785 break;
1786 #ifdef CONFIG_X86_MCE_P4THERMAL
1787 case THERMAL_APIC_VECTOR:
1788 smp_thermal_interrupt(regs);
1789 break;
1790 #endif
1791 default:
1792 regs->entry_vector = vector;
1793 do_IRQ(regs);
1794 break;
1798 #if defined (__x86_64__)
1799 void store_cpu_user_regs(struct cpu_user_regs *regs)
1801 __vmread(GUEST_SS_SELECTOR, &regs->ss);
1802 __vmread(GUEST_RSP, &regs->rsp);
1803 __vmread(GUEST_RFLAGS, &regs->rflags);
1804 __vmread(GUEST_CS_SELECTOR, &regs->cs);
1805 __vmread(GUEST_DS_SELECTOR, &regs->ds);
1806 __vmread(GUEST_ES_SELECTOR, &regs->es);
1807 __vmread(GUEST_RIP, &regs->rip);
1809 #elif defined (__i386__)
1810 void store_cpu_user_regs(struct cpu_user_regs *regs)
1812 __vmread(GUEST_SS_SELECTOR, &regs->ss);
1813 __vmread(GUEST_RSP, &regs->esp);
1814 __vmread(GUEST_RFLAGS, &regs->eflags);
1815 __vmread(GUEST_CS_SELECTOR, &regs->cs);
1816 __vmread(GUEST_DS_SELECTOR, &regs->ds);
1817 __vmread(GUEST_ES_SELECTOR, &regs->es);
1818 __vmread(GUEST_RIP, &regs->eip);
1820 #endif
1822 #ifdef XEN_DEBUGGER
1823 void save_cpu_user_regs(struct cpu_user_regs *regs)
1825 __vmread(GUEST_SS_SELECTOR, &regs->xss);
1826 __vmread(GUEST_RSP, &regs->esp);
1827 __vmread(GUEST_RFLAGS, &regs->eflags);
1828 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
1829 __vmread(GUEST_RIP, &regs->eip);
1831 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
1832 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
1833 __vmread(GUEST_ES_SELECTOR, &regs->xes);
1834 __vmread(GUEST_DS_SELECTOR, &regs->xds);
1837 void restore_cpu_user_regs(struct cpu_user_regs *regs)
1839 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
1840 __vmwrite(GUEST_RSP, regs->esp);
1841 __vmwrite(GUEST_RFLAGS, regs->eflags);
1842 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
1843 __vmwrite(GUEST_RIP, regs->eip);
1845 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
1846 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
1847 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
1848 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
1850 #endif
1852 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs regs)
1854 unsigned int exit_reason, idtv_info_field;
1855 unsigned long exit_qualification, eip, inst_len = 0;
1856 struct vcpu *v = current;
1857 int error;
1859 if ((error = __vmread(VM_EXIT_REASON, &exit_reason)))
1860 __hvm_bug(&regs);
1862 perfc_incra(vmexits, exit_reason);
1864 __vmread(IDT_VECTORING_INFO_FIELD, &idtv_info_field);
1865 if (idtv_info_field & INTR_INFO_VALID_MASK) {
1866 __vmwrite(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
1868 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1869 if (inst_len >= 1 && inst_len <= 15)
1870 __vmwrite(VM_ENTRY_INSTRUCTION_LEN, inst_len);
1872 if (idtv_info_field & 0x800) { /* valid error code */
1873 unsigned long error_code;
1874 __vmread(IDT_VECTORING_ERROR_CODE, &error_code);
1875 __vmwrite(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1878 HVM_DBG_LOG(DBG_LEVEL_1, "idtv_info_field=%x", idtv_info_field);
1881 /* don't bother H/W interrutps */
1882 if (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT &&
1883 exit_reason != EXIT_REASON_VMCALL &&
1884 exit_reason != EXIT_REASON_IO_INSTRUCTION)
1885 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
1887 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
1888 printk("Failed vm entry\n");
1889 domain_crash_synchronous();
1890 return;
1894 __vmread(GUEST_RIP, &eip);
1895 TRACE_3D(TRC_VMX_VMEXIT, v->domain->domain_id, eip, exit_reason);
1896 TRACE_VMEXIT(0,exit_reason);
1899 switch (exit_reason) {
1900 case EXIT_REASON_EXCEPTION_NMI:
1902 /*
1903 * We don't set the software-interrupt exiting (INT n).
1904 * (1) We can get an exception (e.g. #PG) in the guest, or
1905 * (2) NMI
1906 */
1907 int error;
1908 unsigned int vector;
1909 unsigned long va;
1911 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1912 || !(vector & INTR_INFO_VALID_MASK))
1913 __hvm_bug(&regs);
1914 vector &= 0xff;
1916 TRACE_VMEXIT(1,vector);
1917 perfc_incra(cause_vector, vector);
1919 TRACE_3D(TRC_VMX_VECTOR, v->domain->domain_id, eip, vector);
1920 switch (vector) {
1921 #ifdef XEN_DEBUGGER
1922 case TRAP_debug:
1924 save_cpu_user_regs(&regs);
1925 pdb_handle_exception(1, &regs, 1);
1926 restore_cpu_user_regs(&regs);
1927 break;
1929 case TRAP_int3:
1931 save_cpu_user_regs(&regs);
1932 pdb_handle_exception(3, &regs, 1);
1933 restore_cpu_user_regs(&regs);
1934 break;
1936 #else
1937 case TRAP_debug:
1939 void store_cpu_user_regs(struct cpu_user_regs *regs);
1941 store_cpu_user_regs(&regs);
1942 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS, PENDING_DEBUG_EXC_BS);
1944 domain_pause_for_debugger();
1946 break;
1948 #endif
1949 case TRAP_no_device:
1951 vmx_do_no_device_fault();
1952 break;
1954 case TRAP_page_fault:
1956 __vmread(EXIT_QUALIFICATION, &va);
1957 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs.error_code);
1959 TRACE_VMEXIT(3,regs.error_code);
1960 TRACE_VMEXIT(4,va);
1962 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1963 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
1964 (unsigned long)regs.eax, (unsigned long)regs.ebx,
1965 (unsigned long)regs.ecx, (unsigned long)regs.edx,
1966 (unsigned long)regs.esi, (unsigned long)regs.edi);
1967 v->arch.hvm_vcpu.mmio_op.inst_decoder_regs = &regs;
1969 if (!(error = vmx_do_page_fault(va, &regs))) {
1970 /*
1971 * Inject #PG using Interruption-Information Fields
1972 */
1973 vmx_inject_exception(v, TRAP_page_fault, regs.error_code);
1974 v->arch.hvm_vmx.cpu_cr2 = va;
1975 TRACE_3D(TRC_VMX_INT, v->domain->domain_id, TRAP_page_fault, va);
1977 break;
1979 case TRAP_nmi:
1980 do_nmi(&regs);
1981 break;
1982 default:
1983 vmx_reflect_exception(v);
1984 break;
1986 break;
1988 case EXIT_REASON_EXTERNAL_INTERRUPT:
1989 vmx_vmexit_do_extint(&regs);
1990 break;
1991 case EXIT_REASON_PENDING_INTERRUPT:
1992 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
1993 MONITOR_CPU_BASED_EXEC_CONTROLS);
1994 break;
1995 case EXIT_REASON_TASK_SWITCH:
1996 __hvm_bug(&regs);
1997 break;
1998 case EXIT_REASON_CPUID:
1999 __get_instruction_length(inst_len);
2000 vmx_vmexit_do_cpuid(regs.eax, &regs);
2001 __update_guest_eip(inst_len);
2002 break;
2003 case EXIT_REASON_HLT:
2004 __get_instruction_length(inst_len);
2005 __update_guest_eip(inst_len);
2006 vmx_vmexit_do_hlt();
2007 break;
2008 case EXIT_REASON_INVLPG:
2010 unsigned long va;
2012 __vmread(EXIT_QUALIFICATION, &va);
2013 vmx_vmexit_do_invlpg(va);
2014 __get_instruction_length(inst_len);
2015 __update_guest_eip(inst_len);
2016 break;
2018 case EXIT_REASON_VMCALL:
2019 __get_instruction_length(inst_len);
2020 __vmread(GUEST_RIP, &eip);
2021 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2023 hvm_print_line(v, regs.eax); /* provides the current domain */
2024 __update_guest_eip(inst_len);
2025 break;
2026 case EXIT_REASON_CR_ACCESS:
2028 __vmread(GUEST_RIP, &eip);
2029 __get_instruction_length(inst_len);
2030 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2032 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx, inst_len =%lx, exit_qualification = %lx",
2033 eip, inst_len, exit_qualification);
2034 if (vmx_cr_access(exit_qualification, &regs))
2035 __update_guest_eip(inst_len);
2036 TRACE_VMEXIT(3,regs.error_code);
2037 TRACE_VMEXIT(4,exit_qualification);
2038 break;
2040 case EXIT_REASON_DR_ACCESS:
2041 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2042 vmx_dr_access(exit_qualification, &regs);
2043 __get_instruction_length(inst_len);
2044 __update_guest_eip(inst_len);
2045 break;
2046 case EXIT_REASON_IO_INSTRUCTION:
2047 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2048 __get_instruction_length(inst_len);
2049 vmx_io_instruction(&regs, exit_qualification, inst_len);
2050 TRACE_VMEXIT(4,exit_qualification);
2051 break;
2052 case EXIT_REASON_MSR_READ:
2053 __get_instruction_length(inst_len);
2054 vmx_do_msr_read(&regs);
2055 __update_guest_eip(inst_len);
2056 break;
2057 case EXIT_REASON_MSR_WRITE:
2058 __vmread(GUEST_RIP, &eip);
2059 vmx_do_msr_write(&regs);
2060 __get_instruction_length(inst_len);
2061 __update_guest_eip(inst_len);
2062 break;
2063 case EXIT_REASON_MWAIT_INSTRUCTION:
2064 __hvm_bug(&regs);
2065 break;
2066 default:
2067 __hvm_bug(&regs); /* should not happen */
2071 asmlinkage void vmx_load_cr2(void)
2073 struct vcpu *v = current;
2075 local_irq_disable();
2076 #ifdef __i386__
2077 asm volatile("movl %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2078 #else
2079 asm volatile("movq %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2080 #endif
2083 asmlinkage void vmx_trace_vmentry (void)
2085 TRACE_5D(TRC_VMENTRY,
2086 trace_values[smp_processor_id()][0],
2087 trace_values[smp_processor_id()][1],
2088 trace_values[smp_processor_id()][2],
2089 trace_values[smp_processor_id()][3],
2090 trace_values[smp_processor_id()][4]);
2091 TRACE_VMEXIT(0,9);
2092 TRACE_VMEXIT(1,9);
2093 TRACE_VMEXIT(2,9);
2094 TRACE_VMEXIT(3,9);
2095 TRACE_VMEXIT(4,9);
2096 return;
2099 asmlinkage void vmx_trace_vmexit (void)
2101 TRACE_3D(TRC_VMEXIT,0,0,0);
2102 return;
2105 /*
2106 * Local variables:
2107 * mode: C
2108 * c-set-style: "BSD"
2109 * c-basic-offset: 4
2110 * tab-width: 4
2111 * indent-tabs-mode: nil
2112 * End:
2113 */