ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/processor.h @ 9401:138c76d5e493

[IA64] dump_stack() for debug.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@xenbuild.aw
date Fri Mar 24 10:38:41 2006 -0700 (2006-03-24)
parents dcbe36ee2171
children 741fd616f5dc
line source
1 #ifndef _ASM_IA64_PROCESSOR_H
2 #define _ASM_IA64_PROCESSOR_H
4 /*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
16 #include <linux/config.h>
18 #include <asm/intrinsics.h>
19 #include <asm/kregs.h>
20 #include <asm/ptrace.h>
21 #include <asm/ustack.h>
23 /* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
24 #define ARCH_HAS_SCHED_DOMAIN
26 #define IA64_NUM_DBG_REGS 8
27 /*
28 * Limits for PMC and PMD are set to less than maximum architected values
29 * but should be sufficient for a while
30 */
31 #define IA64_NUM_PMC_REGS 32
32 #define IA64_NUM_PMD_REGS 32
34 #define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
35 #define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
37 /*
38 * TASK_SIZE really is a mis-named. It really is the maximum user
39 * space address (plus one). On IA-64, there are five regions of 2TB
40 * each (assuming 8KB page size), for a total of 8TB of user virtual
41 * address space.
42 */
43 #define TASK_SIZE (current->thread.task_size)
45 /*
46 * This decides where the kernel will search for a free chunk of vm
47 * space during mmap's.
48 */
49 #define TASK_UNMAPPED_BASE (current->thread.map_base)
51 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
52 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
53 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
54 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
55 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
56 /* bit 5 is currently unused */
57 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
58 #define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
60 #define IA64_THREAD_UAC_SHIFT 3
61 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
62 #define IA64_THREAD_FPEMU_SHIFT 6
63 #define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
66 /*
67 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
68 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
69 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
70 */
71 #define IA64_NSEC_PER_CYC_SHIFT 30
73 #ifndef __ASSEMBLY__
75 #include <linux/cache.h>
76 #include <linux/compiler.h>
77 #include <linux/threads.h>
78 #include <linux/types.h>
80 #include <asm/fpu.h>
81 #include <asm/page.h>
82 #include <asm/percpu.h>
83 #include <asm/rse.h>
84 #include <asm/unwind.h>
85 #include <asm/atomic.h>
86 #ifdef CONFIG_NUMA
87 #include <asm/nodedata.h>
88 #endif
90 #ifdef XEN
91 #include <asm/xenprocessor.h>
92 #else
93 /* like above but expressed as bitfields for more efficient access: */
94 struct ia64_psr {
95 __u64 reserved0 : 1;
96 __u64 be : 1;
97 __u64 up : 1;
98 __u64 ac : 1;
99 __u64 mfl : 1;
100 __u64 mfh : 1;
101 __u64 reserved1 : 7;
102 __u64 ic : 1;
103 __u64 i : 1;
104 __u64 pk : 1;
105 __u64 reserved2 : 1;
106 __u64 dt : 1;
107 __u64 dfl : 1;
108 __u64 dfh : 1;
109 __u64 sp : 1;
110 __u64 pp : 1;
111 __u64 di : 1;
112 __u64 si : 1;
113 __u64 db : 1;
114 __u64 lp : 1;
115 __u64 tb : 1;
116 __u64 rt : 1;
117 __u64 reserved3 : 4;
118 __u64 cpl : 2;
119 __u64 is : 1;
120 __u64 mc : 1;
121 __u64 it : 1;
122 __u64 id : 1;
123 __u64 da : 1;
124 __u64 dd : 1;
125 __u64 ss : 1;
126 __u64 ri : 2;
127 __u64 ed : 1;
128 __u64 bn : 1;
129 __u64 reserved4 : 19;
130 };
131 #endif
133 /*
134 * CPU type, hardware bug flags, and per-CPU state. Frequently used
135 * state comes earlier:
136 */
137 struct cpuinfo_ia64 {
138 __u32 softirq_pending;
139 __u64 itm_delta; /* # of clock cycles between clock ticks */
140 __u64 itm_next; /* interval timer mask value to use for next clock tick */
141 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
142 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
143 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
144 __u64 itc_freq; /* frequency of ITC counter */
145 __u64 proc_freq; /* frequency of processor */
146 __u64 cyc_per_usec; /* itc_freq/1000000 */
147 __u64 ptce_base;
148 __u32 ptce_count[2];
149 __u32 ptce_stride[2];
150 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
152 #ifdef CONFIG_SMP
153 __u64 loops_per_jiffy;
154 int cpu;
155 __u32 socket_id; /* physical processor socket id */
156 __u16 core_id; /* core id */
157 __u16 thread_id; /* thread id */
158 __u16 num_log; /* Total number of logical processors on
159 * this socket that were successfully booted */
160 __u8 cores_per_socket; /* Cores per processor socket */
161 __u8 threads_per_core; /* Threads per core */
162 #endif
164 /* CPUID-derived information: */
165 __u64 ppn;
166 __u64 features;
167 __u8 number;
168 __u8 revision;
169 __u8 model;
170 __u8 family;
171 __u8 archrev;
172 char vendor[16];
174 #ifdef CONFIG_NUMA
175 struct ia64_node_data *node_data;
176 #endif
177 };
179 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
181 /*
182 * The "local" data variable. It refers to the per-CPU data of the currently executing
183 * CPU, much like "current" points to the per-task data of the currently executing task.
184 * Do not use the address of local_cpu_data, since it will be different from
185 * cpu_data(smp_processor_id())!
186 */
187 #define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
188 #define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
190 extern void identify_cpu (struct cpuinfo_ia64 *);
191 extern void print_cpu_info (struct cpuinfo_ia64 *);
193 typedef struct {
194 unsigned long seg;
195 } mm_segment_t;
197 #define SET_UNALIGN_CTL(task,value) \
198 ({ \
199 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
200 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
201 0; \
202 })
203 #define GET_UNALIGN_CTL(task,addr) \
204 ({ \
205 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
206 (int __user *) (addr)); \
207 })
209 #define SET_FPEMU_CTL(task,value) \
210 ({ \
211 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
212 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
213 0; \
214 })
215 #define GET_FPEMU_CTL(task,addr) \
216 ({ \
217 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
218 (int __user *) (addr)); \
219 })
221 #ifdef CONFIG_IA32_SUPPORT
222 struct desc_struct {
223 unsigned int a, b;
224 };
226 #define desc_empty(desc) (!((desc)->a + (desc)->b))
227 #define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
229 #define GDT_ENTRY_TLS_ENTRIES 3
230 #define GDT_ENTRY_TLS_MIN 6
231 #define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
233 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
235 struct partial_page_list;
236 #endif
238 struct thread_struct {
239 __u32 flags; /* various thread flags (see IA64_THREAD_*) */
240 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
241 __u8 on_ustack; /* executing on user-stacks? */
242 __u8 pad[3];
243 __u64 ksp; /* kernel stack pointer */
244 __u64 map_base; /* base address for get_unmapped_area() */
245 __u64 task_size; /* limit for task size */
246 __u64 rbs_bot; /* the base address for the RBS */
247 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
249 #ifdef CONFIG_IA32_SUPPORT
250 __u64 eflag; /* IA32 EFLAGS reg */
251 __u64 fsr; /* IA32 floating pt status reg */
252 __u64 fcr; /* IA32 floating pt control reg */
253 __u64 fir; /* IA32 fp except. instr. reg */
254 __u64 fdr; /* IA32 fp except. data reg */
255 __u64 old_k1; /* old value of ar.k1 */
256 __u64 old_iob; /* old IOBase value */
257 struct partial_page_list *ppl; /* partial page list for 4K page size issue */
258 /* cached TLS descriptors. */
259 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
261 # define INIT_THREAD_IA32 .eflag = 0, \
262 .fsr = 0, \
263 .fcr = 0x17800000037fULL, \
264 .fir = 0, \
265 .fdr = 0, \
266 .old_k1 = 0, \
267 .old_iob = 0, \
268 .ppl = NULL,
269 #else
270 # define INIT_THREAD_IA32
271 #endif /* CONFIG_IA32_SUPPORT */
272 #ifdef CONFIG_PERFMON
273 __u64 pmcs[IA64_NUM_PMC_REGS];
274 __u64 pmds[IA64_NUM_PMD_REGS];
275 void *pfm_context; /* pointer to detailed PMU context */
276 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
277 # define INIT_THREAD_PM .pmcs = {0UL, }, \
278 .pmds = {0UL, }, \
279 .pfm_context = NULL, \
280 .pfm_needs_checking = 0UL,
281 #else
282 # define INIT_THREAD_PM
283 #endif
284 __u64 dbr[IA64_NUM_DBG_REGS];
285 __u64 ibr[IA64_NUM_DBG_REGS];
286 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
287 };
289 #define INIT_THREAD { \
290 .flags = 0, \
291 .on_ustack = 0, \
292 .ksp = 0, \
293 .map_base = DEFAULT_MAP_BASE, \
294 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
295 .task_size = DEFAULT_TASK_SIZE, \
296 .last_fph_cpu = -1, \
297 INIT_THREAD_IA32 \
298 INIT_THREAD_PM \
299 .dbr = {0, }, \
300 .ibr = {0, }, \
301 .fph = {{{{0}}}, } \
302 }
304 #define start_thread(regs,new_ip,new_sp) do { \
305 set_fs(USER_DS); \
306 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
307 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
308 regs->cr_iip = new_ip; \
309 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
310 regs->ar_rnat = 0; \
311 regs->ar_bspstore = current->thread.rbs_bot; \
312 regs->ar_fpsr = FPSR_DEFAULT; \
313 regs->loadrs = 0; \
314 regs->r8 = current->mm->dumpable; /* set "don't zap registers" flag */ \
315 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
316 if (unlikely(!current->mm->dumpable)) { \
317 /* \
318 * Zap scratch regs to avoid leaking bits between processes with different \
319 * uid/privileges. \
320 */ \
321 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
322 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
323 } \
324 } while (0)
326 /* Forward declarations, a strange C thing... */
327 struct mm_struct;
328 struct task_struct;
330 /*
331 * Free all resources held by a thread. This is called after the
332 * parent of DEAD_TASK has collected the exit status of the task via
333 * wait().
334 */
335 #define release_thread(dead_task)
337 /* Prepare to copy thread state - unlazy all lazy status */
338 #define prepare_to_copy(tsk) do { } while (0)
340 /*
341 * This is the mechanism for creating a new kernel thread.
342 *
343 * NOTE 1: Only a kernel-only process (ie the swapper or direct
344 * descendants who haven't done an "execve()") should use this: it
345 * will work within a system call from a "real" process, but the
346 * process memory space will not be free'd until both the parent and
347 * the child have exited.
348 *
349 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
350 * into trouble in init/main.c when the child thread returns to
351 * do_basic_setup() and the timing is such that free_initmem() has
352 * been called already.
353 */
354 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
356 /* Get wait channel for task P. */
357 extern unsigned long get_wchan (struct task_struct *p);
359 /* Return instruction pointer of blocked task TSK. */
360 #define KSTK_EIP(tsk) \
361 ({ \
362 struct pt_regs *_regs = ia64_task_regs(tsk); \
363 _regs->cr_iip + ia64_psr(_regs)->ri; \
364 })
366 /* Return stack pointer of blocked task TSK. */
367 #define KSTK_ESP(tsk) ((tsk)->thread.ksp)
369 extern void ia64_getreg_unknown_kr (void);
370 extern void ia64_setreg_unknown_kr (void);
372 #define ia64_get_kr(regnum) \
373 ({ \
374 unsigned long r = 0; \
375 \
376 switch (regnum) { \
377 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
378 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
379 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
380 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
381 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
382 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
383 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
384 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
385 default: ia64_getreg_unknown_kr(); break; \
386 } \
387 r; \
388 })
390 #define ia64_set_kr(regnum, r) \
391 ({ \
392 switch (regnum) { \
393 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
394 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
395 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
396 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
397 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
398 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
399 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
400 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
401 default: ia64_setreg_unknown_kr(); break; \
402 } \
403 })
405 /*
406 * The following three macros can't be inline functions because we don't have struct
407 * task_struct at this point.
408 */
410 /*
411 * Return TRUE if task T owns the fph partition of the CPU we're running on.
412 * Must be called from code that has preemption disabled.
413 */
414 #ifndef XEN
415 #define ia64_is_local_fpu_owner(t) \
416 ({ \
417 struct task_struct *__ia64_islfo_task = (t); \
418 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
419 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
420 })
421 #endif
423 /*
424 * Mark task T as owning the fph partition of the CPU we're running on.
425 * Must be called from code that has preemption disabled.
426 */
427 #define ia64_set_local_fpu_owner(t) do { \
428 struct task_struct *__ia64_slfo_task = (t); \
429 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
430 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
431 } while (0)
433 /* Mark the fph partition of task T as being invalid on all CPUs. */
434 #define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
436 extern void __ia64_init_fpu (void);
437 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
438 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
439 extern void ia64_save_debug_regs (unsigned long *save_area);
440 extern void ia64_load_debug_regs (unsigned long *save_area);
441 #ifdef XEN
442 extern void dump_stack(void);
443 #endif
445 #ifdef CONFIG_IA32_SUPPORT
446 extern void ia32_save_state (struct task_struct *task);
447 extern void ia32_load_state (struct task_struct *task);
448 #endif
450 #define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
451 #define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
453 /* load fp 0.0 into fph */
454 static inline void
455 ia64_init_fpu (void) {
456 ia64_fph_enable();
457 __ia64_init_fpu();
458 ia64_fph_disable();
459 }
461 /* save f32-f127 at FPH */
462 static inline void
463 ia64_save_fpu (struct ia64_fpreg *fph) {
464 ia64_fph_enable();
465 __ia64_save_fpu(fph);
466 ia64_fph_disable();
467 }
469 /* load f32-f127 from FPH */
470 static inline void
471 ia64_load_fpu (struct ia64_fpreg *fph) {
472 ia64_fph_enable();
473 __ia64_load_fpu(fph);
474 ia64_fph_disable();
475 }
477 static inline __u64
478 ia64_clear_ic (void)
479 {
480 __u64 psr;
481 psr = ia64_getreg(_IA64_REG_PSR);
482 ia64_stop();
483 ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
484 ia64_srlz_i();
485 return psr;
486 }
488 /*
489 * Restore the psr.
490 */
491 static inline void
492 ia64_set_psr (__u64 psr)
493 {
494 ia64_stop();
495 ia64_setreg(_IA64_REG_PSR_L, psr);
496 ia64_srlz_d();
497 }
499 /*
500 * Insert a translation into an instruction and/or data translation
501 * register.
502 */
503 static inline void
504 ia64_itr (__u64 target_mask, __u64 tr_num,
505 __u64 vmaddr, __u64 pte,
506 __u64 log_page_size)
507 {
508 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
509 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
510 ia64_stop();
511 if (target_mask & 0x1)
512 ia64_itri(tr_num, pte);
513 if (target_mask & 0x2)
514 ia64_itrd(tr_num, pte);
515 }
517 /*
518 * Insert a translation into the instruction and/or data translation
519 * cache.
520 */
521 static inline void
522 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
523 __u64 log_page_size)
524 {
525 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
526 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
527 ia64_stop();
528 /* as per EAS2.6, itc must be the last instruction in an instruction group */
529 if (target_mask & 0x1)
530 ia64_itci(pte);
531 if (target_mask & 0x2)
532 ia64_itcd(pte);
533 }
535 /*
536 * Purge a range of addresses from instruction and/or data translation
537 * register(s).
538 */
539 static inline void
540 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
541 {
542 if (target_mask & 0x1)
543 ia64_ptri(vmaddr, (log_size << 2));
544 if (target_mask & 0x2)
545 ia64_ptrd(vmaddr, (log_size << 2));
546 }
548 /* Set the interrupt vector address. The address must be suitably aligned (32KB). */
549 static inline void
550 ia64_set_iva (void *ivt_addr)
551 {
552 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
553 ia64_srlz_i();
554 }
556 /* Set the page table address and control bits. */
557 static inline void
558 ia64_set_pta (__u64 pta)
559 {
560 /* Note: srlz.i implies srlz.d */
561 ia64_setreg(_IA64_REG_CR_PTA, pta);
562 ia64_srlz_i();
563 }
565 static inline void
566 ia64_eoi (void)
567 {
568 ia64_setreg(_IA64_REG_CR_EOI, 0);
569 ia64_srlz_d();
570 }
572 #define cpu_relax() ia64_hint(ia64_hint_pause)
574 static inline void
575 ia64_set_lrr0 (unsigned long val)
576 {
577 ia64_setreg(_IA64_REG_CR_LRR0, val);
578 ia64_srlz_d();
579 }
581 static inline void
582 ia64_set_lrr1 (unsigned long val)
583 {
584 ia64_setreg(_IA64_REG_CR_LRR1, val);
585 ia64_srlz_d();
586 }
589 /*
590 * Given the address to which a spill occurred, return the unat bit
591 * number that corresponds to this address.
592 */
593 static inline __u64
594 ia64_unat_pos (void *spill_addr)
595 {
596 return ((__u64) spill_addr >> 3) & 0x3f;
597 }
599 /*
600 * Set the NaT bit of an integer register which was spilled at address
601 * SPILL_ADDR. UNAT is the mask to be updated.
602 */
603 static inline void
604 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
605 {
606 __u64 bit = ia64_unat_pos(spill_addr);
607 __u64 mask = 1UL << bit;
609 *unat = (*unat & ~mask) | (nat << bit);
610 }
612 /*
613 * Return saved PC of a blocked thread.
614 * Note that the only way T can block is through a call to schedule() -> switch_to().
615 */
616 static inline unsigned long
617 thread_saved_pc (struct task_struct *t)
618 {
619 struct unw_frame_info info;
620 unsigned long ip;
622 unw_init_from_blocked_task(&info, t);
623 if (unw_unwind(&info) < 0)
624 return 0;
625 unw_get_ip(&info, &ip);
626 return ip;
627 }
629 /*
630 * Get the current instruction/program counter value.
631 */
632 #define current_text_addr() \
633 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
635 static inline __u64
636 ia64_get_ivr (void)
637 {
638 __u64 r;
639 ia64_srlz_d();
640 r = ia64_getreg(_IA64_REG_CR_IVR);
641 ia64_srlz_d();
642 return r;
643 }
645 #ifdef XEN
646 /* Get the page table address and control bits. */
647 static inline __u64
648 ia64_get_pta (void)
649 {
650 __u64 r;
651 ia64_srlz_d();
652 r = ia64_getreg(_IA64_REG_CR_PTA);
653 ia64_srlz_d();
654 return r;
655 }
656 #endif
658 static inline void
659 ia64_set_dbr (__u64 regnum, __u64 value)
660 {
661 __ia64_set_dbr(regnum, value);
662 #ifdef CONFIG_ITANIUM
663 ia64_srlz_d();
664 #endif
665 }
667 static inline __u64
668 ia64_get_dbr (__u64 regnum)
669 {
670 __u64 retval;
672 retval = __ia64_get_dbr(regnum);
673 #ifdef CONFIG_ITANIUM
674 ia64_srlz_d();
675 #endif
676 return retval;
677 }
679 static inline __u64
680 ia64_rotr (__u64 w, __u64 n)
681 {
682 return (w >> n) | (w << (64 - n));
683 }
685 #define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
687 /*
688 * Take a mapped kernel address and return the equivalent address
689 * in the region 7 identity mapped virtual area.
690 */
691 static inline void *
692 ia64_imva (void *addr)
693 {
694 void *result;
695 result = (void *) ia64_tpa(addr);
696 return __va(result);
697 }
699 #define ARCH_HAS_PREFETCH
700 #define ARCH_HAS_PREFETCHW
701 #define ARCH_HAS_SPINLOCK_PREFETCH
702 #define PREFETCH_STRIDE L1_CACHE_BYTES
704 static inline void
705 prefetch (const void *x)
706 {
707 ia64_lfetch(ia64_lfhint_none, x);
708 }
710 static inline void
711 prefetchw (const void *x)
712 {
713 ia64_lfetch_excl(ia64_lfhint_none, x);
714 }
716 #define spin_lock_prefetch(x) prefetchw(x)
718 extern unsigned long boot_option_idle_override;
720 #endif /* !__ASSEMBLY__ */
722 #endif /* _ASM_IA64_PROCESSOR_H */