ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/system.h @ 7922:0ee00faf332d

Adapt to removal of #ifdef ia64 in xmalloc (handle SMP_CACHE_SHIFT)
author djm@kirby.fc.hp.com
date Wed Nov 23 15:23:28 2005 -0600 (2005-11-23)
parents d0a2b36f72f2
children c668c6abb5f0
line source
1 #ifndef _ASM_IA64_SYSTEM_H
2 #define _ASM_IA64_SYSTEM_H
4 /*
5 * System defines. Note that this is included both from .c and .S
6 * files, so it does only defines, not any C code. This is based
7 * on information published in the Processor Abstraction Layer
8 * and the System Abstraction Layer manual.
9 *
10 * Copyright (C) 1998-2003 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
13 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
14 */
15 #include <linux/config.h>
17 #include <asm/kregs.h>
18 #include <asm/page.h>
19 #include <asm/pal.h>
20 #include <asm/percpu.h>
22 #define GATE_ADDR __IA64_UL_CONST(0xa000000000000000)
23 /*
24 * 0xa000000000000000+2*PERCPU_PAGE_SIZE
25 * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
26 */
27 #define KERNEL_START __IA64_UL_CONST(0xa000000100000000)
28 #define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
30 #ifndef __ASSEMBLY__
32 #include <linux/kernel.h>
33 #include <linux/types.h>
35 struct pci_vector_struct {
36 __u16 segment; /* PCI Segment number */
37 __u16 bus; /* PCI Bus number */
38 __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
39 __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
40 __u32 irq; /* IRQ assigned */
41 };
43 extern struct ia64_boot_param {
44 __u64 command_line; /* physical address of command line arguments */
45 __u64 efi_systab; /* physical address of EFI system table */
46 __u64 efi_memmap; /* physical address of EFI memory map */
47 __u64 efi_memmap_size; /* size of EFI memory map */
48 __u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
49 __u32 efi_memdesc_version; /* memory descriptor version */
50 struct {
51 __u16 num_cols; /* number of columns on console output device */
52 __u16 num_rows; /* number of rows on console output device */
53 __u16 orig_x; /* cursor's x position */
54 __u16 orig_y; /* cursor's y position */
55 } console_info;
56 __u64 fpswa; /* physical address of the fpswa interface */
57 __u64 initrd_start;
58 __u64 initrd_size;
59 //for loading initrd for dom0
60 __u64 domain_start; /* virtual address where the boot time domain begins */
61 __u64 domain_size; /* how big is the boot domain */
63 } *ia64_boot_param;
65 /*
66 * Macros to force memory ordering. In these descriptions, "previous"
67 * and "subsequent" refer to program order; "visible" means that all
68 * architecturally visible effects of a memory access have occurred
69 * (at a minimum, this means the memory has been read or written).
70 *
71 * wmb(): Guarantees that all preceding stores to memory-
72 * like regions are visible before any subsequent
73 * stores and that all following stores will be
74 * visible only after all previous stores.
75 * rmb(): Like wmb(), but for reads.
76 * mb(): wmb()/rmb() combo, i.e., all previous memory
77 * accesses are visible before all subsequent
78 * accesses and vice versa. This is also known as
79 * a "fence."
80 *
81 * Note: "mb()" and its variants cannot be used as a fence to order
82 * accesses to memory mapped I/O registers. For that, mf.a needs to
83 * be used. However, we don't want to always use mf.a because (a)
84 * it's (presumably) much slower than mf and (b) mf.a is supported for
85 * sequential memory pages only.
86 */
87 #define mb() ia64_mf()
88 #define rmb() mb()
89 #define wmb() mb()
90 #define read_barrier_depends() do { } while(0)
92 #ifdef CONFIG_SMP
93 # define smp_mb() mb()
94 # define smp_rmb() rmb()
95 # define smp_wmb() wmb()
96 # define smp_read_barrier_depends() read_barrier_depends()
97 #else
98 # define smp_mb() barrier()
99 # define smp_rmb() barrier()
100 # define smp_wmb() barrier()
101 # define smp_read_barrier_depends() do { } while(0)
102 #endif
104 /*
105 * XXX check on these---I suspect what Linus really wants here is
106 * acquire vs release semantics but we can't discuss this stuff with
107 * Linus just yet. Grrr...
108 */
109 #define set_mb(var, value) do { (var) = (value); mb(); } while (0)
110 #define set_wmb(var, value) do { (var) = (value); mb(); } while (0)
112 #define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
114 /*
115 * The group barrier in front of the rsm & ssm are necessary to ensure
116 * that none of the previous instructions in the same group are
117 * affected by the rsm/ssm.
118 */
119 /* For spinlocks etc */
121 /*
122 * - clearing psr.i is implicitly serialized (visible by next insn)
123 * - setting psr.i requires data serialization
124 * - we need a stop-bit before reading PSR because we sometimes
125 * write a floating-point register right before reading the PSR
126 * and that writes to PSR.mfl
127 */
128 #define __local_irq_save(x) \
129 do { \
130 ia64_stop(); \
131 (x) = ia64_getreg(_IA64_REG_PSR); \
132 ia64_stop(); \
133 ia64_rsm(IA64_PSR_I); \
134 } while (0)
136 #define __local_irq_disable() \
137 do { \
138 ia64_stop(); \
139 ia64_rsm(IA64_PSR_I); \
140 } while (0)
142 #define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
144 #ifdef CONFIG_IA64_DEBUG_IRQ
146 extern unsigned long last_cli_ip;
148 # define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
150 # define local_irq_save(x) \
151 do { \
152 unsigned long psr; \
153 \
154 __local_irq_save(psr); \
155 if (psr & IA64_PSR_I) \
156 __save_ip(); \
157 (x) = psr; \
158 } while (0)
160 # define local_irq_disable() do { unsigned long x; local_irq_save(x); } while (0)
162 # define local_irq_restore(x) \
163 do { \
164 unsigned long old_psr, psr = (x); \
165 \
166 local_save_flags(old_psr); \
167 __local_irq_restore(psr); \
168 if ((old_psr & IA64_PSR_I) && !(psr & IA64_PSR_I)) \
169 __save_ip(); \
170 } while (0)
172 #else /* !CONFIG_IA64_DEBUG_IRQ */
173 # define local_irq_save(x) __local_irq_save(x)
174 # define local_irq_disable() __local_irq_disable()
175 # define local_irq_restore(x) __local_irq_restore(x)
176 #endif /* !CONFIG_IA64_DEBUG_IRQ */
178 #define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
179 #define local_save_flags(flags) ({ ia64_stop(); (flags) = ia64_getreg(_IA64_REG_PSR); })
181 #define irqs_disabled() \
182 ({ \
183 unsigned long __ia64_id_flags; \
184 local_save_flags(__ia64_id_flags); \
185 (__ia64_id_flags & IA64_PSR_I) == 0; \
186 })
188 #ifdef __KERNEL__
190 #ifdef CONFIG_IA32_SUPPORT
191 # define IS_IA32_PROCESS(regs) (ia64_psr(regs)->is != 0)
192 #else
193 # define IS_IA32_PROCESS(regs) 0
194 struct task_struct;
195 static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
196 static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
197 #endif
199 /*
200 * Context switch from one thread to another. If the two threads have
201 * different address spaces, schedule() has already taken care of
202 * switching to the new address space by calling switch_mm().
203 *
204 * Disabling access to the fph partition and the debug-register
205 * context switch MUST be done before calling ia64_switch_to() since a
206 * newly created thread returns directly to
207 * ia64_ret_from_syscall_clear_r8.
208 */
209 extern struct task_struct *ia64_switch_to (void *next_task);
211 struct task_struct;
213 extern void ia64_save_extra (struct task_struct *task);
214 extern void ia64_load_extra (struct task_struct *task);
216 #ifdef CONFIG_PERFMON
217 DECLARE_PER_CPU(unsigned long, pfm_syst_info);
218 # define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
219 #else
220 # define PERFMON_IS_SYSWIDE() (0)
221 #endif
223 #define IA64_HAS_EXTRA_STATE(t) \
224 ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
225 || IS_IA32_PROCESS(ia64_task_regs(t)) || PERFMON_IS_SYSWIDE())
227 #define __switch_to(prev,next,last) do { \
228 if (IA64_HAS_EXTRA_STATE(prev)) \
229 ia64_save_extra(prev); \
230 if (IA64_HAS_EXTRA_STATE(next)) \
231 ia64_load_extra(next); \
232 ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
233 (last) = ia64_switch_to((next)); \
234 } while (0)
236 #ifdef CONFIG_SMP
237 /*
238 * In the SMP case, we save the fph state when context-switching away from a thread that
239 * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
240 * pick up the state from task->thread.fph, avoiding the complication of having to fetch
241 * the latest fph state from another CPU. In other words: eager save, lazy restore.
242 */
243 # define switch_to(prev,next,last) do { \
244 if (ia64_psr(ia64_task_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
245 ia64_psr(ia64_task_regs(prev))->mfh = 0; \
246 (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
247 __ia64_save_fpu((prev)->thread.fph); \
248 } \
249 __switch_to(prev, next, last); \
250 } while (0)
251 #else
252 # define switch_to(prev,next,last) __switch_to(prev, next, last)
253 #endif
255 /*
256 * On IA-64, we don't want to hold the runqueue's lock during the low-level context-switch,
257 * because that could cause a deadlock. Here is an example by Erich Focht:
258 *
259 * Example:
260 * CPU#0:
261 * schedule()
262 * -> spin_lock_irq(&rq->lock)
263 * -> context_switch()
264 * -> wrap_mmu_context()
265 * -> read_lock(&tasklist_lock)
266 *
267 * CPU#1:
268 * sys_wait4() or release_task() or forget_original_parent()
269 * -> write_lock(&tasklist_lock)
270 * -> do_notify_parent()
271 * -> wake_up_parent()
272 * -> try_to_wake_up()
273 * -> spin_lock_irq(&parent_rq->lock)
274 *
275 * If the parent's rq happens to be on CPU#0, we'll wait for the rq->lock
276 * of that CPU which will not be released, because there we wait for the
277 * tasklist_lock to become available.
278 */
279 #define __ARCH_WANT_UNLOCKED_CTXSW
281 #define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
283 void cpu_idle_wait(void);
285 #define arch_align_stack(x) (x)
287 #endif /* __KERNEL__ */
289 #endif /* __ASSEMBLY__ */
291 #ifdef XEN
292 #include <asm/xensystem.h>
293 #endif
295 #endif /* _ASM_IA64_SYSTEM_H */