ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/io.h @ 7922:0ee00faf332d

Adapt to removal of #ifdef ia64 in xmalloc (handle SMP_CACHE_SHIFT)
author djm@kirby.fc.hp.com
date Wed Nov 23 15:23:28 2005 -0600 (2005-11-23)
parents 06d84bf87159
children 0c94043f5c5b
line source
1 #ifndef _ASM_IA64_IO_H
2 #define _ASM_IA64_IO_H
4 /*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
22 /* We don't use IO slowdowns on the ia64, but.. */
23 #define __SLOW_DOWN_IO do { } while (0)
24 #define SLOW_DOWN_IO do { } while (0)
26 #ifdef XEN
27 #define __IA64_UNCACHED_OFFSET 0xe800000000000000UL
28 #else
29 #define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */
30 #endif
32 /*
33 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
34 * large machines may have multiple other I/O spaces so we can't place any a priori limit
35 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
36 */
37 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
39 #define MAX_IO_SPACES_BITS 4
40 #define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
41 #define IO_SPACE_BITS 24
42 #define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
44 #define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
45 #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
46 #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
48 #define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | (p & 0xfff))
50 struct io_space {
51 unsigned long mmio_base; /* base in MMIO space */
52 int sparse;
53 };
55 extern struct io_space io_space[];
56 extern unsigned int num_io_spaces;
58 # ifdef __KERNEL__
60 /*
61 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
62 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
63 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
64 *
65 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
66 * code that uses bare port numbers without the prerequisite pci_iomap().
67 */
68 #define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
69 #define PIO_MASK (PIO_OFFSET - 1)
70 #define PIO_RESERVED __IA64_UNCACHED_OFFSET
71 #define HAVE_ARCH_PIO_SIZE
73 #include <asm/intrinsics.h>
74 #include <asm/machvec.h>
75 #include <asm/page.h>
76 #include <asm/system.h>
77 #include <asm-generic/iomap.h>
79 /*
80 * Change virtual addresses to physical addresses and vv.
81 */
82 static inline unsigned long
83 virt_to_phys (volatile void *address)
84 {
85 return (unsigned long) address - PAGE_OFFSET;
86 }
88 static inline void*
89 phys_to_virt (unsigned long address)
90 {
91 return (void *) (address + PAGE_OFFSET);
92 }
94 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
95 extern int valid_phys_addr_range (unsigned long addr, size_t *count); /* efi.c */
97 /*
98 * The following two macros are deprecated and scheduled for removal.
99 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
100 */
101 #define bus_to_virt phys_to_virt
102 #define virt_to_bus virt_to_phys
103 #define page_to_bus page_to_phys
105 # endif /* KERNEL */
107 /*
108 * Memory fence w/accept. This should never be used in code that is
109 * not IA-64 specific.
110 */
111 #define __ia64_mf_a() ia64_mfa()
113 /**
114 * ___ia64_mmiowb - I/O write barrier
115 *
116 * Ensure ordering of I/O space writes. This will make sure that writes
117 * following the barrier will arrive after all previous writes. For most
118 * ia64 platforms, this is a simple 'mf.a' instruction.
119 *
120 * See Documentation/DocBook/deviceiobook.tmpl for more information.
121 */
122 static inline void ___ia64_mmiowb(void)
123 {
124 ia64_mfa();
125 }
127 static inline void*
128 __ia64_mk_io_addr (unsigned long port)
129 {
130 struct io_space *space;
131 unsigned long offset;
133 space = &io_space[IO_SPACE_NR(port)];
134 port = IO_SPACE_PORT(port);
135 if (space->sparse)
136 offset = IO_SPACE_SPARSE_ENCODING(port);
137 else
138 offset = port;
140 return (void *) (space->mmio_base | offset);
141 }
143 #define __ia64_inb ___ia64_inb
144 #define __ia64_inw ___ia64_inw
145 #define __ia64_inl ___ia64_inl
146 #define __ia64_outb ___ia64_outb
147 #define __ia64_outw ___ia64_outw
148 #define __ia64_outl ___ia64_outl
149 #define __ia64_readb ___ia64_readb
150 #define __ia64_readw ___ia64_readw
151 #define __ia64_readl ___ia64_readl
152 #define __ia64_readq ___ia64_readq
153 #define __ia64_readb_relaxed ___ia64_readb
154 #define __ia64_readw_relaxed ___ia64_readw
155 #define __ia64_readl_relaxed ___ia64_readl
156 #define __ia64_readq_relaxed ___ia64_readq
157 #define __ia64_writeb ___ia64_writeb
158 #define __ia64_writew ___ia64_writew
159 #define __ia64_writel ___ia64_writel
160 #define __ia64_writeq ___ia64_writeq
161 #define __ia64_mmiowb ___ia64_mmiowb
163 /*
164 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
165 * that the access has completed before executing other I/O accesses. Since we're doing
166 * the accesses through an uncachable (UC) translation, the CPU will execute them in
167 * program order. However, we still need to tell the compiler not to shuffle them around
168 * during optimization, which is why we use "volatile" pointers.
169 */
171 static inline unsigned int
172 ___ia64_inb (unsigned long port)
173 {
174 volatile unsigned char *addr = __ia64_mk_io_addr(port);
175 unsigned char ret;
177 ret = *addr;
178 __ia64_mf_a();
179 return ret;
180 }
182 static inline unsigned int
183 ___ia64_inw (unsigned long port)
184 {
185 volatile unsigned short *addr = __ia64_mk_io_addr(port);
186 unsigned short ret;
188 ret = *addr;
189 __ia64_mf_a();
190 return ret;
191 }
193 static inline unsigned int
194 ___ia64_inl (unsigned long port)
195 {
196 volatile unsigned int *addr = __ia64_mk_io_addr(port);
197 unsigned int ret;
199 ret = *addr;
200 __ia64_mf_a();
201 return ret;
202 }
204 static inline void
205 ___ia64_outb (unsigned char val, unsigned long port)
206 {
207 volatile unsigned char *addr = __ia64_mk_io_addr(port);
209 *addr = val;
210 __ia64_mf_a();
211 }
213 static inline void
214 ___ia64_outw (unsigned short val, unsigned long port)
215 {
216 volatile unsigned short *addr = __ia64_mk_io_addr(port);
218 *addr = val;
219 __ia64_mf_a();
220 }
222 static inline void
223 ___ia64_outl (unsigned int val, unsigned long port)
224 {
225 volatile unsigned int *addr = __ia64_mk_io_addr(port);
227 *addr = val;
228 __ia64_mf_a();
229 }
231 static inline void
232 __insb (unsigned long port, void *dst, unsigned long count)
233 {
234 unsigned char *dp = dst;
236 while (count--)
237 *dp++ = platform_inb(port);
238 }
240 static inline void
241 __insw (unsigned long port, void *dst, unsigned long count)
242 {
243 unsigned short *dp = dst;
245 while (count--)
246 *dp++ = platform_inw(port);
247 }
249 static inline void
250 __insl (unsigned long port, void *dst, unsigned long count)
251 {
252 unsigned int *dp = dst;
254 while (count--)
255 *dp++ = platform_inl(port);
256 }
258 static inline void
259 __outsb (unsigned long port, const void *src, unsigned long count)
260 {
261 const unsigned char *sp = src;
263 while (count--)
264 platform_outb(*sp++, port);
265 }
267 static inline void
268 __outsw (unsigned long port, const void *src, unsigned long count)
269 {
270 const unsigned short *sp = src;
272 while (count--)
273 platform_outw(*sp++, port);
274 }
276 static inline void
277 __outsl (unsigned long port, const void *src, unsigned long count)
278 {
279 const unsigned int *sp = src;
281 while (count--)
282 platform_outl(*sp++, port);
283 }
285 /*
286 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
287 * specification regarding legacy I/O support. Thus, we have to make these operations
288 * platform dependent...
289 */
290 #define __inb platform_inb
291 #define __inw platform_inw
292 #define __inl platform_inl
293 #define __outb platform_outb
294 #define __outw platform_outw
295 #define __outl platform_outl
296 #define __mmiowb platform_mmiowb
298 #define inb(p) __inb(p)
299 #define inw(p) __inw(p)
300 #define inl(p) __inl(p)
301 #define insb(p,d,c) __insb(p,d,c)
302 #define insw(p,d,c) __insw(p,d,c)
303 #define insl(p,d,c) __insl(p,d,c)
304 #define outb(v,p) __outb(v,p)
305 #define outw(v,p) __outw(v,p)
306 #define outl(v,p) __outl(v,p)
307 #define outsb(p,s,c) __outsb(p,s,c)
308 #define outsw(p,s,c) __outsw(p,s,c)
309 #define outsl(p,s,c) __outsl(p,s,c)
310 #define mmiowb() __mmiowb()
312 /*
313 * The address passed to these functions are ioremap()ped already.
314 *
315 * We need these to be machine vectors since some platforms don't provide
316 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
317 * a good idea). Writes are ok though for all existing ia64 platforms (and
318 * hopefully it'll stay that way).
319 */
320 static inline unsigned char
321 ___ia64_readb (const volatile void __iomem *addr)
322 {
323 return *(volatile unsigned char __force *)addr;
324 }
326 static inline unsigned short
327 ___ia64_readw (const volatile void __iomem *addr)
328 {
329 return *(volatile unsigned short __force *)addr;
330 }
332 static inline unsigned int
333 ___ia64_readl (const volatile void __iomem *addr)
334 {
335 return *(volatile unsigned int __force *) addr;
336 }
338 static inline unsigned long
339 ___ia64_readq (const volatile void __iomem *addr)
340 {
341 return *(volatile unsigned long __force *) addr;
342 }
344 static inline void
345 __writeb (unsigned char val, volatile void __iomem *addr)
346 {
347 *(volatile unsigned char __force *) addr = val;
348 }
350 static inline void
351 __writew (unsigned short val, volatile void __iomem *addr)
352 {
353 *(volatile unsigned short __force *) addr = val;
354 }
356 static inline void
357 __writel (unsigned int val, volatile void __iomem *addr)
358 {
359 *(volatile unsigned int __force *) addr = val;
360 }
362 static inline void
363 __writeq (unsigned long val, volatile void __iomem *addr)
364 {
365 *(volatile unsigned long __force *) addr = val;
366 }
368 #define __readb platform_readb
369 #define __readw platform_readw
370 #define __readl platform_readl
371 #define __readq platform_readq
372 #define __readb_relaxed platform_readb_relaxed
373 #define __readw_relaxed platform_readw_relaxed
374 #define __readl_relaxed platform_readl_relaxed
375 #define __readq_relaxed platform_readq_relaxed
377 #define readb(a) __readb((a))
378 #define readw(a) __readw((a))
379 #define readl(a) __readl((a))
380 #define readq(a) __readq((a))
381 #define readb_relaxed(a) __readb_relaxed((a))
382 #define readw_relaxed(a) __readw_relaxed((a))
383 #define readl_relaxed(a) __readl_relaxed((a))
384 #define readq_relaxed(a) __readq_relaxed((a))
385 #define __raw_readb readb
386 #define __raw_readw readw
387 #define __raw_readl readl
388 #define __raw_readq readq
389 #define __raw_readb_relaxed readb_relaxed
390 #define __raw_readw_relaxed readw_relaxed
391 #define __raw_readl_relaxed readl_relaxed
392 #define __raw_readq_relaxed readq_relaxed
393 #define writeb(v,a) __writeb((v), (a))
394 #define writew(v,a) __writew((v), (a))
395 #define writel(v,a) __writel((v), (a))
396 #define writeq(v,a) __writeq((v), (a))
397 #define __raw_writeb writeb
398 #define __raw_writew writew
399 #define __raw_writel writel
400 #define __raw_writeq writeq
402 #ifndef inb_p
403 # define inb_p inb
404 #endif
405 #ifndef inw_p
406 # define inw_p inw
407 #endif
408 #ifndef inl_p
409 # define inl_p inl
410 #endif
412 #ifndef outb_p
413 # define outb_p outb
414 #endif
415 #ifndef outw_p
416 # define outw_p outw
417 #endif
418 #ifndef outl_p
419 # define outl_p outl
420 #endif
422 /*
423 * An "address" in IO memory space is not clearly either an integer or a pointer. We will
424 * accept both, thus the casts.
425 *
426 * On ia-64, we access the physical I/O memory space through the uncached kernel region.
427 */
428 static inline void __iomem *
429 ioremap (unsigned long offset, unsigned long size)
430 {
431 return (void __iomem *) (__IA64_UNCACHED_OFFSET | (offset));
432 }
434 static inline void
435 iounmap (volatile void __iomem *addr)
436 {
437 }
439 #define ioremap_nocache(o,s) ioremap(o,s)
441 # ifdef __KERNEL__
443 /*
444 * String version of IO memory access ops:
445 */
446 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
447 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
448 extern void memset_io(volatile void __iomem *s, int c, long n);
450 #define dma_cache_inv(_start,_size) do { } while (0)
451 #define dma_cache_wback(_start,_size) do { } while (0)
452 #define dma_cache_wback_inv(_start,_size) do { } while (0)
454 # endif /* __KERNEL__ */
456 /*
457 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
458 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
459 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
460 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
461 * over BIO-level virtual merging.
462 */
463 extern unsigned long ia64_max_iommu_merge_mask;
464 #if 1
465 #define BIO_VMERGE_BOUNDARY 0
466 #else
467 /*
468 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
469 * replaced by dma_merge_mask() or something of that sort. Note: the only way
470 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
471 * expanded into:
472 *
473 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
474 *
475 * which is precisely what we want.
476 */
477 #define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
478 #endif
480 #endif /* _ASM_IA64_IO_H */