ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/xen/xenentry.S @ 13775:0df9dc2f1d03

[IA64] Fix compile warnings in xenentry.S

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
author awilliam@xenbuild2.aw
date Thu Feb 01 13:54:26 2007 -0700 (2007-02-01)
parents dd58c6062292
children e47738923a05
line source
1 /*
2 * ia64/xen/entry.S
3 *
4 * Alternate kernel routines for Xen. Heavily leveraged from
5 * ia64/kernel/entry.S
6 *
7 * Copyright (C) 2005 Hewlett-Packard Co
8 * Dan Magenheimer <dan.magenheimer@.hp.com>
9 */
11 #include <linux/config.h>
13 #include <asm/asmmacro.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/kregs.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/pgtable.h>
19 #include <asm/percpu.h>
20 #include <asm/processor.h>
21 #include <asm/thread_info.h>
22 #include <asm/unistd.h>
24 #ifdef CONFIG_XEN
25 #include "xenminstate.h"
26 #else
27 #include "minstate.h"
28 #endif
30 /*
31 * prev_task <- ia64_switch_to(struct task_struct *next)
32 * With Ingo's new scheduler, interrupts are disabled when this routine gets
33 * called. The code starting at .map relies on this. The rest of the code
34 * doesn't care about the interrupt masking status.
35 */
36 #ifdef CONFIG_XEN
37 GLOBAL_ENTRY(xen_switch_to)
38 .prologue
39 alloc r16=ar.pfs,1,0,0,0
40 movl r22=running_on_xen;;
41 ld4 r22=[r22];;
42 cmp.eq p7,p0=r22,r0
43 (p7) br.cond.sptk.many __ia64_switch_to;;
44 #else
45 GLOBAL_ENTRY(ia64_switch_to)
46 .prologue
47 alloc r16=ar.pfs,1,0,0,0
48 #endif
49 DO_SAVE_SWITCH_STACK
50 .body
52 adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
53 movl r25=init_task
54 mov r27=IA64_KR(CURRENT_STACK)
55 adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
56 dep r20=0,in0,61,3 // physical address of "next"
57 ;;
58 st8 [r22]=sp // save kernel stack pointer of old task
59 shr.u r26=r20,IA64_GRANULE_SHIFT
60 cmp.eq p7,p6=r25,in0
61 ;;
62 /*
63 * If we've already mapped this task's page, we can skip doing it again.
64 */
65 (p6) cmp.eq p7,p6=r26,r27
66 (p6) br.cond.dpnt .map
67 ;;
68 .done:
69 ld8 sp=[r21] // load kernel stack pointer of new task
70 #ifdef CONFIG_XEN
71 // update "current" application register
72 mov r8=IA64_KR_CURRENT
73 mov r9=in0;;
74 XEN_HYPER_SET_KR
75 #else
76 mov IA64_KR(CURRENT)=in0 // update "current" application register
77 #endif
78 mov r8=r13 // return pointer to previously running task
79 mov r13=in0 // set "current" pointer
80 ;;
81 DO_LOAD_SWITCH_STACK
83 #ifdef CONFIG_SMP
84 sync.i // ensure "fc"s done by this CPU are visible on other CPUs
85 #endif
86 br.ret.sptk.many rp // boogie on out in new context
88 .map:
89 #ifdef CONFIG_XEN
90 movl r25=XSI_PSR_IC // clear psr.ic
91 ;;
92 st4 [r25]=r0
93 ;;
94 #else
95 rsm psr.ic // interrupts (psr.i) are already disabled here
96 #endif
97 movl r25=PAGE_KERNEL
98 ;;
99 srlz.d
100 or r23=r25,r20 // construct PA | page properties
101 mov r25=IA64_GRANULE_SHIFT<<2
102 ;;
103 #ifdef CONFIG_XEN
104 movl r8=XSI_ITIR
105 ;;
106 st8 [r8]=r25
107 ;;
108 movl r8=XSI_IFA
109 ;;
110 st8 [r8]=in0 // VA of next task...
111 ;;
112 mov r25=IA64_TR_CURRENT_STACK
113 // remember last page we mapped...
114 mov r8=IA64_KR_CURRENT_STACK
115 mov r9=r26;;
116 XEN_HYPER_SET_KR;;
117 #else
118 mov cr.itir=r25
119 mov cr.ifa=in0 // VA of next task...
120 ;;
121 mov r25=IA64_TR_CURRENT_STACK
122 mov IA64_KR(CURRENT_STACK)=r26 // remember last page we mapped...
123 #endif
124 ;;
125 itr.d dtr[r25]=r23 // wire in new mapping...
126 #ifdef CONFIG_XEN
127 ;;
128 srlz.d
129 mov r9=1
130 movl r8=XSI_PSR_IC
131 ;;
132 st4 [r8]=r9
133 ;;
134 #else
135 ssm psr.ic // reenable the psr.ic bit
136 ;;
137 srlz.d
138 #endif
139 br.cond.sptk .done
140 #ifdef CONFIG_XEN
141 END(xen_switch_to)
142 #else
143 END(ia64_switch_to)
144 #endif
146 /*
147 * Invoke a system call, but do some tracing before and after the call.
148 * We MUST preserve the current register frame throughout this routine
149 * because some system calls (such as ia64_execve) directly
150 * manipulate ar.pfs.
151 */
152 #ifdef CONFIG_XEN
153 GLOBAL_ENTRY(xen_trace_syscall)
154 PT_REGS_UNWIND_INFO(0)
155 movl r16=running_on_xen;;
156 ld4 r16=[r16];;
157 cmp.eq p7,p0=r16,r0
158 (p7) br.cond.sptk.many __ia64_trace_syscall;;
159 #else
160 GLOBAL_ENTRY(ia64_trace_syscall)
161 PT_REGS_UNWIND_INFO(0)
162 #endif
163 /*
164 * We need to preserve the scratch registers f6-f11 in case the system
165 * call is sigreturn.
166 */
167 adds r16=PT(F6)+16,sp
168 adds r17=PT(F7)+16,sp
169 ;;
170 stf.spill [r16]=f6,32
171 stf.spill [r17]=f7,32
172 ;;
173 stf.spill [r16]=f8,32
174 stf.spill [r17]=f9,32
175 ;;
176 stf.spill [r16]=f10
177 stf.spill [r17]=f11
178 br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
179 adds r16=PT(F6)+16,sp
180 adds r17=PT(F7)+16,sp
181 ;;
182 ldf.fill f6=[r16],32
183 ldf.fill f7=[r17],32
184 ;;
185 ldf.fill f8=[r16],32
186 ldf.fill f9=[r17],32
187 ;;
188 ldf.fill f10=[r16]
189 ldf.fill f11=[r17]
190 // the syscall number may have changed, so re-load it and re-calculate the
191 // syscall entry-point:
192 adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #)
193 ;;
194 ld8 r15=[r15]
195 mov r3=NR_syscalls - 1
196 ;;
197 adds r15=-1024,r15
198 movl r16=sys_call_table
199 ;;
200 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
201 cmp.leu p6,p7=r15,r3
202 ;;
203 (p6) ld8 r20=[r20] // load address of syscall entry point
204 (p7) movl r20=sys_ni_syscall
205 ;;
206 mov b6=r20
207 br.call.sptk.many rp=b6 // do the syscall
208 .strace_check_retval:
209 cmp.lt p6,p0=r8,r0 // syscall failed?
210 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
211 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
212 mov r10=0
213 (p6) br.cond.sptk strace_error // syscall failed ->
214 ;; // avoid RAW on r10
215 .strace_save_retval:
216 .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
217 .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
218 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
219 .ret3:
220 (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
221 br.cond.sptk .work_pending_syscall_end
223 strace_error:
224 ld8 r3=[r2] // load pt_regs.r8
225 sub r9=0,r8 // negate return value to get errno value
226 ;;
227 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
228 adds r3=16,r2 // r3=&pt_regs.r10
229 ;;
230 (p6) mov r10=-1
231 (p6) mov r8=r9
232 br.cond.sptk .strace_save_retval
233 #ifdef CONFIG_XEN
234 END(xen_trace_syscall)
235 #else
236 END(ia64_trace_syscall)
237 #endif
239 #ifdef CONFIG_XEN
240 GLOBAL_ENTRY(xen_ret_from_clone)
241 PT_REGS_UNWIND_INFO(0)
242 movl r16=running_on_xen;;
243 ld4 r16=[r16];;
244 cmp.eq p7,p0=r16,r0
245 (p7) br.cond.sptk.many __ia64_ret_from_clone;;
246 #else
247 GLOBAL_ENTRY(ia64_ret_from_clone)
248 PT_REGS_UNWIND_INFO(0)
249 #endif
250 { /*
251 * Some versions of gas generate bad unwind info if the first instruction of a
252 * procedure doesn't go into the first slot of a bundle. This is a workaround.
253 */
254 nop.m 0
255 nop.i 0
256 /*
257 * We need to call schedule_tail() to complete the scheduling process.
258 * Called by ia64_switch_to() after do_fork()->copy_thread(). r8 contains the
259 * address of the previously executing task.
260 */
261 br.call.sptk.many rp=ia64_invoke_schedule_tail
262 }
263 .ret8:
264 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
265 ;;
266 ld4 r2=[r2]
267 ;;
268 mov r8=0
269 and r2=_TIF_SYSCALL_TRACEAUDIT,r2
270 ;;
271 cmp.ne p6,p0=r2,r0
272 (p6) br.cond.spnt .strace_check_retval
273 ;; // added stop bits to prevent r8 dependency
274 #ifdef CONFIG_XEN
275 br.cond.sptk ia64_ret_from_syscall
276 END(xen_ret_from_clone)
277 #else
278 END(ia64_ret_from_clone)
279 #endif
280 /*
281 * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
282 * need to switch to bank 0 and doesn't restore the scratch registers.
283 * To avoid leaking kernel bits, the scratch registers are set to
284 * the following known-to-be-safe values:
285 *
286 * r1: restored (global pointer)
287 * r2: cleared
288 * r3: 1 (when returning to user-level)
289 * r8-r11: restored (syscall return value(s))
290 * r12: restored (user-level stack pointer)
291 * r13: restored (user-level thread pointer)
292 * r14: set to __kernel_syscall_via_epc
293 * r15: restored (syscall #)
294 * r16-r17: cleared
295 * r18: user-level b6
296 * r19: cleared
297 * r20: user-level ar.fpsr
298 * r21: user-level b0
299 * r22: cleared
300 * r23: user-level ar.bspstore
301 * r24: user-level ar.rnat
302 * r25: user-level ar.unat
303 * r26: user-level ar.pfs
304 * r27: user-level ar.rsc
305 * r28: user-level ip
306 * r29: user-level psr
307 * r30: user-level cfm
308 * r31: user-level pr
309 * f6-f11: cleared
310 * pr: restored (user-level pr)
311 * b0: restored (user-level rp)
312 * b6: restored
313 * b7: set to __kernel_syscall_via_epc
314 * ar.unat: restored (user-level ar.unat)
315 * ar.pfs: restored (user-level ar.pfs)
316 * ar.rsc: restored (user-level ar.rsc)
317 * ar.rnat: restored (user-level ar.rnat)
318 * ar.bspstore: restored (user-level ar.bspstore)
319 * ar.fpsr: restored (user-level ar.fpsr)
320 * ar.ccv: cleared
321 * ar.csd: cleared
322 * ar.ssd: cleared
323 */
324 #ifdef CONFIG_XEN
325 GLOBAL_ENTRY(xen_leave_syscall)
326 PT_REGS_UNWIND_INFO(0)
327 movl r22=running_on_xen;;
328 ld4 r22=[r22];;
329 cmp.eq p7,p0=r22,r0
330 (p7) br.cond.sptk.many __ia64_leave_syscall;;
331 #else
332 ENTRY(ia64_leave_syscall)
333 PT_REGS_UNWIND_INFO(0)
334 #endif
335 /*
336 * work.need_resched etc. mustn't get changed by this CPU before it returns to
337 * user- or fsys-mode, hence we disable interrupts early on.
338 *
339 * p6 controls whether current_thread_info()->flags needs to be check for
340 * extra work. We always check for extra work when returning to user-level.
341 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
342 * is 0. After extra work processing has been completed, execution
343 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
344 * needs to be redone.
345 */
346 #ifdef CONFIG_PREEMPT
347 rsm psr.i // disable interrupts
348 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
349 (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
350 ;;
351 .pred.rel.mutex pUStk,pKStk
352 (pKStk) ld4 r21=[r20] // r21 <- preempt_count
353 (pUStk) mov r21=0 // r21 <- 0
354 ;;
355 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
356 #else /* !CONFIG_PREEMPT */
357 #ifdef CONFIG_XEN
358 movl r2=XSI_PSR_I_ADDR
359 mov r18=1
360 ;;
361 ld8 r2=[r2]
362 ;;
363 (pUStk) st1 [r2]=r18
364 #else
365 (pUStk) rsm psr.i
366 #endif
367 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
368 (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
369 #endif
370 .work_processed_syscall:
371 adds r2=PT(LOADRS)+16,r12
372 adds r3=PT(AR_BSPSTORE)+16,r12
373 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
374 ;;
375 (p6) ld4 r31=[r18] // load current_thread_info()->flags
376 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
377 nop.i 0
378 ;;
379 mov r16=ar.bsp // M2 get existing backing store pointer
380 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
381 (p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
382 ;;
383 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
384 (p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
385 (p6) br.cond.spnt .work_pending_syscall
386 ;;
387 // start restoring the state saved on the kernel stack (struct pt_regs):
388 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
389 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
390 (pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
391 ;;
392 invala // M0|1 invalidate ALAT
393 #ifdef CONFIG_XEN
394 movl r28=XSI_PSR_I_ADDR
395 movl r29=XSI_PSR_IC
396 ;;
397 ld8 r28=[r28]
398 mov r30=1
399 ;;
400 st1 [r28]=r30
401 st4 [r29]=r0 // note: clears both vpsr.i and vpsr.ic!
402 ;;
403 #else
404 rsm psr.i | psr.ic // M2 turn off interrupts and interruption collection
405 #endif
406 cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
408 ld8 r29=[r2],16 // M0|1 load cr.ipsr
409 ld8 r28=[r3],16 // M0|1 load cr.iip
410 mov r22=r0 // A clear r22
411 ;;
412 ld8 r30=[r2],16 // M0|1 load cr.ifs
413 ld8 r25=[r3],16 // M0|1 load ar.unat
414 (pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
415 ;;
416 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
417 #ifdef CONFIG_XEN
418 (pKStk) mov r21=r8
419 (pKStk) XEN_HYPER_GET_PSR
420 ;;
421 (pKStk) mov r22=r8
422 (pKStk) mov r8=r21
423 ;;
424 #else
425 (pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled
426 #endif
427 nop 0
428 ;;
429 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
430 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
431 mov f6=f0 // F clear f6
432 ;;
433 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
434 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
435 mov f7=f0 // F clear f7
436 ;;
437 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
438 ld8.fill r1=[r3],16 // M0|1 load r1
439 (pUStk) mov r17=1 // A
440 ;;
441 (pUStk) st1 [r14]=r17 // M2|3
442 ld8.fill r13=[r3],16 // M0|1
443 mov f8=f0 // F clear f8
444 ;;
445 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
446 ld8.fill r15=[r3] // M0|1 restore r15
447 mov b6=r18 // I0 restore b6
449 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0 // A
450 mov f9=f0 // F clear f9
451 (pKStk) br.cond.dpnt.many skip_rbs_switch // B
453 srlz.d // M0 ensure interruption collection is off (for cover)
454 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
455 #ifdef CONFIG_XEN
456 XEN_HYPER_COVER;
457 #else
458 cover // B add current frame into dirty partition & set cr.ifs
459 #endif
460 ;;
461 (pUStk) ld4 r17=[r17] // M0|1 r17 = cpu_data->phys_stacked_size_p8
462 mov r19=ar.bsp // M2 get new backing store pointer
463 mov f10=f0 // F clear f10
465 nop.m 0
466 movl r14=__kernel_syscall_via_epc // X
467 ;;
468 mov.m ar.csd=r0 // M2 clear ar.csd
469 mov.m ar.ccv=r0 // M2 clear ar.ccv
470 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
472 mov.m ar.ssd=r0 // M2 clear ar.ssd
473 mov f11=f0 // F clear f11
474 br.cond.sptk.many rbs_switch // B
475 #ifdef CONFIG_XEN
476 END(xen_leave_syscall)
477 #else
478 END(ia64_leave_syscall)
479 #endif
481 #ifdef CONFIG_XEN
482 GLOBAL_ENTRY(xen_leave_kernel)
483 PT_REGS_UNWIND_INFO(0)
484 movl r22=running_on_xen;;
485 ld4 r22=[r22];;
486 cmp.eq p7,p0=r22,r0
487 (p7) br.cond.sptk.many __ia64_leave_kernel;;
488 #else
489 GLOBAL_ENTRY(ia64_leave_kernel)
490 PT_REGS_UNWIND_INFO(0)
491 #endif
492 /*
493 * work.need_resched etc. mustn't get changed by this CPU before it returns to
494 * user- or fsys-mode, hence we disable interrupts early on.
495 *
496 * p6 controls whether current_thread_info()->flags needs to be check for
497 * extra work. We always check for extra work when returning to user-level.
498 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
499 * is 0. After extra work processing has been completed, execution
500 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
501 * needs to be redone.
502 */
503 #ifdef CONFIG_PREEMPT
504 rsm psr.i // disable interrupts
505 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
506 (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
507 ;;
508 .pred.rel.mutex pUStk,pKStk
509 (pKStk) ld4 r21=[r20] // r21 <- preempt_count
510 (pUStk) mov r21=0 // r21 <- 0
511 ;;
512 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
513 #else
514 #ifdef CONFIG_XEN
515 (pUStk) movl r17=XSI_PSR_I_ADDR
516 (pUStk) mov r31=1
517 ;;
518 (pUStk) ld8 r17=[r17]
519 ;;
520 (pUStk) st1 [r17]=r31
521 ;;
522 #else
523 (pUStk) rsm psr.i
524 #endif
525 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
526 (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
527 #endif
528 .work_processed_kernel:
529 adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
530 ;;
531 (p6) ld4 r31=[r17] // load current_thread_info()->flags
532 adds r21=PT(PR)+16,r12
533 ;;
535 lfetch [r21],PT(CR_IPSR)-PT(PR)
536 adds r2=PT(B6)+16,r12
537 adds r3=PT(R16)+16,r12
538 ;;
539 lfetch [r21]
540 ld8 r28=[r2],8 // load b6
541 adds r29=PT(R24)+16,r12
543 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
544 adds r30=PT(AR_CCV)+16,r12
545 (p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
546 ;;
547 ld8.fill r24=[r29]
548 ld8 r15=[r30] // load ar.ccv
549 (p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending?
550 ;;
551 ld8 r29=[r2],16 // load b7
552 ld8 r30=[r3],16 // load ar.csd
553 (p6) br.cond.spnt .work_pending
554 ;;
555 ld8 r31=[r2],16 // load ar.ssd
556 ld8.fill r8=[r3],16
557 ;;
558 ld8.fill r9=[r2],16
559 ld8.fill r10=[r3],PT(R17)-PT(R10)
560 ;;
561 ld8.fill r11=[r2],PT(R18)-PT(R11)
562 ld8.fill r17=[r3],16
563 ;;
564 ld8.fill r18=[r2],16
565 ld8.fill r19=[r3],16
566 ;;
567 ld8.fill r20=[r2],16
568 ld8.fill r21=[r3],16
569 mov ar.csd=r30
570 mov ar.ssd=r31
571 ;;
572 #ifdef CONFIG_XEN
573 movl r23=XSI_PSR_I_ADDR
574 movl r22=XSI_PSR_IC
575 ;;
576 ld8 r23=[r23]
577 mov r25=1
578 ;;
579 st1 [r23]=r25
580 st4 [r22]=r0 // note: clears both vpsr.i and vpsr.ic!
581 ;;
582 #else
583 rsm psr.i | psr.ic // initiate turning off of interrupt and interruption collection
584 #endif
585 invala // invalidate ALAT
586 ;;
587 ld8.fill r22=[r2],24
588 ld8.fill r23=[r3],24
589 mov b6=r28
590 ;;
591 ld8.fill r25=[r2],16
592 ld8.fill r26=[r3],16
593 mov b7=r29
594 ;;
595 ld8.fill r27=[r2],16
596 ld8.fill r28=[r3],16
597 ;;
598 ld8.fill r29=[r2],16
599 ld8.fill r30=[r3],24
600 ;;
601 ld8.fill r31=[r2],PT(F9)-PT(R31)
602 adds r3=PT(F10)-PT(F6),r3
603 ;;
604 ldf.fill f9=[r2],PT(F6)-PT(F9)
605 ldf.fill f10=[r3],PT(F8)-PT(F10)
606 ;;
607 ldf.fill f6=[r2],PT(F7)-PT(F6)
608 ;;
609 ldf.fill f7=[r2],PT(F11)-PT(F7)
610 ldf.fill f8=[r3],32
611 ;;
612 srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
613 mov ar.ccv=r15
614 ;;
615 ldf.fill f11=[r2]
616 #ifdef CONFIG_XEN
617 ;;
618 // r16-r31 all now hold bank1 values
619 movl r2=XSI_BANK1_R16
620 movl r3=XSI_BANK1_R16+8
621 ;;
622 .mem.offset 0,0; st8.spill [r2]=r16,16
623 .mem.offset 8,0; st8.spill [r3]=r17,16
624 ;;
625 .mem.offset 0,0; st8.spill [r2]=r18,16
626 .mem.offset 8,0; st8.spill [r3]=r19,16
627 ;;
628 .mem.offset 0,0; st8.spill [r2]=r20,16
629 .mem.offset 8,0; st8.spill [r3]=r21,16
630 ;;
631 .mem.offset 0,0; st8.spill [r2]=r22,16
632 .mem.offset 8,0; st8.spill [r3]=r23,16
633 ;;
634 .mem.offset 0,0; st8.spill [r2]=r24,16
635 .mem.offset 8,0; st8.spill [r3]=r25,16
636 ;;
637 .mem.offset 0,0; st8.spill [r2]=r26,16
638 .mem.offset 8,0; st8.spill [r3]=r27,16
639 ;;
640 .mem.offset 0,0; st8.spill [r2]=r28,16
641 .mem.offset 8,0; st8.spill [r3]=r29,16
642 ;;
643 .mem.offset 0,0; st8.spill [r2]=r30,16
644 .mem.offset 8,0; st8.spill [r3]=r31,16
645 ;;
646 movl r2=XSI_BANKNUM;;
647 st4 [r2]=r0;
648 #else
649 bsw.0 // switch back to bank 0 (no stop bit required beforehand...)
650 #endif
651 ;;
652 (pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency)
653 adds r16=PT(CR_IPSR)+16,r12
654 adds r17=PT(CR_IIP)+16,r12
656 #ifdef CONFIG_XEN
657 (pKStk) mov r29=r8
658 (pKStk) XEN_HYPER_GET_PSR
659 ;;
660 (pKStk) mov r22=r8
661 (pKStk) mov r8=r29
662 ;;
663 #else
664 (pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled
665 #endif
666 nop.i 0
667 nop.i 0
668 ;;
669 ld8 r29=[r16],16 // load cr.ipsr
670 ld8 r28=[r17],16 // load cr.iip
671 ;;
672 ld8 r30=[r16],16 // load cr.ifs
673 ld8 r25=[r17],16 // load ar.unat
674 ;;
675 ld8 r26=[r16],16 // load ar.pfs
676 ld8 r27=[r17],16 // load ar.rsc
677 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
678 ;;
679 ld8 r24=[r16],16 // load ar.rnat (may be garbage)
680 ld8 r23=[r17],16 // load ar.bspstore (may be garbage)
681 ;;
682 ld8 r31=[r16],16 // load predicates
683 ld8 r21=[r17],16 // load b0
684 ;;
685 ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
686 ld8.fill r1=[r17],16 // load r1
687 ;;
688 ld8.fill r12=[r16],16
689 ld8.fill r13=[r17],16
690 (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
691 ;;
692 ld8 r20=[r16],16 // ar.fpsr
693 ld8.fill r15=[r17],16
694 ;;
695 ld8.fill r14=[r16],16
696 ld8.fill r2=[r17]
697 (pUStk) mov r17=1
698 ;;
699 ld8.fill r3=[r16]
700 (pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
701 shr.u r18=r19,16 // get byte size of existing "dirty" partition
702 ;;
703 mov r16=ar.bsp // get existing backing store pointer
704 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0
705 ;;
706 ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8
707 (pKStk) br.cond.dpnt skip_rbs_switch
709 /*
710 * Restore user backing store.
711 *
712 * NOTE: alloc, loadrs, and cover can't be predicated.
713 */
714 (pNonSys) br.cond.dpnt dont_preserve_current_frame
716 #ifdef CONFIG_XEN
717 XEN_HYPER_COVER;
718 #else
719 cover // add current frame into dirty partition and set cr.ifs
720 #endif
721 ;;
722 mov r19=ar.bsp // get new backing store pointer
723 rbs_switch:
724 sub r16=r16,r18 // krbs = old bsp - size of dirty partition
725 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
726 ;;
727 sub r19=r19,r16 // calculate total byte size of dirty partition
728 add r18=64,r18 // don't force in0-in7 into memory...
729 ;;
730 shl r19=r19,16 // shift size of dirty partition into loadrs position
731 ;;
732 dont_preserve_current_frame:
733 /*
734 * To prevent leaking bits between the kernel and user-space,
735 * we must clear the stacked registers in the "invalid" partition here.
736 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
737 * 5 registers/cycle on McKinley).
738 */
739 # define pRecurse p6
740 # define pReturn p7
741 #ifdef CONFIG_ITANIUM
742 # define Nregs 10
743 #else
744 # define Nregs 14
745 #endif
746 alloc loc0=ar.pfs,2,Nregs-2,2,0
747 shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
748 sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
749 ;;
750 mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
751 shladd in0=loc1,3,r17
752 mov in1=0
753 ;;
754 TEXT_ALIGN(32)
755 rse_clear_invalid:
756 #ifdef CONFIG_ITANIUM
757 // cycle 0
758 { .mii
759 alloc loc0=ar.pfs,2,Nregs-2,2,0
760 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
761 add out0=-Nregs*8,in0
762 }{ .mfb
763 add out1=1,in1 // increment recursion count
764 nop.f 0
765 nop.b 0 // can't do br.call here because of alloc (WAW on CFM)
766 ;;
767 }{ .mfi // cycle 1
768 mov loc1=0
769 nop.f 0
770 mov loc2=0
771 }{ .mib
772 mov loc3=0
773 mov loc4=0
774 (pRecurse) br.call.sptk.many b0=rse_clear_invalid
776 }{ .mfi // cycle 2
777 mov loc5=0
778 nop.f 0
779 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
780 }{ .mib
781 mov loc6=0
782 mov loc7=0
783 (pReturn) br.ret.sptk.many b0
784 }
785 #else /* !CONFIG_ITANIUM */
786 alloc loc0=ar.pfs,2,Nregs-2,2,0
787 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
788 add out0=-Nregs*8,in0
789 add out1=1,in1 // increment recursion count
790 mov loc1=0
791 mov loc2=0
792 ;;
793 mov loc3=0
794 mov loc4=0
795 mov loc5=0
796 mov loc6=0
797 mov loc7=0
798 (pRecurse) br.call.dptk.few b0=rse_clear_invalid
799 ;;
800 mov loc8=0
801 mov loc9=0
802 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
803 mov loc10=0
804 mov loc11=0
805 (pReturn) br.ret.dptk.many b0
806 #endif /* !CONFIG_ITANIUM */
807 # undef pRecurse
808 # undef pReturn
809 ;;
810 alloc r17=ar.pfs,0,0,0,0 // drop current register frame
811 ;;
812 loadrs
813 ;;
814 skip_rbs_switch:
815 mov ar.unat=r25 // M2
816 (pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22
817 (pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise
818 ;;
819 (pUStk) mov ar.bspstore=r23 // M2
820 (pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp
821 (pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise
822 ;;
823 #ifdef CONFIG_XEN
824 movl r25=XSI_IPSR
825 ;;
826 st8[r25]=r29,XSI_IFS_OFS-XSI_IPSR_OFS
827 ;;
828 #else
829 mov cr.ipsr=r29 // M2
830 #endif
831 mov ar.pfs=r26 // I0
832 (pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise
834 #ifdef CONFIG_XEN
835 (p9) st8 [r25]=r30
836 ;;
837 adds r25=XSI_IIP_OFS-XSI_IFS_OFS,r25
838 ;;
839 #else
840 (p9) mov cr.ifs=r30 // M2
841 #endif
842 mov b0=r21 // I0
843 (pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise
845 mov ar.fpsr=r20 // M2
846 #ifdef CONFIG_XEN
847 st8 [r25]=r28
848 #else
849 mov cr.iip=r28 // M2
850 #endif
851 nop 0
852 ;;
853 (pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode
854 nop 0
855 (pLvSys)mov r2=r0
857 mov ar.rsc=r27 // M2
858 mov pr=r31,-1 // I0
859 #ifdef CONFIG_XEN
860 ;;
861 XEN_HYPER_RFI;
862 #else
863 rfi // B
864 #endif
866 /*
867 * On entry:
868 * r20 = &current->thread_info->pre_count (if CONFIG_PREEMPT)
869 * r31 = current->thread_info->flags
870 * On exit:
871 * p6 = TRUE if work-pending-check needs to be redone
872 */
873 .work_pending_syscall:
874 add r2=-8,r2
875 add r3=-8,r3
876 ;;
877 st8 [r2]=r8
878 st8 [r3]=r10
879 .work_pending:
880 tbit.z p6,p0=r31,TIF_NEED_RESCHED // current_thread_info()->need_resched==0?
881 (p6) br.cond.sptk.few .notify
882 #ifdef CONFIG_PREEMPT
883 (pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
884 ;;
885 (pKStk) st4 [r20]=r21
886 ssm psr.i // enable interrupts
887 #endif
888 br.call.spnt.many rp=schedule
889 .ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1
890 #ifdef CONFIG_XEN
891 movl r2=XSI_PSR_I_ADDR
892 mov r20=1
893 ;;
894 ld8 r2=[r2]
895 ;;
896 st1 [r2]=r20
897 #else
898 rsm psr.i // disable interrupts
899 #endif
900 ;;
901 #ifdef CONFIG_PREEMPT
902 (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
903 ;;
904 (pKStk) st4 [r20]=r0 // preempt_count() <- 0
905 #endif
906 (pLvSys)br.cond.sptk.few .work_pending_syscall_end
907 br.cond.sptk.many .work_processed_kernel // re-check
909 .notify:
910 (pUStk) br.call.spnt.many rp=notify_resume_user
911 .ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0
912 (pLvSys)br.cond.sptk.few .work_pending_syscall_end
913 br.cond.sptk.many .work_processed_kernel // don't re-check
915 .work_pending_syscall_end:
916 adds r2=PT(R8)+16,r12
917 adds r3=PT(R10)+16,r12
918 ;;
919 ld8 r8=[r2]
920 ld8 r10=[r3]
921 br.cond.sptk.many .work_processed_syscall // re-check
923 #ifdef CONFIG_XEN
924 END(xen_leave_kernel)
925 #else
926 END(ia64_leave_kernel)
927 #endif